From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CD56CA04DB; Thu, 15 Oct 2020 17:27:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 006A01EAE5; Thu, 15 Oct 2020 17:23:58 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 15F3E1EAD5 for ; Thu, 15 Oct 2020 17:23:55 +0200 (CEST) IronPort-SDR: NbUW7o/qFO6NnxSeouZCOrLfUR6ePT9CFWMSHrJppjvCEwtjp6Js6jP5xWdluzb3kAcWe/2t1F +bwl3fTLyPCw== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909192" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909192" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:55 -0700 IronPort-SDR: n8V0sbcQHuGOtoofuhzZVtIGBw7TJCzvx56b7IIseC11BFoRt6RjhLTUiGSyziC7VqFYqBQ4Vt LdRTlczTlBpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151921" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:51 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Wei Zhao , Jeff Guo , Haiyue Wang Date: Thu, 15 Oct 2020 16:22:51 +0100 Message-Id: <20201015152259.97562-11-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v7 10/18] net/ixgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Wei Zhao Cc: Jeff Guo Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev Reviewed-by: Haiyue Wang --- v4: - Updated enum name. - Moved placement of condition check. - Added condition check to tx cleanup path selection. --- drivers/net/ixgbe/ixgbe_rxtx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 29d385c062..3141398e10 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -2405,6 +2405,7 @@ ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) #endif txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST) { if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128 && (rte_eal_process_type() != RTE_PROC_PRIMARY || txq->sw_ring_v != NULL)) { return ixgbe_tx_done_cleanup_vec(txq, free_cnt); @@ -2503,6 +2504,7 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq) PMD_INIT_LOG(DEBUG, "Using simple tx code path"); dev->tx_pkt_prepare = NULL; if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128 && (rte_eal_process_type() != RTE_PROC_PRIMARY || ixgbe_txq_vec_setup(txq) == 0)) { PMD_INIT_LOG(DEBUG, "Vector tx enabled."); @@ -4744,7 +4746,8 @@ ixgbe_set_rx_function(struct rte_eth_dev *dev) * conditions to be met and Rx Bulk Allocation should be allowed. */ if (ixgbe_rx_vec_dev_conf_condition_check(dev) || - !adapter->rx_bulk_alloc_allowed) { + !adapter->rx_bulk_alloc_allowed || + rte_get_max_simd_bitwidth() < RTE_SIMD_128) { PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx " "preconditions", dev->data->port_id); -- 2.22.0