From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66929A04DD; Wed, 28 Oct 2020 04:23:10 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D6DD4A8E9; Wed, 28 Oct 2020 04:19:57 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id F16626CAC for ; Wed, 28 Oct 2020 04:19:49 +0100 (CET) IronPort-SDR: KcqZzFik0pcoinRmFJO4B4HRXqejSfljY3Y1yDOU25wktVM+21YJINNpcajQ0iYoen6LQBLw24 bqfwBctaUfag== X-IronPort-AV: E=McAfee;i="6000,8403,9787"; a="148052793" X-IronPort-AV: E=Sophos;i="5.77,425,1596524400"; d="scan'208";a="148052793" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 20:19:49 -0700 IronPort-SDR: 4pExHMva6FGNa/PfgXf6TsyqCs0w104JBChoRtII8lrN7zwBA9L7cQcfEfBXWhszb2O6YA03Cb 3MWySWHN9uPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,425,1596524400"; d="scan'208";a="526174461" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga005.fm.intel.com with ESMTP; 27 Oct 2020 20:19:47 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Amir Shay Date: Wed, 28 Oct 2020 11:23:10 +0800 Message-Id: <20201028032320.1755208-12-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20201028032320.1755208-1-qi.z.zhang@intel.com> References: <20201028032320.1755208-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 11/21] net/ice/base: add support for class 5+ modules X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently QSFP/SFP modules up to power class 4 are supported. 100G modules require higher power in many cases. Also, low power mode requires support of power classes 7 and even 8. This change extends "Get Link Status" AQ command (0x0607) to support class 5+ modules. The patch also add couple other missing bits for link status. Signed-off-by: Amir Shay Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index cadd6df384..3b75cf577a 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1442,6 +1442,10 @@ struct ice_aqc_get_link_status_data { #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) u8 link_cfg_err; #define ICE_AQ_LINK_CFG_ERR BIT(0) +#define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) +#define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) +#define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) +#define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) u8 link_info; #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ #define ICE_AQ_LINK_FAULT BIT(1) @@ -1489,7 +1493,7 @@ struct ice_aqc_get_link_status_data { #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M /* External Device Power Ability */ u8 power_desc; -#define ICE_AQ_PWR_CLASS_M 0x3 +#define ICE_AQ_PWR_CLASS_M 0x3F #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 -- 2.25.4