From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id ECDA6A09D3; Thu, 12 Nov 2020 11:32:16 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2E1A15928; Thu, 12 Nov 2020 11:32:15 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 48D7B56A3; Thu, 12 Nov 2020 11:32:13 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B88C9139F; Thu, 12 Nov 2020 02:32:11 -0800 (PST) Received: from net-arm-kp920-01.shanghai.arm.com (net-arm-kp920-01.shanghai.arm.com [10.169.210.104]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 00E7B3F73C; Thu, 12 Nov 2020 02:32:08 -0800 (PST) From: Ruifeng Wang To: Jerin Jacob , Ruifeng Wang , David Marchand , Honnappa Nagarahalli , Phil Yang Cc: dev@dpdk.org, nd@arm.com, stable@dpdk.org Date: Thu, 12 Nov 2020 18:31:57 +0800 Message-Id: <20201112103157.53486-1-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v1] eal/arm: fix clang build of native target X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When doing Clang build with '-mcpu=native' on N1 platform, build failed with: ../lib/librte_eal/arm/include/rte_atomic_64.h:76:39: error: instruction requires: lse __ATOMIC128_CAS_OP(__cas_128_release, "caspl") This is because native detection for Neoverse N1 was added in Clang-11. Prior version of Clang's assembler doesn't know LSE support on hardware. Fixed this for Clang earlier than version 11 by specifying architecture for assembler. Referred to [1] for this fix. Fixes: 7e2c3e17fe2c ("eal/arm64: add 128-bit atomic compare exchange") Cc: stable@dpdk.org [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e0d5896bd356cd577f9710a02d7a474cdf58426b Signed-off-by: Ruifeng Wang --- lib/librte_eal/arm/include/rte_atomic_64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h index 2cef88629..7fcd17466 100644 --- a/lib/librte_eal/arm/include/rte_atomic_64.h +++ b/lib/librte_eal/arm/include/rte_atomic_64.h @@ -46,6 +46,8 @@ rte_atomic_thread_fence(int memorder) /*------------------------ 128 bit atomic operations -------------------------*/ #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS) +#define __LSE_PREAMBLE ".arch armv8-a+lse\n" + #define __ATOMIC128_CAS_OP(cas_op_name, op_string) \ static __rte_noinline rte_int128_t \ cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated) \ @@ -59,6 +61,7 @@ cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated) \ register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0]; \ register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1]; \ asm volatile( \ + __LSE_PREAMBLE \ op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]" \ : [old0] "+r" (x0), \ [old1] "+r" (x1) \ @@ -76,6 +79,7 @@ __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa") __ATOMIC128_CAS_OP(__cas_128_release, "caspl") __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal") +#undef __LSE_PREAMBLE #undef __ATOMIC128_CAS_OP #endif -- 2.20.1