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From: Timothy McDaniel <timothy.mcdaniel@intel.com>
To: dev@dpdk.org
Cc: jerinj@marvell.com, harry.van.haaren@intel.com, mdr@ashroe.eu,
nhorman@tuxdriver.com, nikhil.rao@intel.com, erik.g.carrillo@intel.com,
abhinandan.gujjar@intel.com, pbhagavatula@marvell.com,
hemant.agrawal@nxp.com, mattias.ronnblom@ericsson.com,
peter.mccarthy@intel.com
Date: Tue, 16 Mar 2021 17:18:49 -0500
Message-Id: <20210316221857.2254-18-timothy.mcdaniel@intel.com>
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Subject: [dpdk-dev] [PATCH 17/25] event/dlb2: add DLB v2.5 support to
sequence number management
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Update sequence number management functions for DLB v2.5,
accounting for new combined register map and hardware access macros.
Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
drivers/event/dlb2/pf/base/dlb2_resource.c | 1 +
drivers/event/dlb2/pf/base/dlb2_resource.h | 4 +-
.../event/dlb2/pf/base/dlb2_resource_new.c | 105 ++++++++++++++++++
3 files changed, 108 insertions(+), 2 deletions(-)
diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c
index 1759cee6b..bd1404f33 100644
--- a/drivers/event/dlb2/pf/base/dlb2_resource.c
+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c
@@ -242,3 +242,4 @@ int dlb2_hw_get_ldb_queue_depth(struct dlb2_hw *hw,
return 0;
}
+
diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.h b/drivers/event/dlb2/pf/base/dlb2_resource.h
index 2e13193bb..00a0b6b57 100644
--- a/drivers/event/dlb2/pf/base/dlb2_resource.h
+++ b/drivers/event/dlb2/pf/base/dlb2_resource.h
@@ -792,8 +792,8 @@ int dlb2_get_group_sequence_number_occupancy(struct dlb2_hw *hw,
* ordered queue is configured.
*/
int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,
- unsigned int group_id,
- unsigned long val);
+ u32 group_id,
+ u32 val);
/**
* dlb2_reset_domain() - reset a scheduling domain
diff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c
index f147937c0..9e4e49583 100644
--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c
+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c
@@ -6129,3 +6129,108 @@ void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)
DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, ctrl);
}
+/**
+ * dlb2_get_group_sequence_numbers() - return a group's number of SNs per queue
+ * @hw: dlb2_hw handle for a particular device.
+ * @group_id: sequence number group ID.
+ *
+ * This function returns the configured number of sequence numbers per queue
+ * for the specified group.
+ *
+ * Return:
+ * Returns -EINVAL if group_id is invalid, else the group's SNs per queue.
+ */
+int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw, u32 group_id)
+{
+ if (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)
+ return -EINVAL;
+
+ return hw->rsrcs.sn_groups[group_id].sequence_numbers_per_queue;
+}
+
+/**
+ * dlb2_get_group_sequence_number_occupancy() - return a group's in-use slots
+ * @hw: dlb2_hw handle for a particular device.
+ * @group_id: sequence number group ID.
+ *
+ * This function returns the group's number of in-use slots (i.e. load-balanced
+ * queues using the specified group).
+ *
+ * Return:
+ * Returns -EINVAL if group_id is invalid, else the group's SNs per queue.
+ */
+int dlb2_get_group_sequence_number_occupancy(struct dlb2_hw *hw, u32 group_id)
+{
+ if (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)
+ return -EINVAL;
+
+ return dlb2_sn_group_used_slots(&hw->rsrcs.sn_groups[group_id]);
+}
+
+static void dlb2_log_set_group_sequence_numbers(struct dlb2_hw *hw,
+ u32 group_id,
+ u32 val)
+{
+ DLB2_HW_DBG(hw, "DLB2 set group sequence numbers:\n");
+ DLB2_HW_DBG(hw, "\tGroup ID: %u\n", group_id);
+ DLB2_HW_DBG(hw, "\tValue: %u\n", val);
+}
+
+/**
+ * dlb2_set_group_sequence_numbers() - assign a group's number of SNs per queue
+ * @hw: dlb2_hw handle for a particular device.
+ * @group_id: sequence number group ID.
+ * @val: requested amount of sequence numbers per queue.
+ *
+ * This function configures the group's number of sequence numbers per queue.
+ * val can be a power-of-two between 32 and 1024, inclusive. This setting can
+ * be configured until the first ordered load-balanced queue is configured, at
+ * which point the configuration is locked.
+ *
+ * Return:
+ * Returns 0 upon success; -EINVAL if group_id or val is invalid, -EPERM if an
+ * ordered queue is configured.
+ */
+int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,
+ u32 group_id,
+ u32 val)
+{
+ const u32 valid_allocations[] = {64, 128, 256, 512, 1024};
+ struct dlb2_sn_group *group;
+ u32 sn_mode = 0;
+ int mode;
+
+ if (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)
+ return -EINVAL;
+
+ group = &hw->rsrcs.sn_groups[group_id];
+
+ /*
+ * Once the first load-balanced queue using an SN group is configured,
+ * the group cannot be changed.
+ */
+ if (group->slot_use_bitmap != 0)
+ return -EPERM;
+
+ for (mode = 0; mode < DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES; mode++)
+ if (val == valid_allocations[mode])
+ break;
+
+ if (mode == DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES)
+ return -EINVAL;
+
+ group->mode = mode;
+ group->sequence_numbers_per_queue = val;
+
+ DLB2_BITS_SET(sn_mode, hw->rsrcs.sn_groups[0].mode,
+ DLB2_RO_GRP_SN_MODE_SN_MODE_0);
+ DLB2_BITS_SET(sn_mode, hw->rsrcs.sn_groups[1].mode,
+ DLB2_RO_GRP_SN_MODE_SN_MODE_1);
+
+ DLB2_CSR_WR(hw, DLB2_RO_GRP_SN_MODE(hw->ver), sn_mode);
+
+ dlb2_log_set_group_sequence_numbers(hw, group_id, val);
+
+ return 0;
+}
+
--
2.23.0