From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8AAD7A0561; Thu, 18 Mar 2021 08:19:22 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 33D6A140ED3; Thu, 18 Mar 2021 08:19:05 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 52831140ECE for ; Thu, 18 Mar 2021 08:19:03 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C41F9ED1; Thu, 18 Mar 2021 00:19:02 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.125]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 26C513F718; Thu, 18 Mar 2021 00:18:59 -0700 (PDT) From: Feifei Wang To: Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko Cc: dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang , Honnappa Nagarahalli Date: Thu, 18 Mar 2021 15:18:40 +0800 Message-Id: <20210318071840.359957-5-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210318071840.359957-1-feifei.wang2@arm.com> References: <20210318071840.359957-1-feifei.wang2@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v1 4/4] net/mlx5: replace SMP barriers with C11 barriers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Replace SMP barrier with atomic thread fence. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli --- drivers/net/mlx5/mlx5_mr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c index 7ce1d3e64..650fe9093 100644 --- a/drivers/net/mlx5/mlx5_mr.c +++ b/drivers/net/mlx5/mlx5_mr.c @@ -109,11 +109,11 @@ mlx5_mr_mem_event_free_cb(struct mlx5_dev_ctx_shared *sh, /* * Flush local caches by propagating invalidation across cores. - * rte_smp_wmb() is to keep the order that dev_gen updated before + * release-fence is to keep the order that dev_gen updated before * rebuilding global cache. Therefore, other core can flush their * local cache on time. */ - rte_smp_wmb(); + rte_atomic_thread_fence(__ATOMIC_RELEASE); mlx5_mr_rebuild_cache(&sh->share_cache); } rte_rwlock_write_unlock(&sh->share_cache.rwlock); @@ -412,11 +412,11 @@ mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, /* * Flush local caches by propagating invalidation across cores. - * rte_smp_wmb() is to keep the order that dev_gen updated before + * release-fence is to keep the order that dev_gen updated before * rebuilding global cache. Therefore, other core can flush their * local cache on time. */ - rte_smp_wmb(); + rte_atomic_thread_fence(__ATOMIC_RELEASE); mlx5_mr_rebuild_cache(&sh->share_cache); rte_rwlock_read_unlock(&sh->share_cache.rwlock); return 0; -- 2.25.1