From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D43AA034F; Tue, 30 Mar 2021 03:39:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 60E55140F04; Tue, 30 Mar 2021 03:39:39 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id A4459140F0A for ; Tue, 30 Mar 2021 03:39:33 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from suanmingm@nvidia.com) with SMTP; 30 Mar 2021 04:39:29 +0300 Received: from nvidia.com (mtbc-r640-03.mtbc.labs.mlnx [10.75.70.8]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12U1dLb1018771; Tue, 30 Mar 2021 04:39:28 +0300 From: Suanming Mou To: orika@nvidia.com Cc: dev@dpdk.org, viacheslavo@nvidia.com, matan@nvidia.com, rasland@nvidia.com, John Hurley Date: Tue, 30 Mar 2021 04:39:16 +0300 Message-Id: <20210330013916.1319266-5-suanmingm@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210330013916.1319266-1-suanmingm@nvidia.com> References: <20210309235732.3952418-1-suanmingm@nvidia.com> <20210330013916.1319266-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 4/4] regex/mlx5: prevent wrong calculation of free sqs in umr mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: John Hurley A recent change adds support for scattered mbuf and UMR support for regex. Part of this commit makes the pi and ci counters of the regex_sq a quarter of the length in non umr mode, effectively moving them from 16 bits to 14. The new get_free method casts the difference in pi and ci to a 16 bit value when calculating the free send queues, accounting for any wrapping when pi has looped back to 0 but ci has not yet. However, the move to 14 bits while still casting to 16 can now lead to corrupted, large values returned. Modify the get_free function to take in the has_umr flag and, accordingly, account for wrapping on either 14 or 16 bit pi/ci difference. Fixes: d55c9f637263 ("regex/mlx5: add data path scattered mbuf process") Signed-off-by: John Hurley Acked-by: Ori Kam --- drivers/regex/mlx5/mlx5_regex_fastpath.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index 4f9402c583..b57e7d7794 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -192,8 +192,10 @@ send_doorbell(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq) } static inline int -get_free(struct mlx5_regex_sq *sq) { - return (sq_size_get(sq) - (uint16_t)(sq->pi - sq->ci)); +get_free(struct mlx5_regex_sq *sq, uint8_t has_umr) { + return (sq_size_get(sq) - ((sq->pi - sq->ci) & + (has_umr ? (MLX5_REGEX_MAX_WQE_INDEX >> 2) : + MLX5_REGEX_MAX_WQE_INDEX))); } static inline uint32_t @@ -385,7 +387,7 @@ mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, while ((sqid = ffs(queue->free_sqs))) { sqid--; /* ffs returns 1 for bit 0 */ sq = &queue->sqs[sqid]; - nb_desc = get_free(sq); + nb_desc = get_free(sq, priv->has_umr); if (nb_desc) { /* The ops be handled can't exceed nb_ops. */ if (nb_desc > nb_left) @@ -418,7 +420,7 @@ mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, while ((sqid = ffs(queue->free_sqs))) { sqid--; /* ffs returns 1 for bit 0 */ sq = &queue->sqs[sqid]; - while (get_free(sq)) { + while (get_free(sq, priv->has_umr)) { job_id = job_id_get(sqid, sq_size_get(sq), sq->pi); prep_one(priv, queue, sq, ops[i], &queue->jobs[job_id]); i++; -- 2.25.1