From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 54290A0546; Wed, 7 Apr 2021 03:14:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3D69E140FF9; Wed, 7 Apr 2021 03:14:37 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 73F6D407FF for ; Wed, 7 Apr 2021 03:14:35 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from akozyrev@nvidia.com) with SMTP; 7 Apr 2021 04:14:34 +0300 Received: from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 1371EYj6019068; Wed, 7 Apr 2021 04:14:34 +0300 From: Alexander Kozyrev To: dev@dpdk.org Cc: stable@dpdk.org, rasland@nvidia.com, viacheslavo@nvidia.com Date: Wed, 7 Apr 2021 01:14:33 +0000 Message-Id: <20210407011433.22785-1-akozyrev@nvidia.com> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH] net/mlx5: fix modify field action order for IPv6 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Mellanox hardware can only modify any packet field in 32-bit chunks, which means 4 such chunks are needed to modify an IPv6 address. The modification order of these chunks starts from the most significant bits for the IPv6 address. That leads to confusing results when trying to modify either source or destination address via the MODIFY_FIELD action. Fix the order of 32-bit chunks for IPv6 addresses modification by starting from the least significant bits. Fixes: 641dbe4fb053 ("net/mlx5: support modify field flow action") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/mlx5_flow_dv.c | 46 +++++++++++++++++---------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 6f8d16cec3..d3bf093b70 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1515,8 +1515,9 @@ mlx5_flow_field_id_to_modify_info case RTE_FLOW_FIELD_IPV6_SRC: if (mask) { if (data->offset < 32) { - info[idx] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_SIPV6_127_96}; + info[idx] = (struct field_modify_info){4, + 4 * idx, + MLX5_MODI_OUT_SIPV6_31_0}; if (width < 32) { mask[idx] = rte_cpu_to_be_32(0xffffffff >> @@ -1533,7 +1534,7 @@ mlx5_flow_field_id_to_modify_info if (data->offset < 64) { info[idx] = (struct field_modify_info){4, 4 * idx, - MLX5_MODI_OUT_SIPV6_95_64}; + MLX5_MODI_OUT_SIPV6_63_32}; if (width < 32) { mask[idx] = rte_cpu_to_be_32(0xffffffff >> @@ -1549,8 +1550,8 @@ mlx5_flow_field_id_to_modify_info } if (data->offset < 96) { info[idx] = (struct field_modify_info){4, - 8 * idx, - MLX5_MODI_OUT_SIPV6_63_32}; + 4 * idx, + MLX5_MODI_OUT_SIPV6_95_64}; if (width < 32) { mask[idx] = rte_cpu_to_be_32(0xffffffff >> @@ -1564,30 +1565,31 @@ mlx5_flow_field_id_to_modify_info break; ++idx; } - info[idx] = (struct field_modify_info){4, 12 * idx, - MLX5_MODI_OUT_SIPV6_31_0}; + info[idx] = (struct field_modify_info){4, 4 * idx, + MLX5_MODI_OUT_SIPV6_127_96}; mask[idx] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_SIPV6_127_96}; + MLX5_MODI_OUT_SIPV6_31_0}; if (data->offset < 64) info[idx++] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_SIPV6_95_64}; + MLX5_MODI_OUT_SIPV6_63_32}; if (data->offset < 96) info[idx++] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_SIPV6_63_32}; + MLX5_MODI_OUT_SIPV6_95_64}; if (data->offset < 128) info[idx++] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_SIPV6_31_0}; + MLX5_MODI_OUT_SIPV6_127_96}; } break; case RTE_FLOW_FIELD_IPV6_DST: if (mask) { if (data->offset < 32) { - info[idx] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_DIPV6_127_96}; + info[idx] = (struct field_modify_info){4, + 4 * idx, + MLX5_MODI_OUT_DIPV6_31_0}; if (width < 32) { mask[idx] = rte_cpu_to_be_32(0xffffffff >> @@ -1604,7 +1606,7 @@ mlx5_flow_field_id_to_modify_info if (data->offset < 64) { info[idx] = (struct field_modify_info){4, 4 * idx, - MLX5_MODI_OUT_DIPV6_95_64}; + MLX5_MODI_OUT_DIPV6_63_32}; if (width < 32) { mask[idx] = rte_cpu_to_be_32(0xffffffff >> @@ -1620,8 +1622,8 @@ mlx5_flow_field_id_to_modify_info } if (data->offset < 96) { info[idx] = (struct field_modify_info){4, - 8 * idx, - MLX5_MODI_OUT_DIPV6_63_32}; + 4 * idx, + MLX5_MODI_OUT_DIPV6_95_64}; if (width < 32) { mask[idx] = rte_cpu_to_be_32(0xffffffff >> @@ -1635,23 +1637,23 @@ mlx5_flow_field_id_to_modify_info break; ++idx; } - info[idx] = (struct field_modify_info){4, 12 * idx, - MLX5_MODI_OUT_DIPV6_31_0}; + info[idx] = (struct field_modify_info){4, 4 * idx, + MLX5_MODI_OUT_DIPV6_127_96}; mask[idx] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_DIPV6_127_96}; + MLX5_MODI_OUT_DIPV6_31_0}; if (data->offset < 64) info[idx++] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_DIPV6_95_64}; + MLX5_MODI_OUT_DIPV6_63_32}; if (data->offset < 96) info[idx++] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_DIPV6_63_32}; + MLX5_MODI_OUT_DIPV6_95_64}; if (data->offset < 128) info[idx++] = (struct field_modify_info){4, 0, - MLX5_MODI_OUT_DIPV6_31_0}; + MLX5_MODI_OUT_DIPV6_127_96}; } break; case RTE_FLOW_FIELD_TCP_PORT_SRC: -- 2.24.1