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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT020.mail.protection.outlook.com (10.13.174.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.27 via Frontend Transport; Thu, 29 Apr 2021 06:16:55 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 06:16:53 +0000 From: Gregory Etelson To: CC: , , , , Viacheslav Ovsiienko , "Shahaf Shuler" Date: Thu, 29 Apr 2021 09:16:31 +0300 Message-ID: <20210429061634.3481-3-getelson@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210429061634.3481-1-getelson@nvidia.com> References: <20210428175906.21387-1-getelson@nvidia.com> <20210429061634.3481-1-getelson@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0f4968e5-68df-44c0-f51f-08d90ad6638f X-MS-TrafficTypeDiagnostic: CH2PR12MB4198: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 06:16:55.8174 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f4968e5-68df-44c0-f51f-08d90ad6638f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4198 Subject: [dpdk-dev] [PATCH v2 2/4] net/mlx5: update PRM definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add integrity and IPv4 IHL bits to PRM file. Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 31 ++++++++++++++++++++---- drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 35 ++++++++++++++++++++++++++-- 3 files changed, 61 insertions(+), 6 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 6c6f4391a1..3d3994e575 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -626,6 +626,29 @@ mlx5_devx_cmd_create_flex_parser(void *ctx, return parse_flex_obj; } +static int +mlx5_devx_query_pkt_integrity_match(void *hcattr) +{ + return MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.inner_l3_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.inner_l4_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.outer_l3_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.outer_l4_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive + .inner_ipv4_checksum_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.inner_l4_checksum_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive + .outer_ipv4_checksum_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.outer_l4_checksum_ok); +} + /** * Query HCA attributes. * Using those attributes we can check on run time if the device @@ -823,10 +846,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, return -1; } hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); - attr->log_max_ft_sampler_num = - MLX5_GET(flow_table_nic_cap, - hcattr, flow_table_properties.log_max_ft_sampler_num); - + attr->log_max_ft_sampler_num = MLX5_GET + (flow_table_nic_cap, hcattr, + flow_table_properties_nic_receive.log_max_ft_sampler_num); + attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); /* Query HCA offloads for Ethernet protocol. */ memset(in, 0, sizeof(in)); memset(out, 0, sizeof(out)); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index eee8fee107..b31a828383 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -142,6 +142,7 @@ struct mlx5_hca_attr { uint32_t cqe_compression:1; uint32_t mini_cqe_resp_flow_tag:1; uint32_t mini_cqe_resp_l3_l4_tag:1; + uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; int log_max_qp_sz; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index c6d8060bb9..903faccd56 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -778,7 +778,12 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits { u8 tcp_flags[0x9]; u8 tcp_sport[0x10]; u8 tcp_dport[0x10]; - u8 reserved_at_c0[0x18]; + u8 reserved_at_c0[0x10]; + u8 ipv4_ihl[0x4]; + u8 l3_ok[0x1]; + u8 l4_ok[0x1]; + u8 ipv4_checksum_ok[0x1]; + u8 l4_checksum_ok[0x1]; u8 ip_ttl_hoplimit[0x8]; u8 udp_sport[0x10]; u8 udp_dport[0x10]; @@ -1656,9 +1661,35 @@ struct mlx5_ifc_roce_caps_bits { u8 reserved_at_20[0x7e0]; }; +/* + * Table 1872 - Flow Table Fields Supported 2 Format + */ +struct mlx5_ifc_ft_fields_support_2_bits { + u8 reserved_at_0[0x14]; + u8 inner_ipv4_ihl[0x1]; + u8 outer_ipv4_ihl[0x1]; + u8 psp_syndrome[0x1]; + u8 inner_l3_ok[0x1]; + u8 inner_l4_ok[0x1]; + u8 outer_l3_ok[0x1]; + u8 outer_l4_ok[0x1]; + u8 psp_header[0x1]; + u8 inner_ipv4_checksum_ok[0x1]; + u8 inner_l4_checksum_ok[0x1]; + u8 outer_ipv4_checksum_ok[0x1]; + u8 outer_l4_checksum_ok[0x1]; +}; + struct mlx5_ifc_flow_table_nic_cap_bits { u8 reserved_at_0[0x200]; - struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_receive; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_unused[5]; + u8 reserved_at_1C0[0x200]; + u8 header_modify_nic_receive[0x400]; + struct mlx5_ifc_ft_fields_support_2_bits + ft_field_support_2_nic_receive; }; union mlx5_ifc_hca_cap_union_bits { -- 2.31.1