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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT009.mail.protection.outlook.com (10.13.173.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.27 via Frontend Transport; Thu, 29 Apr 2021 15:45:13 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:45:10 +0000 From: Matan Azrad To: CC: , , Date: Thu, 29 Apr 2021 18:43:35 +0300 Message-ID: <20210429154335.2820028-17-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 54457a1e-2292-402c-fcdc-08d90b25c782 X-MS-TrafficTypeDiagnostic: BY5PR12MB4870: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2201; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:45:13.7462 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54457a1e-2292-402c-fcdc-08d90b25c782 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4870 Subject: [dpdk-dev] [PATCH v2 16/16] common/mlx5: add UMR and RDMA write WQE defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Suanming Mou This patch adds the struct defining UMR and RDMA write WQEs. Signed-off-by: Suanming Mou Signed-off-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 187 +++++++++++++++++++++------------ 1 file changed, 121 insertions(+), 66 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index c2cd2d9f70..1ffee5fd56 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -412,6 +412,127 @@ struct mlx5_cqe_ts { uint8_t op_own; }; +struct mlx5_wqe_rseg { + uint64_t raddr; + uint32_t rkey; + uint32_t reserved; +} __rte_packed; + +#define MLX5_UMRC_IF_OFFSET 31u +#define MLX5_UMRC_KO_OFFSET 16u +#define MLX5_UMRC_TO_BS_OFFSET 0u + +struct mlx5_wqe_umr_cseg { + uint32_t if_cf_toe_cq_res; + uint32_t ko_to_bs; + uint64_t mkey_mask; + uint32_t rsvd1[8]; +} __rte_packed; + +struct mlx5_wqe_mkey_cseg { + uint32_t fr_res_af_sf; + uint32_t qpn_mkey; + uint32_t reserved2; + uint32_t flags_pd; + uint64_t start_addr; + uint64_t len; + uint32_t bsf_octword_size; + uint32_t reserved3[4]; + uint32_t translations_octword_size; + uint32_t res4_lps; + uint32_t reserved; +} __rte_packed; + +enum { + MLX5_BSF_SIZE_16B = 0x0, + MLX5_BSF_SIZE_32B = 0x1, + MLX5_BSF_SIZE_64B = 0x2, + MLX5_BSF_SIZE_128B = 0x3, +}; + +enum { + MLX5_BSF_P_TYPE_SIGNATURE = 0x0, + MLX5_BSF_P_TYPE_CRYPTO = 0x1, +}; + +enum { + MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, +}; + +enum { + MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, +}; + +enum { + MLX5_BLOCK_SIZE_512B = 0x1, + MLX5_BLOCK_SIZE_520B = 0x2, + MLX5_BLOCK_SIZE_4096B = 0x3, + MLX5_BLOCK_SIZE_4160B = 0x4, + MLX5_BLOCK_SIZE_1MB = 0x5, + MLX5_BLOCK_SIZE_4048B = 0x6, +}; + +#define MLX5_BSF_SIZE_OFFSET 30 +#define MLX5_BSF_P_TYPE_OFFSET 24 +#define MLX5_ENCRYPTION_ORDER_OFFSET 16 +#define MLX5_BLOCK_SIZE_OFFSET 24 + +struct mlx5_wqe_umr_bsf_seg { + /* + * bs_bpt_eo_es contains: + * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET + * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET + * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET + * es encryption_standard 4 bits at offset 0 + */ + uint32_t bs_bpt_eo_es; + uint32_t raw_data_size; + /* + * bsp_res contains: + * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET + * res reserved 24 bits + */ + uint32_t bsp_res; + uint32_t reserved0; + uint8_t xts_initial_tweak[16]; + /* + * res_dp contains: + * res reserved 8 bits + * dp dek_pointer 24 bits at offset 0 + */ + uint32_t res_dp; + uint32_t reserved1; + uint64_t keytag; + uint32_t reserved2[4]; +} __rte_packed; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +struct mlx5_umr_wqe { + struct mlx5_wqe_cseg ctr; + struct mlx5_wqe_umr_cseg ucseg; + struct mlx5_wqe_mkey_cseg mkc; + union { + struct mlx5_wqe_dseg kseg[0]; + struct mlx5_wqe_umr_bsf_seg bsf[0]; + }; +} __rte_packed; + +struct mlx5_rdma_write_wqe { + struct mlx5_wqe_cseg ctr; + struct mlx5_wqe_rseg rseg; + struct mlx5_wqe_dseg dseg[0]; +} __rte_packed; + +#ifdef PEDANTIC +#pragma GCC diagnostic error "-Wpedantic" +#endif + /* GGA */ /* MMO metadata segment */ @@ -1096,72 +1217,6 @@ struct mlx5_ifc_create_mkey_in_bits { u8 klm_pas_mtt[][0x20]; }; -enum { - MLX5_BSF_SIZE_16B = 0x0, - MLX5_BSF_SIZE_32B = 0x1, - MLX5_BSF_SIZE_64B = 0x2, - MLX5_BSF_SIZE_128B = 0x3, -}; - -enum { - MLX5_BSF_P_TYPE_SIGNATURE = 0x0, - MLX5_BSF_P_TYPE_CRYPTO = 0x1, -}; - -enum { - MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, - MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, - MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, - MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, -}; - -enum { - MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, -}; - -enum { - MLX5_BLOCK_SIZE_512B = 0x1, - MLX5_BLOCK_SIZE_520B = 0x2, - MLX5_BLOCK_SIZE_4096B = 0x3, - MLX5_BLOCK_SIZE_4160B = 0x4, - MLX5_BLOCK_SIZE_1MB = 0x5, - MLX5_BLOCK_SIZE_4048B = 0x6, -}; - -#define MLX5_BSF_SIZE_OFFSET 30 -#define MLX5_BSF_P_TYPE_OFFSET 24 -#define MLX5_ENCRYPTION_ORDER_OFFSET 16 -#define MLX5_BLOCK_SIZE_OFFSET 24 - -struct mlx5_wqe_umr_bsf_seg { - /* - * bs_bpt_eo_es contains: - * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET - * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET - * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET - * es encryption_standard 4 bits at offset 0 - */ - uint32_t bs_bpt_eo_es; - uint32_t raw_data_size; - /* - * bsp_res contains: - * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET - * res reserved 24 bits - */ - uint32_t bsp_res; - uint32_t reserved0; - uint8_t xts_initial_tweak[16]; - /* - * res_dp contains: - * res reserved 8 bits - * dp dek_pointer 24 bits at offset 0 - */ - uint32_t res_dp; - uint32_t reserved1; - uint64_t keytag; - uint32_t reserved2[4]; -} __rte_packed; - enum { MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, -- 2.25.1