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From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
CC: <getelson@nvidia.com>, <matan@nvidia.com>, <orika@nvidia.com>,
<rasland@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, "Shahaf
Shuler" <shahafs@nvidia.com>
Date: Thu, 29 Apr 2021 21:36:57 +0300
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Subject: [dpdk-dev] [PATCH v3 2/4] net/mlx5: update PRM definitions
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Add integrity and IPv4 IHL bits to PRM file.
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 31 ++++++++++++++++++++---
drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
drivers/common/mlx5/mlx5_prm.h | 37 +++++++++++++++++++++++++---
3 files changed, 62 insertions(+), 7 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 79fff6457c..1b54c05313 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -626,6 +626,29 @@ mlx5_devx_cmd_create_flex_parser(void *ctx,
return parse_flex_obj;
}
+static int
+mlx5_devx_query_pkt_integrity_match(void *hcattr)
+{
+ return MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive.inner_l3_ok) &&
+ MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive.inner_l4_ok) &&
+ MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive.outer_l3_ok) &&
+ MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive.outer_l4_ok) &&
+ MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive
+ .inner_ipv4_checksum_ok) &&
+ MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
+ MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive
+ .outer_ipv4_checksum_ok) &&
+ MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive.outer_l4_checksum_ok);
+}
+
/**
* Query HCA attributes.
* Using those attributes we can check on run time if the device
@@ -823,10 +846,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
return -1;
}
hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
- attr->log_max_ft_sampler_num =
- MLX5_GET(flow_table_nic_cap,
- hcattr, flow_table_properties.log_max_ft_sampler_num);
-
+ attr->log_max_ft_sampler_num = MLX5_GET
+ (flow_table_nic_cap, hcattr,
+ flow_table_properties_nic_receive.log_max_ft_sampler_num);
+ attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
/* Query HCA offloads for Ethernet protocol. */
memset(in, 0, sizeof(in));
memset(out, 0, sizeof(out));
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 870bdb6b30..5681e03fee 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -143,6 +143,7 @@ struct mlx5_hca_attr {
uint32_t cqe_compression:1;
uint32_t mini_cqe_resp_flow_tag:1;
uint32_t mini_cqe_resp_l3_l4_tag:1;
+ uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
int log_max_qp_sz;
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index efa5ae67bf..330101233a 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -778,7 +778,12 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
u8 tcp_flags[0x9];
u8 tcp_sport[0x10];
u8 tcp_dport[0x10];
- u8 reserved_at_c0[0x18];
+ u8 reserved_at_c0[0x10];
+ u8 ipv4_ihl[0x4];
+ u8 l3_ok[0x1];
+ u8 l4_ok[0x1];
+ u8 ipv4_checksum_ok[0x1];
+ u8 l4_checksum_ok[0x1];
u8 ip_ttl_hoplimit[0x8];
u8 udp_sport[0x10];
u8 udp_dport[0x10];
@@ -1656,9 +1661,35 @@ struct mlx5_ifc_roce_caps_bits {
u8 reserved_at_20[0x7e0];
};
+/*
+ * Table 1872 - Flow Table Fields Supported 2 Format
+ */
+struct mlx5_ifc_ft_fields_support_2_bits {
+ u8 reserved_at_0[0x14];
+ u8 inner_ipv4_ihl[0x1];
+ u8 outer_ipv4_ihl[0x1];
+ u8 psp_syndrome[0x1];
+ u8 inner_l3_ok[0x1];
+ u8 inner_l4_ok[0x1];
+ u8 outer_l3_ok[0x1];
+ u8 outer_l4_ok[0x1];
+ u8 psp_header[0x1];
+ u8 inner_ipv4_checksum_ok[0x1];
+ u8 inner_l4_checksum_ok[0x1];
+ u8 outer_ipv4_checksum_ok[0x1];
+ u8 outer_l4_checksum_ok[0x1];
+};
+
struct mlx5_ifc_flow_table_nic_cap_bits {
- u8 reserved_at_0[0x200];
- struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
+ u8 reserved_at_0[0x200];
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_receive;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_unused[5];
+ u8 reserved_at_1C0[0x200];
+ u8 header_modify_nic_receive[0x400];
+ struct mlx5_ifc_ft_fields_support_2_bits
+ ft_field_support_2_nic_receive;
};
union mlx5_ifc_hca_cap_union_bits {
--
2.31.1