From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EBBADA0A02; Tue, 18 May 2021 10:51:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BEAB541101; Tue, 18 May 2021 10:51:10 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id A00C8410FE for ; Tue, 18 May 2021 10:51:09 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1427D31B; Tue, 18 May 2021 01:51:09 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.111]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D46913F719; Tue, 18 May 2021 01:51:06 -0700 (PDT) From: Feifei Wang To: Matan Azrad , Shahaf Shuler Cc: dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang Date: Tue, 18 May 2021 16:50:57 +0800 Message-Id: <20210518085058.630072-2-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210518085058.630072-1-feifei.wang2@arm.com> References: <20210318071840.359957-1-feifei.wang2@arm.com> <20210518085058.630072-1-feifei.wang2@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 1/2] net/mlx4: remove unnecessary wmb for Memory Region cache X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 'dev_gen' is a variable to trigger all cores to flush their local caches once the global MR cache has been rebuilt. This is due to MR cache's R/W lock can maintain synchronization between threads: 1. dev_gen and global cache updating ordering inside the lock protected section does not matter. Because other threads cannot take the lock until global cache has been updated. Thus, in out of order platform, even if other agents firstly observe updated dev_gen but global does not update, they still have to wait the lock. As a result, it is unnecessary to add a wmb between global cache rebuilding and updating the dev_gen to keep the memory store order. 2. Store-Release of unlock provides the implicit wmb at the level visible by software. This makes 'rebuilding global cache' and 'updating dev_gen' be observed before local_cache starts to be updated by other agents. Thus, wmb after 'updating dev_gen' can be removed. Suggested-by: Ruifeng Wang Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- drivers/net/mlx4/mlx4_mr.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/net/mlx4/mlx4_mr.c b/drivers/net/mlx4/mlx4_mr.c index 6b2f0cf187..2274b5df19 100644 --- a/drivers/net/mlx4/mlx4_mr.c +++ b/drivers/net/mlx4/mlx4_mr.c @@ -948,18 +948,13 @@ mlx4_mr_mem_event_free_cb(struct rte_eth_dev *dev, const void *addr, size_t len) if (rebuild) { mr_rebuild_dev_cache(dev); /* - * Flush local caches by propagating invalidation across cores. - * rte_smp_wmb() is enough to synchronize this event. If one of - * freed memsegs is seen by other core, that means the memseg - * has been allocated by allocator, which will come after this - * free call. Therefore, this store instruction (incrementing - * generation below) will be guaranteed to be seen by other core - * before the core sees the newly allocated memory. + * No explicit wmb is needed after updating dev_gen due to + * store-release ordering in unlock that provides the + * implicit barrier at the software visible level. */ ++priv->mr.dev_gen; DEBUG("broadcasting local cache flush, gen=%d", priv->mr.dev_gen); - rte_smp_wmb(); } rte_rwlock_write_unlock(&priv->mr.rwlock); #ifdef RTE_LIBRTE_MLX4_DEBUG -- 2.25.1