* [dpdk-dev] [PATCH 2/3] common/sfc_efx/base: add MAE VLAN presence match bits
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
@ 2021-04-28 9:49 ` Ivan Malov
2021-04-28 10:08 ` Kinsella, Ray
2021-04-30 14:49 ` Kinsella, Ray
2021-04-28 9:49 ` [dpdk-dev] [PATCH 3/3] net/sfc: support matching on VLAN presence in transfer rules Ivan Malov
` (10 subsequent siblings)
11 siblings, 2 replies; 23+ messages in thread
From: Ivan Malov @ 2021-04-28 9:49 UTC (permalink / raw)
To: dev; +Cc: Andrew Rybchenko, Andy Moreton, Ray Kinsella, Neil Horman
Introduce necessary infrastructure for these fields to
be set, validated and compared during class comparison.
Enumeration and mappings envisaged are MCDI-compatible.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
---
drivers/common/sfc_efx/base/efx.h | 18 ++
drivers/common/sfc_efx/base/efx_impl.h | 3 +-
drivers/common/sfc_efx/base/efx_mae.c | 235 ++++++++++++++++++++++++-
drivers/common/sfc_efx/version.map | 1 +
4 files changed, 254 insertions(+), 3 deletions(-)
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 771fe5a17..8e13075b0 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -4103,6 +4103,10 @@ efx_mae_match_spec_fini(
__in efx_mae_match_spec_t *spec);
typedef enum efx_mae_field_id_e {
+ /*
+ * Fields which can be set by efx_mae_match_spec_field_set()
+ * or by using dedicated field-specific helper APIs.
+ */
EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
EFX_MAE_FIELD_ETHER_TYPE_BE,
EFX_MAE_FIELD_ETH_SADDR_BE,
@@ -4140,6 +4144,12 @@ typedef enum efx_mae_field_id_e {
EFX_MAE_FIELD_ENC_VNET_ID_BE,
EFX_MAE_FIELD_OUTER_RULE_ID,
+ /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
+ EFX_MAE_FIELD_HAS_OVLAN,
+ EFX_MAE_FIELD_HAS_IVLAN,
+ EFX_MAE_FIELD_ENC_HAS_OVLAN,
+ EFX_MAE_FIELD_ENC_HAS_IVLAN,
+
EFX_MAE_FIELD_NIDS
} efx_mae_field_id_t;
@@ -4198,6 +4208,14 @@ efx_mae_match_spec_field_set(
__in size_t mask_size,
__in_bcount(mask_size) const uint8_t *mask);
+/* The corresponding mask will be set to B_TRUE. */
+LIBEFX_API
+extern __checkReturn efx_rc_t
+efx_mae_match_spec_bit_set(
+ __in efx_mae_match_spec_t *spec,
+ __in efx_mae_field_id_t field_id,
+ __in boolean_t value);
+
/* If the mask argument is NULL, the API will use full mask by default. */
LIBEFX_API
extern __checkReturn efx_rc_t
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 4a513171a..8b63cfb37 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1720,7 +1720,8 @@ struct efx_mae_match_spec_s {
efx_mae_rule_type_t emms_type;
uint32_t emms_prio;
union emms_mask_value_pairs {
- uint8_t action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
+ uint8_t action[
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN];
uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN];
} emms_mask_value_pairs;
};
diff --git a/drivers/common/sfc_efx/base/efx_mae.c b/drivers/common/sfc_efx/base/efx_mae.c
index 80fe155d0..33ba31389 100644
--- a/drivers/common/sfc_efx/base/efx_mae.c
+++ b/drivers/common/sfc_efx/base/efx_mae.c
@@ -451,6 +451,10 @@ typedef enum efx_mae_field_cap_id_e {
EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
+ EFX_MAE_FIELD_ID_HAS_OVLAN = MAE_FIELD_HAS_OVLAN,
+ EFX_MAE_FIELD_ID_HAS_IVLAN = MAE_FIELD_HAS_IVLAN,
+ EFX_MAE_FIELD_ID_ENC_HAS_OVLAN = MAE_FIELD_ENC_HAS_OVLAN,
+ EFX_MAE_FIELD_ID_ENC_HAS_IVLAN = MAE_FIELD_ENC_HAS_IVLAN,
EFX_MAE_FIELD_CAP_NIDS
} efx_mae_field_cap_id_t;
@@ -577,6 +581,65 @@ static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
#undef EFX_MAE_MV_DESC_ALT
#undef EFX_MAE_MV_DESC
+};
+
+/*
+ * The following structure is a means to describe an MAE bit.
+ * The information in it is meant to be used internally by
+ * APIs for addressing a given flag in a mask-value pairs
+ * structure and for validation purposes.
+ */
+typedef struct efx_mae_mv_bit_desc_s {
+ /*
+ * Arrays using this struct are indexed by field IDs.
+ * Fields which aren't meant to be referenced by these
+ * arrays comprise gaps (invalid entries). Below field
+ * helps to identify such entries.
+ */
+ boolean_t emmbd_entry_is_valid;
+ efx_mae_field_cap_id_t emmbd_bit_cap_id;
+ size_t emmbd_value_ofst;
+ unsigned int emmbd_value_lbn;
+ size_t emmbd_mask_ofst;
+ unsigned int emmbd_mask_lbn;
+} efx_mae_mv_bit_desc_t;
+
+static const efx_mae_mv_bit_desc_t __efx_mae_outer_rule_mv_bit_desc_set[] = {
+#define EFX_MAE_MV_BIT_DESC(_name) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ B_TRUE, \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_LBN, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_LBN, \
+ }
+
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
+
+#undef EFX_MAE_MV_BIT_DESC
+};
+
+static const efx_mae_mv_bit_desc_t __efx_mae_action_rule_mv_bit_desc_set[] = {
+#define EFX_MAE_MV_BIT_DESC(_name) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ B_TRUE, \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
+ }
+
+ EFX_MAE_MV_BIT_DESC(HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(HAS_IVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
+
+#undef EFX_MAE_MV_BIT_DESC
};
__checkReturn efx_rc_t
@@ -775,6 +838,70 @@ efx_mae_match_spec_field_set(
EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mae_match_spec_bit_set(
+ __in efx_mae_match_spec_t *spec,
+ __in efx_mae_field_id_t field_id,
+ __in boolean_t value)
+{
+ const efx_mae_mv_bit_desc_t *bit_descp;
+ unsigned int bit_desc_set_nentries;
+ unsigned int byte_idx;
+ unsigned int bit_idx;
+ uint8_t *mvp;
+ efx_rc_t rc;
+
+ switch (spec->emms_type) {
+ case EFX_MAE_RULE_OUTER:
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
+ bit_descp = &__efx_mae_outer_rule_mv_bit_desc_set[field_id];
+ mvp = spec->emms_mask_value_pairs.outer;
+ break;
+ case EFX_MAE_RULE_ACTION:
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
+ bit_descp = &__efx_mae_action_rule_mv_bit_desc_set[field_id];
+ mvp = spec->emms_mask_value_pairs.action;
+ break;
+ default:
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if ((unsigned int)field_id >= bit_desc_set_nentries) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE) {
+ rc = EINVAL;
+ goto fail3;
+ }
+
+ byte_idx = bit_descp->emmbd_value_ofst + bit_descp->emmbd_value_lbn / 8;
+ bit_idx = bit_descp->emmbd_value_lbn % 8;
+
+ if (value != B_FALSE)
+ mvp[byte_idx] |= (1U << bit_idx);
+ else
+ mvp[byte_idx] &= ~(1U << bit_idx);
+
+ byte_idx = bit_descp->emmbd_mask_ofst + bit_descp->emmbd_mask_lbn / 8;
+ bit_idx = bit_descp->emmbd_mask_lbn % 8;
+ mvp[byte_idx] |= (1U << bit_idx);
+
+ return (0);
+
fail3:
EFSYS_PROBE(fail3);
fail2:
@@ -891,6 +1018,8 @@ efx_mae_match_spec_is_valid(
const efx_mae_field_cap_t *field_caps;
const efx_mae_mv_desc_t *desc_setp;
unsigned int desc_set_nentries;
+ const efx_mae_mv_bit_desc_t *bit_desc_setp;
+ unsigned int bit_desc_set_nentries;
boolean_t is_valid = B_TRUE;
efx_mae_field_id_t field_id;
const uint8_t *mvp;
@@ -901,6 +1030,9 @@ efx_mae_match_spec_is_valid(
desc_setp = __efx_mae_outer_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
mvp = spec->emms_mask_value_pairs.outer;
break;
case EFX_MAE_RULE_ACTION:
@@ -908,6 +1040,9 @@ efx_mae_match_spec_is_valid(
desc_setp = __efx_mae_action_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
mvp = spec->emms_mask_value_pairs.action;
break;
default:
@@ -975,6 +1110,48 @@ efx_mae_match_spec_is_valid(
break;
}
+ if (is_valid == B_FALSE)
+ return (B_FALSE);
+ }
+
+ for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
+ ++field_id) {
+ const efx_mae_mv_bit_desc_t *bit_descp =
+ &bit_desc_setp[field_id];
+ unsigned int byte_idx =
+ bit_descp->emmbd_mask_ofst +
+ bit_descp->emmbd_mask_lbn / 8;
+ unsigned int bit_idx =
+ bit_descp->emmbd_mask_lbn % 8;
+ efx_mae_field_cap_id_t bit_cap_id =
+ bit_descp->emmbd_bit_cap_id;
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE)
+ continue; /* Skip array gap */
+
+ if ((unsigned int)bit_cap_id >= field_ncaps) {
+ /* No capability for this bit = unsupported. */
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
+ if (is_valid == B_FALSE)
+ break;
+ else
+ continue;
+ }
+
+ switch (field_caps[bit_cap_id].emfc_support) {
+ case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
+ is_valid = B_TRUE;
+ break;
+ case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) != 0);
+ break;
+ case MAE_FIELD_SUPPORTED_MATCH_NEVER:
+ case MAE_FIELD_UNSUPPORTED:
+ default:
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
+ break;
+ }
+
if (is_valid == B_FALSE)
break;
}
@@ -1528,6 +1705,8 @@ efx_mae_match_specs_class_cmp(
const efx_mae_field_cap_t *field_caps;
const efx_mae_mv_desc_t *desc_setp;
unsigned int desc_set_nentries;
+ const efx_mae_mv_bit_desc_t *bit_desc_setp;
+ unsigned int bit_desc_set_nentries;
boolean_t have_same_class = B_TRUE;
efx_mae_field_id_t field_id;
const uint8_t *mvpl;
@@ -1540,6 +1719,9 @@ efx_mae_match_specs_class_cmp(
desc_setp = __efx_mae_outer_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
mvpl = left->emms_mask_value_pairs.outer;
mvpr = right->emms_mask_value_pairs.outer;
break;
@@ -1548,6 +1730,9 @@ efx_mae_match_specs_class_cmp(
desc_setp = __efx_mae_action_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
mvpl = left->emms_mask_value_pairs.action;
mvpr = right->emms_mask_value_pairs.action;
break;
@@ -1620,6 +1805,52 @@ efx_mae_match_specs_class_cmp(
}
}
+ if (have_same_class == B_FALSE)
+ goto done;
+
+ for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
+ ++field_id) {
+ const efx_mae_mv_bit_desc_t *bit_descp =
+ &bit_desc_setp[field_id];
+ efx_mae_field_cap_id_t bit_cap_id =
+ bit_descp->emmbd_bit_cap_id;
+ unsigned int byte_idx;
+ unsigned int bit_idx;
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE)
+ continue; /* Skip array gap */
+
+ if ((unsigned int)bit_cap_id >= field_ncaps)
+ break;
+
+ byte_idx =
+ bit_descp->emmbd_mask_ofst +
+ bit_descp->emmbd_mask_lbn / 8;
+ bit_idx =
+ bit_descp->emmbd_mask_lbn % 8;
+
+ if (field_caps[bit_cap_id].emfc_mask_affects_class &&
+ (mvpl[byte_idx] & (1U << bit_idx)) !=
+ (mvpr[byte_idx] & (1U << bit_idx))) {
+ have_same_class = B_FALSE;
+ break;
+ }
+
+ byte_idx =
+ bit_descp->emmbd_value_ofst +
+ bit_descp->emmbd_value_lbn / 8;
+ bit_idx =
+ bit_descp->emmbd_value_lbn % 8;
+
+ if (field_caps[bit_cap_id].emfc_match_affects_class &&
+ (mvpl[byte_idx] & (1U << bit_idx)) !=
+ (mvpr[byte_idx] & (1U << bit_idx))) {
+ have_same_class = B_FALSE;
+ break;
+ }
+ }
+
+done:
*have_same_classp = have_same_class;
return (0);
@@ -2254,10 +2485,10 @@ efx_mae_action_rule_insert(
* MCDI request and are thus safe to be copied directly to the buffer.
*/
EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
- MAE_FIELD_MASK_VALUE_PAIRS_LEN);
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
memcpy(payload + offset, spec->emms_mask_value_pairs.action,
- MAE_FIELD_MASK_VALUE_PAIRS_LEN);
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
efx_mcdi_execute(enp, &req);
diff --git a/drivers/common/sfc_efx/version.map b/drivers/common/sfc_efx/version.map
index 5e724fd10..75da5aa5c 100644
--- a/drivers/common/sfc_efx/version.map
+++ b/drivers/common/sfc_efx/version.map
@@ -106,6 +106,7 @@ INTERNAL {
efx_mae_fini;
efx_mae_get_limits;
efx_mae_init;
+ efx_mae_match_spec_bit_set;
efx_mae_match_spec_field_set;
efx_mae_match_spec_fini;
efx_mae_match_spec_init;
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [dpdk-dev] [PATCH 2/3] common/sfc_efx/base: add MAE VLAN presence match bits
2021-04-28 9:49 ` [dpdk-dev] [PATCH 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
@ 2021-04-28 10:08 ` Kinsella, Ray
2021-04-28 11:09 ` Ivan Malov
2021-04-30 14:49 ` Kinsella, Ray
1 sibling, 1 reply; 23+ messages in thread
From: Kinsella, Ray @ 2021-04-28 10:08 UTC (permalink / raw)
To: Ivan Malov, dev; +Cc: Andrew Rybchenko, Andy Moreton, Neil Horman
On 28/04/2021 10:49, Ivan Malov wrote:
> Introduce necessary infrastructure for these fields to
> be set, validated and compared during class comparison.
> Enumeration and mappings envisaged are MCDI-compatible.
>
> Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
> Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
> Reviewed-by: Andy Moreton <amoreton@xilinx.com>
> ---
> drivers/common/sfc_efx/base/efx.h | 18 ++
> drivers/common/sfc_efx/base/efx_impl.h | 3 +-
> drivers/common/sfc_efx/base/efx_mae.c | 235 ++++++++++++++++++++++++-
> drivers/common/sfc_efx/version.map | 1 +
> 4 files changed, 254 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
> index 771fe5a17..8e13075b0 100644
> --- a/drivers/common/sfc_efx/base/efx.h
> +++ b/drivers/common/sfc_efx/base/efx.h
> @@ -4103,6 +4103,10 @@ efx_mae_match_spec_fini(
> __in efx_mae_match_spec_t *spec);
>
> typedef enum efx_mae_field_id_e {
> + /*
> + * Fields which can be set by efx_mae_match_spec_field_set()
> + * or by using dedicated field-specific helper APIs.
> + */
> EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
> EFX_MAE_FIELD_ETHER_TYPE_BE,
> EFX_MAE_FIELD_ETH_SADDR_BE,
> @@ -4140,6 +4144,12 @@ typedef enum efx_mae_field_id_e {
> EFX_MAE_FIELD_ENC_VNET_ID_BE,
> EFX_MAE_FIELD_OUTER_RULE_ID,
>
> + /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
> + EFX_MAE_FIELD_HAS_OVLAN,
> + EFX_MAE_FIELD_HAS_IVLAN,
> + EFX_MAE_FIELD_ENC_HAS_OVLAN,
> + EFX_MAE_FIELD_ENC_HAS_IVLAN,
> +
> EFX_MAE_FIELD_NIDS
> } efx_mae_field_id_t;
>
> @@ -4198,6 +4208,14 @@ efx_mae_match_spec_field_set(
> __in size_t mask_size,
> __in_bcount(mask_size) const uint8_t *mask);
>
> +/* The corresponding mask will be set to B_TRUE. */
> +LIBEFX_API
> +extern __checkReturn efx_rc_t
Missing rte_internal on the forward declaration?
> +efx_mae_match_spec_bit_set(
> + __in efx_mae_match_spec_t *spec,
> + __in efx_mae_field_id_t field_id,
> + __in boolean_t value);
> +
> /* If the mask argument is NULL, the API will use full mask by default. */
> LIBEFX_API
> extern __checkReturn efx_rc_t
> diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
> index 4a513171a..8b63cfb37 100644
> --- a/drivers/common/sfc_efx/base/efx_impl.h
> +++ b/drivers/common/sfc_efx/base/efx_impl.h
> @@ -1720,7 +1720,8 @@ struct efx_mae_match_spec_s {
> efx_mae_rule_type_t emms_type;
> uint32_t emms_prio;
> union emms_mask_value_pairs {
> - uint8_t action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
> + uint8_t action[
> + MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN];
> uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN];
> } emms_mask_value_pairs;
> };
> diff --git a/drivers/common/sfc_efx/base/efx_mae.c b/drivers/common/sfc_efx/base/efx_mae.c
> index 80fe155d0..33ba31389 100644
> --- a/drivers/common/sfc_efx/base/efx_mae.c
> +++ b/drivers/common/sfc_efx/base/efx_mae.c
> @@ -451,6 +451,10 @@ typedef enum efx_mae_field_cap_id_e {
> EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
> EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
> EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
> + EFX_MAE_FIELD_ID_HAS_OVLAN = MAE_FIELD_HAS_OVLAN,
> + EFX_MAE_FIELD_ID_HAS_IVLAN = MAE_FIELD_HAS_IVLAN,
> + EFX_MAE_FIELD_ID_ENC_HAS_OVLAN = MAE_FIELD_ENC_HAS_OVLAN,
> + EFX_MAE_FIELD_ID_ENC_HAS_IVLAN = MAE_FIELD_ENC_HAS_IVLAN,
>
> EFX_MAE_FIELD_CAP_NIDS
> } efx_mae_field_cap_id_t;
> @@ -577,6 +581,65 @@ static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
>
> #undef EFX_MAE_MV_DESC_ALT
> #undef EFX_MAE_MV_DESC
> +};
> +
> +/*
> + * The following structure is a means to describe an MAE bit.
> + * The information in it is meant to be used internally by
> + * APIs for addressing a given flag in a mask-value pairs
> + * structure and for validation purposes.
> + */
> +typedef struct efx_mae_mv_bit_desc_s {
> + /*
> + * Arrays using this struct are indexed by field IDs.
> + * Fields which aren't meant to be referenced by these
> + * arrays comprise gaps (invalid entries). Below field
> + * helps to identify such entries.
> + */
> + boolean_t emmbd_entry_is_valid;
> + efx_mae_field_cap_id_t emmbd_bit_cap_id;
> + size_t emmbd_value_ofst;
> + unsigned int emmbd_value_lbn;
> + size_t emmbd_mask_ofst;
> + unsigned int emmbd_mask_lbn;
> +} efx_mae_mv_bit_desc_t;
> +
> +static const efx_mae_mv_bit_desc_t __efx_mae_outer_rule_mv_bit_desc_set[] = {
> +#define EFX_MAE_MV_BIT_DESC(_name) \
> + [EFX_MAE_FIELD_##_name] = \
> + { \
> + B_TRUE, \
> + EFX_MAE_FIELD_ID_##_name, \
> + MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
> + MAE_ENC_FIELD_PAIRS_##_name##_LBN, \
> + MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
> + MAE_ENC_FIELD_PAIRS_##_name##_MASK_LBN, \
> + }
> +
> + EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
> + EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
> +
> +#undef EFX_MAE_MV_BIT_DESC
> +};
> +
> +static const efx_mae_mv_bit_desc_t __efx_mae_action_rule_mv_bit_desc_set[] = {
> +#define EFX_MAE_MV_BIT_DESC(_name) \
> + [EFX_MAE_FIELD_##_name] = \
> + { \
> + B_TRUE, \
> + EFX_MAE_FIELD_ID_##_name, \
> + MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST, \
> + MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
> + MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST, \
> + MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
> + }
> +
> + EFX_MAE_MV_BIT_DESC(HAS_OVLAN),
> + EFX_MAE_MV_BIT_DESC(HAS_IVLAN),
> + EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
> + EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
> +
> +#undef EFX_MAE_MV_BIT_DESC
> };
>
> __checkReturn efx_rc_t
> @@ -775,6 +838,70 @@ efx_mae_match_spec_field_set(
> EFSYS_PROBE(fail5);
> fail4:
> EFSYS_PROBE(fail4);
> +fail3:
> + EFSYS_PROBE(fail3);
> +fail2:
> + EFSYS_PROBE(fail2);
> +fail1:
> + EFSYS_PROBE1(fail1, efx_rc_t, rc);
> + return (rc);
> +}
> +
> + __checkReturn efx_rc_t
> +efx_mae_match_spec_bit_set(
> + __in efx_mae_match_spec_t *spec,
> + __in efx_mae_field_id_t field_id,
> + __in boolean_t value)
> +{
> + const efx_mae_mv_bit_desc_t *bit_descp;
> + unsigned int bit_desc_set_nentries;
> + unsigned int byte_idx;
> + unsigned int bit_idx;
> + uint8_t *mvp;
> + efx_rc_t rc;
> +
> + switch (spec->emms_type) {
> + case EFX_MAE_RULE_OUTER:
> + bit_desc_set_nentries =
> + EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
> + bit_descp = &__efx_mae_outer_rule_mv_bit_desc_set[field_id];
> + mvp = spec->emms_mask_value_pairs.outer;
> + break;
> + case EFX_MAE_RULE_ACTION:
> + bit_desc_set_nentries =
> + EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
> + bit_descp = &__efx_mae_action_rule_mv_bit_desc_set[field_id];
> + mvp = spec->emms_mask_value_pairs.action;
> + break;
> + default:
> + rc = ENOTSUP;
> + goto fail1;
> + }
> +
> + if ((unsigned int)field_id >= bit_desc_set_nentries) {
> + rc = EINVAL;
> + goto fail2;
> + }
> +
> + if (bit_descp->emmbd_entry_is_valid == B_FALSE) {
> + rc = EINVAL;
> + goto fail3;
> + }
> +
> + byte_idx = bit_descp->emmbd_value_ofst + bit_descp->emmbd_value_lbn / 8;
> + bit_idx = bit_descp->emmbd_value_lbn % 8;
> +
> + if (value != B_FALSE)
> + mvp[byte_idx] |= (1U << bit_idx);
> + else
> + mvp[byte_idx] &= ~(1U << bit_idx);
> +
> + byte_idx = bit_descp->emmbd_mask_ofst + bit_descp->emmbd_mask_lbn / 8;
> + bit_idx = bit_descp->emmbd_mask_lbn % 8;
> + mvp[byte_idx] |= (1U << bit_idx);
> +
> + return (0);
> +
> fail3:
> EFSYS_PROBE(fail3);
> fail2:
> @@ -891,6 +1018,8 @@ efx_mae_match_spec_is_valid(
> const efx_mae_field_cap_t *field_caps;
> const efx_mae_mv_desc_t *desc_setp;
> unsigned int desc_set_nentries;
> + const efx_mae_mv_bit_desc_t *bit_desc_setp;
> + unsigned int bit_desc_set_nentries;
> boolean_t is_valid = B_TRUE;
> efx_mae_field_id_t field_id;
> const uint8_t *mvp;
> @@ -901,6 +1030,9 @@ efx_mae_match_spec_is_valid(
> desc_setp = __efx_mae_outer_rule_mv_desc_set;
> desc_set_nentries =
> EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
> + bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
> + bit_desc_set_nentries =
> + EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
> mvp = spec->emms_mask_value_pairs.outer;
> break;
> case EFX_MAE_RULE_ACTION:
> @@ -908,6 +1040,9 @@ efx_mae_match_spec_is_valid(
> desc_setp = __efx_mae_action_rule_mv_desc_set;
> desc_set_nentries =
> EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
> + bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
> + bit_desc_set_nentries =
> + EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
> mvp = spec->emms_mask_value_pairs.action;
> break;
> default:
> @@ -975,6 +1110,48 @@ efx_mae_match_spec_is_valid(
> break;
> }
>
> + if (is_valid == B_FALSE)
> + return (B_FALSE);
> + }
> +
> + for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
> + ++field_id) {
> + const efx_mae_mv_bit_desc_t *bit_descp =
> + &bit_desc_setp[field_id];
> + unsigned int byte_idx =
> + bit_descp->emmbd_mask_ofst +
> + bit_descp->emmbd_mask_lbn / 8;
> + unsigned int bit_idx =
> + bit_descp->emmbd_mask_lbn % 8;
> + efx_mae_field_cap_id_t bit_cap_id =
> + bit_descp->emmbd_bit_cap_id;
> +
> + if (bit_descp->emmbd_entry_is_valid == B_FALSE)
> + continue; /* Skip array gap */
> +
> + if ((unsigned int)bit_cap_id >= field_ncaps) {
> + /* No capability for this bit = unsupported. */
> + is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
> + if (is_valid == B_FALSE)
> + break;
> + else
> + continue;
> + }
> +
> + switch (field_caps[bit_cap_id].emfc_support) {
> + case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
> + is_valid = B_TRUE;
> + break;
> + case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
> + is_valid = ((mvp[byte_idx] & (1U << bit_idx)) != 0);
> + break;
> + case MAE_FIELD_SUPPORTED_MATCH_NEVER:
> + case MAE_FIELD_UNSUPPORTED:
> + default:
> + is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
> + break;
> + }
> +
> if (is_valid == B_FALSE)
> break;
> }
> @@ -1528,6 +1705,8 @@ efx_mae_match_specs_class_cmp(
> const efx_mae_field_cap_t *field_caps;
> const efx_mae_mv_desc_t *desc_setp;
> unsigned int desc_set_nentries;
> + const efx_mae_mv_bit_desc_t *bit_desc_setp;
> + unsigned int bit_desc_set_nentries;
> boolean_t have_same_class = B_TRUE;
> efx_mae_field_id_t field_id;
> const uint8_t *mvpl;
> @@ -1540,6 +1719,9 @@ efx_mae_match_specs_class_cmp(
> desc_setp = __efx_mae_outer_rule_mv_desc_set;
> desc_set_nentries =
> EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
> + bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
> + bit_desc_set_nentries =
> + EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
> mvpl = left->emms_mask_value_pairs.outer;
> mvpr = right->emms_mask_value_pairs.outer;
> break;
> @@ -1548,6 +1730,9 @@ efx_mae_match_specs_class_cmp(
> desc_setp = __efx_mae_action_rule_mv_desc_set;
> desc_set_nentries =
> EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
> + bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
> + bit_desc_set_nentries =
> + EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
> mvpl = left->emms_mask_value_pairs.action;
> mvpr = right->emms_mask_value_pairs.action;
> break;
> @@ -1620,6 +1805,52 @@ efx_mae_match_specs_class_cmp(
> }
> }
>
> + if (have_same_class == B_FALSE)
> + goto done;
> +
> + for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
> + ++field_id) {
> + const efx_mae_mv_bit_desc_t *bit_descp =
> + &bit_desc_setp[field_id];
> + efx_mae_field_cap_id_t bit_cap_id =
> + bit_descp->emmbd_bit_cap_id;
> + unsigned int byte_idx;
> + unsigned int bit_idx;
> +
> + if (bit_descp->emmbd_entry_is_valid == B_FALSE)
> + continue; /* Skip array gap */
> +
> + if ((unsigned int)bit_cap_id >= field_ncaps)
> + break;
> +
> + byte_idx =
> + bit_descp->emmbd_mask_ofst +
> + bit_descp->emmbd_mask_lbn / 8;
> + bit_idx =
> + bit_descp->emmbd_mask_lbn % 8;
> +
> + if (field_caps[bit_cap_id].emfc_mask_affects_class &&
> + (mvpl[byte_idx] & (1U << bit_idx)) !=
> + (mvpr[byte_idx] & (1U << bit_idx))) {
> + have_same_class = B_FALSE;
> + break;
> + }
> +
> + byte_idx =
> + bit_descp->emmbd_value_ofst +
> + bit_descp->emmbd_value_lbn / 8;
> + bit_idx =
> + bit_descp->emmbd_value_lbn % 8;
> +
> + if (field_caps[bit_cap_id].emfc_match_affects_class &&
> + (mvpl[byte_idx] & (1U << bit_idx)) !=
> + (mvpr[byte_idx] & (1U << bit_idx))) {
> + have_same_class = B_FALSE;
> + break;
> + }
> + }
> +
> +done:
> *have_same_classp = have_same_class;
>
> return (0);
> @@ -2254,10 +2485,10 @@ efx_mae_action_rule_insert(
> * MCDI request and are thus safe to be copied directly to the buffer.
> */
> EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
> - MAE_FIELD_MASK_VALUE_PAIRS_LEN);
> + MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
> offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
> memcpy(payload + offset, spec->emms_mask_value_pairs.action,
> - MAE_FIELD_MASK_VALUE_PAIRS_LEN);
> + MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
>
> efx_mcdi_execute(enp, &req);
>
> diff --git a/drivers/common/sfc_efx/version.map b/drivers/common/sfc_efx/version.map
> index 5e724fd10..75da5aa5c 100644
> --- a/drivers/common/sfc_efx/version.map
> +++ b/drivers/common/sfc_efx/version.map
> @@ -106,6 +106,7 @@ INTERNAL {
> efx_mae_fini;
> efx_mae_get_limits;
> efx_mae_init;
> + efx_mae_match_spec_bit_set;
> efx_mae_match_spec_field_set;
> efx_mae_match_spec_fini;
> efx_mae_match_spec_init;
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [dpdk-dev] [PATCH 2/3] common/sfc_efx/base: add MAE VLAN presence match bits
2021-04-28 10:08 ` Kinsella, Ray
@ 2021-04-28 11:09 ` Ivan Malov
0 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-04-28 11:09 UTC (permalink / raw)
To: Kinsella, Ray, dev; +Cc: Andrew Rybchenko, Andy Moreton, Neil Horman
Hi,
On 28/04/2021 13:08, Kinsella, Ray wrote:
>
>
> On 28/04/2021 10:49, Ivan Malov wrote:
>> Introduce necessary infrastructure for these fields to
>> be set, validated and compared during class comparison.
>> Enumeration and mappings envisaged are MCDI-compatible.
>>
>> Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
>> Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
>> Reviewed-by: Andy Moreton <amoreton@xilinx.com>
>> ---
>> drivers/common/sfc_efx/base/efx.h | 18 ++
>> drivers/common/sfc_efx/base/efx_impl.h | 3 +-
>> drivers/common/sfc_efx/base/efx_mae.c | 235 ++++++++++++++++++++++++-
>> drivers/common/sfc_efx/version.map | 1 +
>> 4 files changed, 254 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
>> index 771fe5a17..8e13075b0 100644
>> --- a/drivers/common/sfc_efx/base/efx.h
>> +++ b/drivers/common/sfc_efx/base/efx.h
>> @@ -4103,6 +4103,10 @@ efx_mae_match_spec_fini(
>> __in efx_mae_match_spec_t *spec);
>>
>> typedef enum efx_mae_field_id_e {
>> + /*
>> + * Fields which can be set by efx_mae_match_spec_field_set()
>> + * or by using dedicated field-specific helper APIs.
>> + */
>> EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
>> EFX_MAE_FIELD_ETHER_TYPE_BE,
>> EFX_MAE_FIELD_ETH_SADDR_BE,
>> @@ -4140,6 +4144,12 @@ typedef enum efx_mae_field_id_e {
>> EFX_MAE_FIELD_ENC_VNET_ID_BE,
>> EFX_MAE_FIELD_OUTER_RULE_ID,
>>
>> + /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
>> + EFX_MAE_FIELD_HAS_OVLAN,
>> + EFX_MAE_FIELD_HAS_IVLAN,
>> + EFX_MAE_FIELD_ENC_HAS_OVLAN,
>> + EFX_MAE_FIELD_ENC_HAS_IVLAN,
>> +
>> EFX_MAE_FIELD_NIDS
>> } efx_mae_field_id_t;
>>
>> @@ -4198,6 +4208,14 @@ efx_mae_match_spec_field_set(
>> __in size_t mask_size,
>> __in_bcount(mask_size) const uint8_t *mask);
>>
>> +/* The corresponding mask will be set to B_TRUE. */
>> +LIBEFX_API
>> +extern __checkReturn efx_rc_t
>
> Missing rte_internal on the forward declaration?
Not really. It has LIBEFX_API in place. And LIBEFX_API, in turn, is
defined as __rte_internal in drivers/common/sfc_efx/efsys.h . Thank you.
>
>> +efx_mae_match_spec_bit_set(
>> + __in efx_mae_match_spec_t *spec,
>> + __in efx_mae_field_id_t field_id,
>> + __in boolean_t value);
>> +
>> /* If the mask argument is NULL, the API will use full mask by default. */
>> LIBEFX_API
>> extern __checkReturn efx_rc_t
>> diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
>> index 4a513171a..8b63cfb37 100644
>> --- a/drivers/common/sfc_efx/base/efx_impl.h
>> +++ b/drivers/common/sfc_efx/base/efx_impl.h
>> @@ -1720,7 +1720,8 @@ struct efx_mae_match_spec_s {
>> efx_mae_rule_type_t emms_type;
>> uint32_t emms_prio;
>> union emms_mask_value_pairs {
>> - uint8_t action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
>> + uint8_t action[
>> + MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN];
>> uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN];
>> } emms_mask_value_pairs;
>> };
>> diff --git a/drivers/common/sfc_efx/base/efx_mae.c b/drivers/common/sfc_efx/base/efx_mae.c
>> index 80fe155d0..33ba31389 100644
>> --- a/drivers/common/sfc_efx/base/efx_mae.c
>> +++ b/drivers/common/sfc_efx/base/efx_mae.c
>> @@ -451,6 +451,10 @@ typedef enum efx_mae_field_cap_id_e {
>> EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
>> EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
>> EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
>> + EFX_MAE_FIELD_ID_HAS_OVLAN = MAE_FIELD_HAS_OVLAN,
>> + EFX_MAE_FIELD_ID_HAS_IVLAN = MAE_FIELD_HAS_IVLAN,
>> + EFX_MAE_FIELD_ID_ENC_HAS_OVLAN = MAE_FIELD_ENC_HAS_OVLAN,
>> + EFX_MAE_FIELD_ID_ENC_HAS_IVLAN = MAE_FIELD_ENC_HAS_IVLAN,
>>
>> EFX_MAE_FIELD_CAP_NIDS
>> } efx_mae_field_cap_id_t;
>> @@ -577,6 +581,65 @@ static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
>>
>> #undef EFX_MAE_MV_DESC_ALT
>> #undef EFX_MAE_MV_DESC
>> +};
>> +
>> +/*
>> + * The following structure is a means to describe an MAE bit.
>> + * The information in it is meant to be used internally by
>> + * APIs for addressing a given flag in a mask-value pairs
>> + * structure and for validation purposes.
>> + */
>> +typedef struct efx_mae_mv_bit_desc_s {
>> + /*
>> + * Arrays using this struct are indexed by field IDs.
>> + * Fields which aren't meant to be referenced by these
>> + * arrays comprise gaps (invalid entries). Below field
>> + * helps to identify such entries.
>> + */
>> + boolean_t emmbd_entry_is_valid;
>> + efx_mae_field_cap_id_t emmbd_bit_cap_id;
>> + size_t emmbd_value_ofst;
>> + unsigned int emmbd_value_lbn;
>> + size_t emmbd_mask_ofst;
>> + unsigned int emmbd_mask_lbn;
>> +} efx_mae_mv_bit_desc_t;
>> +
>> +static const efx_mae_mv_bit_desc_t __efx_mae_outer_rule_mv_bit_desc_set[] = {
>> +#define EFX_MAE_MV_BIT_DESC(_name) \
>> + [EFX_MAE_FIELD_##_name] = \
>> + { \
>> + B_TRUE, \
>> + EFX_MAE_FIELD_ID_##_name, \
>> + MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
>> + MAE_ENC_FIELD_PAIRS_##_name##_LBN, \
>> + MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
>> + MAE_ENC_FIELD_PAIRS_##_name##_MASK_LBN, \
>> + }
>> +
>> + EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
>> + EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
>> +
>> +#undef EFX_MAE_MV_BIT_DESC
>> +};
>> +
>> +static const efx_mae_mv_bit_desc_t __efx_mae_action_rule_mv_bit_desc_set[] = {
>> +#define EFX_MAE_MV_BIT_DESC(_name) \
>> + [EFX_MAE_FIELD_##_name] = \
>> + { \
>> + B_TRUE, \
>> + EFX_MAE_FIELD_ID_##_name, \
>> + MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST, \
>> + MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
>> + MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST, \
>> + MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
>> + }
>> +
>> + EFX_MAE_MV_BIT_DESC(HAS_OVLAN),
>> + EFX_MAE_MV_BIT_DESC(HAS_IVLAN),
>> + EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
>> + EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
>> +
>> +#undef EFX_MAE_MV_BIT_DESC
>> };
>>
>> __checkReturn efx_rc_t
>> @@ -775,6 +838,70 @@ efx_mae_match_spec_field_set(
>> EFSYS_PROBE(fail5);
>> fail4:
>> EFSYS_PROBE(fail4);
>> +fail3:
>> + EFSYS_PROBE(fail3);
>> +fail2:
>> + EFSYS_PROBE(fail2);
>> +fail1:
>> + EFSYS_PROBE1(fail1, efx_rc_t, rc);
>> + return (rc);
>> +}
>> +
>> + __checkReturn efx_rc_t
>> +efx_mae_match_spec_bit_set(
>> + __in efx_mae_match_spec_t *spec,
>> + __in efx_mae_field_id_t field_id,
>> + __in boolean_t value)
>> +{
>> + const efx_mae_mv_bit_desc_t *bit_descp;
>> + unsigned int bit_desc_set_nentries;
>> + unsigned int byte_idx;
>> + unsigned int bit_idx;
>> + uint8_t *mvp;
>> + efx_rc_t rc;
>> +
>> + switch (spec->emms_type) {
>> + case EFX_MAE_RULE_OUTER:
>> + bit_desc_set_nentries =
>> + EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
>> + bit_descp = &__efx_mae_outer_rule_mv_bit_desc_set[field_id];
>> + mvp = spec->emms_mask_value_pairs.outer;
>> + break;
>> + case EFX_MAE_RULE_ACTION:
>> + bit_desc_set_nentries =
>> + EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
>> + bit_descp = &__efx_mae_action_rule_mv_bit_desc_set[field_id];
>> + mvp = spec->emms_mask_value_pairs.action;
>> + break;
>> + default:
>> + rc = ENOTSUP;
>> + goto fail1;
>> + }
>> +
>> + if ((unsigned int)field_id >= bit_desc_set_nentries) {
>> + rc = EINVAL;
>> + goto fail2;
>> + }
>> +
>> + if (bit_descp->emmbd_entry_is_valid == B_FALSE) {
>> + rc = EINVAL;
>> + goto fail3;
>> + }
>> +
>> + byte_idx = bit_descp->emmbd_value_ofst + bit_descp->emmbd_value_lbn / 8;
>> + bit_idx = bit_descp->emmbd_value_lbn % 8;
>> +
>> + if (value != B_FALSE)
>> + mvp[byte_idx] |= (1U << bit_idx);
>> + else
>> + mvp[byte_idx] &= ~(1U << bit_idx);
>> +
>> + byte_idx = bit_descp->emmbd_mask_ofst + bit_descp->emmbd_mask_lbn / 8;
>> + bit_idx = bit_descp->emmbd_mask_lbn % 8;
>> + mvp[byte_idx] |= (1U << bit_idx);
>> +
>> + return (0);
>> +
>> fail3:
>> EFSYS_PROBE(fail3);
>> fail2:
>> @@ -891,6 +1018,8 @@ efx_mae_match_spec_is_valid(
>> const efx_mae_field_cap_t *field_caps;
>> const efx_mae_mv_desc_t *desc_setp;
>> unsigned int desc_set_nentries;
>> + const efx_mae_mv_bit_desc_t *bit_desc_setp;
>> + unsigned int bit_desc_set_nentries;
>> boolean_t is_valid = B_TRUE;
>> efx_mae_field_id_t field_id;
>> const uint8_t *mvp;
>> @@ -901,6 +1030,9 @@ efx_mae_match_spec_is_valid(
>> desc_setp = __efx_mae_outer_rule_mv_desc_set;
>> desc_set_nentries =
>> EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
>> + bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
>> + bit_desc_set_nentries =
>> + EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
>> mvp = spec->emms_mask_value_pairs.outer;
>> break;
>> case EFX_MAE_RULE_ACTION:
>> @@ -908,6 +1040,9 @@ efx_mae_match_spec_is_valid(
>> desc_setp = __efx_mae_action_rule_mv_desc_set;
>> desc_set_nentries =
>> EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
>> + bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
>> + bit_desc_set_nentries =
>> + EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
>> mvp = spec->emms_mask_value_pairs.action;
>> break;
>> default:
>> @@ -975,6 +1110,48 @@ efx_mae_match_spec_is_valid(
>> break;
>> }
>>
>> + if (is_valid == B_FALSE)
>> + return (B_FALSE);
>> + }
>> +
>> + for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
>> + ++field_id) {
>> + const efx_mae_mv_bit_desc_t *bit_descp =
>> + &bit_desc_setp[field_id];
>> + unsigned int byte_idx =
>> + bit_descp->emmbd_mask_ofst +
>> + bit_descp->emmbd_mask_lbn / 8;
>> + unsigned int bit_idx =
>> + bit_descp->emmbd_mask_lbn % 8;
>> + efx_mae_field_cap_id_t bit_cap_id =
>> + bit_descp->emmbd_bit_cap_id;
>> +
>> + if (bit_descp->emmbd_entry_is_valid == B_FALSE)
>> + continue; /* Skip array gap */
>> +
>> + if ((unsigned int)bit_cap_id >= field_ncaps) {
>> + /* No capability for this bit = unsupported. */
>> + is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
>> + if (is_valid == B_FALSE)
>> + break;
>> + else
>> + continue;
>> + }
>> +
>> + switch (field_caps[bit_cap_id].emfc_support) {
>> + case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
>> + is_valid = B_TRUE;
>> + break;
>> + case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
>> + is_valid = ((mvp[byte_idx] & (1U << bit_idx)) != 0);
>> + break;
>> + case MAE_FIELD_SUPPORTED_MATCH_NEVER:
>> + case MAE_FIELD_UNSUPPORTED:
>> + default:
>> + is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
>> + break;
>> + }
>> +
>> if (is_valid == B_FALSE)
>> break;
>> }
>> @@ -1528,6 +1705,8 @@ efx_mae_match_specs_class_cmp(
>> const efx_mae_field_cap_t *field_caps;
>> const efx_mae_mv_desc_t *desc_setp;
>> unsigned int desc_set_nentries;
>> + const efx_mae_mv_bit_desc_t *bit_desc_setp;
>> + unsigned int bit_desc_set_nentries;
>> boolean_t have_same_class = B_TRUE;
>> efx_mae_field_id_t field_id;
>> const uint8_t *mvpl;
>> @@ -1540,6 +1719,9 @@ efx_mae_match_specs_class_cmp(
>> desc_setp = __efx_mae_outer_rule_mv_desc_set;
>> desc_set_nentries =
>> EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
>> + bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
>> + bit_desc_set_nentries =
>> + EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
>> mvpl = left->emms_mask_value_pairs.outer;
>> mvpr = right->emms_mask_value_pairs.outer;
>> break;
>> @@ -1548,6 +1730,9 @@ efx_mae_match_specs_class_cmp(
>> desc_setp = __efx_mae_action_rule_mv_desc_set;
>> desc_set_nentries =
>> EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
>> + bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
>> + bit_desc_set_nentries =
>> + EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
>> mvpl = left->emms_mask_value_pairs.action;
>> mvpr = right->emms_mask_value_pairs.action;
>> break;
>> @@ -1620,6 +1805,52 @@ efx_mae_match_specs_class_cmp(
>> }
>> }
>>
>> + if (have_same_class == B_FALSE)
>> + goto done;
>> +
>> + for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
>> + ++field_id) {
>> + const efx_mae_mv_bit_desc_t *bit_descp =
>> + &bit_desc_setp[field_id];
>> + efx_mae_field_cap_id_t bit_cap_id =
>> + bit_descp->emmbd_bit_cap_id;
>> + unsigned int byte_idx;
>> + unsigned int bit_idx;
>> +
>> + if (bit_descp->emmbd_entry_is_valid == B_FALSE)
>> + continue; /* Skip array gap */
>> +
>> + if ((unsigned int)bit_cap_id >= field_ncaps)
>> + break;
>> +
>> + byte_idx =
>> + bit_descp->emmbd_mask_ofst +
>> + bit_descp->emmbd_mask_lbn / 8;
>> + bit_idx =
>> + bit_descp->emmbd_mask_lbn % 8;
>> +
>> + if (field_caps[bit_cap_id].emfc_mask_affects_class &&
>> + (mvpl[byte_idx] & (1U << bit_idx)) !=
>> + (mvpr[byte_idx] & (1U << bit_idx))) {
>> + have_same_class = B_FALSE;
>> + break;
>> + }
>> +
>> + byte_idx =
>> + bit_descp->emmbd_value_ofst +
>> + bit_descp->emmbd_value_lbn / 8;
>> + bit_idx =
>> + bit_descp->emmbd_value_lbn % 8;
>> +
>> + if (field_caps[bit_cap_id].emfc_match_affects_class &&
>> + (mvpl[byte_idx] & (1U << bit_idx)) !=
>> + (mvpr[byte_idx] & (1U << bit_idx))) {
>> + have_same_class = B_FALSE;
>> + break;
>> + }
>> + }
>> +
>> +done:
>> *have_same_classp = have_same_class;
>>
>> return (0);
>> @@ -2254,10 +2485,10 @@ efx_mae_action_rule_insert(
>> * MCDI request and are thus safe to be copied directly to the buffer.
>> */
>> EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
>> - MAE_FIELD_MASK_VALUE_PAIRS_LEN);
>> + MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
>> offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
>> memcpy(payload + offset, spec->emms_mask_value_pairs.action,
>> - MAE_FIELD_MASK_VALUE_PAIRS_LEN);
>> + MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
>>
>> efx_mcdi_execute(enp, &req);
>>
>> diff --git a/drivers/common/sfc_efx/version.map b/drivers/common/sfc_efx/version.map
>> index 5e724fd10..75da5aa5c 100644
>> --- a/drivers/common/sfc_efx/version.map
>> +++ b/drivers/common/sfc_efx/version.map
>> @@ -106,6 +106,7 @@ INTERNAL {
>> efx_mae_fini;
>> efx_mae_get_limits;
>> efx_mae_init;
>> + efx_mae_match_spec_bit_set;
>> efx_mae_match_spec_field_set;
>> efx_mae_match_spec_fini;
>> efx_mae_match_spec_init;
>>
--
Ivan M
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [dpdk-dev] [PATCH 2/3] common/sfc_efx/base: add MAE VLAN presence match bits
2021-04-28 9:49 ` [dpdk-dev] [PATCH 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
2021-04-28 10:08 ` Kinsella, Ray
@ 2021-04-30 14:49 ` Kinsella, Ray
1 sibling, 0 replies; 23+ messages in thread
From: Kinsella, Ray @ 2021-04-30 14:49 UTC (permalink / raw)
To: Ivan Malov, dev; +Cc: Andrew Rybchenko, Andy Moreton, Neil Horman
On 28/04/2021 10:49, Ivan Malov wrote:
> Introduce necessary infrastructure for these fields to
> be set, validated and compared during class comparison.
> Enumeration and mappings envisaged are MCDI-compatible.
>
> Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
> Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
> Reviewed-by: Andy Moreton <amoreton@xilinx.com>
> ---
> drivers/common/sfc_efx/base/efx.h | 18 ++
> drivers/common/sfc_efx/base/efx_impl.h | 3 +-
> drivers/common/sfc_efx/base/efx_mae.c | 235 ++++++++++++++++++++++++-
> drivers/common/sfc_efx/version.map | 1 +
> 4 files changed, 254 insertions(+), 3 deletions(-)
>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [dpdk-dev] [PATCH 3/3] net/sfc: support matching on VLAN presence in transfer rules
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
2021-04-28 9:49 ` [dpdk-dev] [PATCH 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
@ 2021-04-28 9:49 ` Ivan Malov
2021-04-30 15:56 ` [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ferruh Yigit
` (9 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-04-28 9:49 UTC (permalink / raw)
To: dev; +Cc: Andrew Rybchenko, Andy Moreton
Take into account VLAN presence fields in items ETH and VLAN.
Provided that the item ETH does not match on the EtherType,
the pattern behaviour will be as follows:
- ETH (mask->has_vlan = 0) | IPv4 = match both tagged and untagged;
- ETH (mask->has_vlan = 1) | IPv4 = match as per spec->has_vlan;
- ETH (mask->has_vlan = 0) | VLAN | IPv4 = match only tagged.
Similar logic applies to double tagging.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
---
drivers/net/sfc/sfc_mae.c | 124 ++++++++++++++++++++++++++++++++------
drivers/net/sfc/sfc_mae.h | 19 +++++-
2 files changed, 123 insertions(+), 20 deletions(-)
diff --git a/drivers/net/sfc/sfc_mae.c b/drivers/net/sfc/sfc_mae.c
index a2c0aa143..d8c662503 100644
--- a/drivers/net/sfc/sfc_mae.c
+++ b/drivers/net/sfc/sfc_mae.c
@@ -728,6 +728,7 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
RTE_BE16(RTE_ETHER_TYPE_QINQ2),
RTE_BE16(RTE_ETHER_TYPE_QINQ3),
};
+ bool enforce_tag_presence[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {};
unsigned int nb_supported_tpids = RTE_DIM(supported_tpids);
unsigned int ethertype_idx;
const uint8_t *valuep;
@@ -753,6 +754,22 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
ethertype_idx < pdata->nb_vlan_tags; ++ethertype_idx) {
unsigned int tpid_idx;
+ /*
+ * This loop can have only two iterations. On the second one,
+ * drop outer tag presence enforcement bit because the inner
+ * tag presence automatically assumes that for the outer tag.
+ */
+ enforce_tag_presence[0] = B_FALSE;
+
+ if (ethertypes[ethertype_idx].mask == RTE_BE16(0)) {
+ if (pdata->tci_masks[ethertype_idx] == RTE_BE16(0))
+ enforce_tag_presence[ethertype_idx] = B_TRUE;
+
+ /* No match on this field, and no value check. */
+ nb_supported_tpids = 1;
+ continue;
+ }
+
/* Exact match is supported only. */
if (ethertypes[ethertype_idx].mask != RTE_BE16(0xffff)) {
rc = EINVAL;
@@ -812,6 +829,24 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
}
}
+ if (enforce_tag_presence[0] || pdata->has_ovlan_mask) {
+ rc = efx_mae_match_spec_bit_set(ctx->match_spec,
+ fremap[EFX_MAE_FIELD_HAS_OVLAN],
+ enforce_tag_presence[0] ||
+ pdata->has_ovlan_value);
+ if (rc != 0)
+ goto fail;
+ }
+
+ if (enforce_tag_presence[1] || pdata->has_ivlan_mask) {
+ rc = efx_mae_match_spec_bit_set(ctx->match_spec,
+ fremap[EFX_MAE_FIELD_HAS_IVLAN],
+ enforce_tag_presence[1] ||
+ pdata->has_ivlan_value);
+ if (rc != 0)
+ goto fail;
+ }
+
valuep = (const uint8_t *)&pdata->l3_next_proto_value;
maskp = (const uint8_t *)&pdata->l3_next_proto_mask;
rc = efx_mae_match_spec_field_set(ctx->match_spec,
@@ -1154,6 +1189,7 @@ sfc_mae_rule_parse_item_eth(const struct rte_flow_item *item,
sfc_mae_item_build_supp_mask(flocs_eth, RTE_DIM(flocs_eth),
&supp_mask, sizeof(supp_mask));
+ supp_mask.has_vlan = 1;
rc = sfc_flow_parse_init(item,
(const void **)&spec, (const void **)&mask,
@@ -1172,14 +1208,23 @@ sfc_mae_rule_parse_item_eth(const struct rte_flow_item *item,
item_spec = (const struct rte_flow_item_eth *)spec;
item_mask = (const struct rte_flow_item_eth *)mask;
+ /*
+ * Remember various match criteria in the parsing context.
+ * sfc_mae_rule_process_pattern_data() will consider them
+ * altogether when the rest of the items have been parsed.
+ */
ethertypes[0].value = item_spec->type;
ethertypes[0].mask = item_mask->type;
+ if (item_mask->has_vlan) {
+ pdata->has_ovlan_mask = B_TRUE;
+ if (item_spec->has_vlan)
+ pdata->has_ovlan_value = B_TRUE;
+ }
} else {
/*
- * The specification is empty. This is wrong in the case
- * when there are more network patterns in line. Other
- * than that, any Ethernet can match. All of that is
- * checked at the end of parsing.
+ * The specification is empty. The overall pattern
+ * validity will be enforced at the end of parsing.
+ * See sfc_mae_rule_process_pattern_data().
*/
return 0;
}
@@ -1229,6 +1274,16 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
{
struct sfc_mae_parse_ctx *ctx_mae = ctx->mae;
struct sfc_mae_pattern_data *pdata = &ctx_mae->pattern_data;
+ boolean_t *has_vlan_mp_by_nb_tags[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {
+ &pdata->has_ovlan_mask,
+ &pdata->has_ivlan_mask,
+ };
+ boolean_t *has_vlan_vp_by_nb_tags[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {
+ &pdata->has_ovlan_value,
+ &pdata->has_ivlan_value,
+ };
+ boolean_t *cur_tag_presence_bit_mp;
+ boolean_t *cur_tag_presence_bit_vp;
const struct sfc_mae_field_locator *flocs;
struct rte_flow_item_vlan supp_mask;
const uint8_t *spec = NULL;
@@ -1244,14 +1299,27 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
"Can't match that many VLAN tags");
}
+ cur_tag_presence_bit_mp = has_vlan_mp_by_nb_tags[pdata->nb_vlan_tags];
+ cur_tag_presence_bit_vp = has_vlan_vp_by_nb_tags[pdata->nb_vlan_tags];
+
+ if (*cur_tag_presence_bit_mp == B_TRUE &&
+ *cur_tag_presence_bit_vp == B_FALSE) {
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "The previous item enforces no (more) VLAN, "
+ "so the current item (VLAN) must not exist");
+ }
+
nb_flocs = RTE_DIM(flocs_vlan) / SFC_MAE_MATCH_VLAN_MAX_NTAGS;
flocs = flocs_vlan + pdata->nb_vlan_tags * nb_flocs;
- /* If parsing fails, this can remain incremented. */
- ++pdata->nb_vlan_tags;
-
sfc_mae_item_build_supp_mask(flocs, nb_flocs,
&supp_mask, sizeof(supp_mask));
+ /*
+ * This only means that the field is supported by the driver and libefx.
+ * Support on NIC level will be checked when all items have been parsed.
+ */
+ supp_mask.has_more_vlan = 1;
rc = sfc_flow_parse_init(item,
(const void **)&spec, (const void **)&mask,
@@ -1262,26 +1330,44 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
return rc;
if (spec != NULL) {
- struct sfc_mae_ethertype *ethertypes = pdata->ethertypes;
+ struct sfc_mae_ethertype *et = pdata->ethertypes;
const struct rte_flow_item_vlan *item_spec;
const struct rte_flow_item_vlan *item_mask;
item_spec = (const struct rte_flow_item_vlan *)spec;
item_mask = (const struct rte_flow_item_vlan *)mask;
- ethertypes[pdata->nb_vlan_tags].value = item_spec->inner_type;
- ethertypes[pdata->nb_vlan_tags].mask = item_mask->inner_type;
- } else {
/*
- * The specification is empty. This is wrong in the case
- * when there are more network patterns in line. Other
- * than that, any Ethernet can match. All of that is
- * checked at the end of parsing.
+ * Remember various match criteria in the parsing context.
+ * sfc_mae_rule_process_pattern_data() will consider them
+ * altogether when the rest of the items have been parsed.
*/
- return 0;
+ et[pdata->nb_vlan_tags + 1].value = item_spec->inner_type;
+ et[pdata->nb_vlan_tags + 1].mask = item_mask->inner_type;
+ pdata->tci_masks[pdata->nb_vlan_tags] = item_mask->tci;
+ if (item_mask->has_more_vlan) {
+ if (pdata->nb_vlan_tags ==
+ SFC_MAE_MATCH_VLAN_MAX_NTAGS) {
+ return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "Can't use 'has_more_vlan' in "
+ "the second item VLAN");
+ }
+ pdata->has_ivlan_mask = B_TRUE;
+ if (item_spec->has_more_vlan)
+ pdata->has_ivlan_value = B_TRUE;
+ }
+
+ /* Convert TCI to MAE representation right now. */
+ rc = sfc_mae_parse_item(flocs, nb_flocs, spec, mask,
+ ctx_mae, error);
+ if (rc != 0)
+ return rc;
}
- return sfc_mae_parse_item(flocs, nb_flocs, spec, mask, ctx_mae, error);
+ ++(pdata->nb_vlan_tags);
+
+ return 0;
}
static const struct sfc_mae_field_locator flocs_ipv4[] = {
@@ -1612,6 +1698,8 @@ static const efx_mae_field_id_t field_ids_no_remap[] = {
FIELD_ID_NO_REMAP(L4_SPORT_BE),
FIELD_ID_NO_REMAP(L4_DPORT_BE),
FIELD_ID_NO_REMAP(TCP_FLAGS_BE),
+ FIELD_ID_NO_REMAP(HAS_OVLAN),
+ FIELD_ID_NO_REMAP(HAS_IVLAN),
#undef FIELD_ID_NO_REMAP
};
@@ -1642,6 +1730,8 @@ static const efx_mae_field_id_t field_ids_remap_to_encap[] = {
FIELD_ID_REMAP_TO_ENCAP(DST_IP6_BE),
FIELD_ID_REMAP_TO_ENCAP(L4_SPORT_BE),
FIELD_ID_REMAP_TO_ENCAP(L4_DPORT_BE),
+ FIELD_ID_REMAP_TO_ENCAP(HAS_OVLAN),
+ FIELD_ID_REMAP_TO_ENCAP(HAS_IVLAN),
#undef FIELD_ID_REMAP_TO_ENCAP
};
diff --git a/drivers/net/sfc/sfc_mae.h b/drivers/net/sfc/sfc_mae.h
index 9740e54e4..0241fe33c 100644
--- a/drivers/net/sfc/sfc_mae.h
+++ b/drivers/net/sfc/sfc_mae.h
@@ -130,12 +130,14 @@ struct sfc_mae_pattern_data {
*
* - If an item ETH is followed by a single item VLAN,
* the former must have "type" set to one of supported
- * TPID values (0x8100, 0x88a8, 0x9100, 0x9200, 0x9300).
+ * TPID values (0x8100, 0x88a8, 0x9100, 0x9200, 0x9300),
+ * or 0x0000/0x0000.
*
* - If an item ETH is followed by two items VLAN, the
* item ETH must have "type" set to one of supported TPID
- * values (0x88a8, 0x9100, 0x9200, 0x9300), and the outermost
- * VLAN item must have "inner_type" set to TPID value 0x8100.
+ * values (0x88a8, 0x9100, 0x9200, 0x9300), or 0x0000/0x0000,
+ * and the outermost VLAN item must have "inner_type" set
+ * to TPID value 0x8100, or 0x0000/0x0000
*
* - If a L2 item is followed by a L3 one, the former must
* indicate "type" ("inner_type") which corresponds to
@@ -156,6 +158,9 @@ struct sfc_mae_pattern_data {
* VLAN (L3 EtherType) --> ETHER_TYPE_BE
*/
struct sfc_mae_ethertype ethertypes[SFC_MAE_L2_MAX_NITEMS];
+
+ rte_be16_t tci_masks[SFC_MAE_MATCH_VLAN_MAX_NTAGS];
+
unsigned int nb_vlan_tags;
/**
@@ -191,6 +196,14 @@ struct sfc_mae_pattern_data {
*/
uint8_t l3_next_proto_restriction_value;
uint8_t l3_next_proto_restriction_mask;
+
+ /* Projected state of EFX_MAE_FIELD_HAS_OVLAN match bit */
+ bool has_ovlan_value;
+ bool has_ovlan_mask;
+
+ /* Projected state of EFX_MAE_FIELD_HAS_IVLAN match bit */
+ bool has_ivlan_value;
+ bool has_ivlan_mask;
};
struct sfc_mae_parse_ctx {
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
2021-04-28 9:49 ` [dpdk-dev] [PATCH 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
2021-04-28 9:49 ` [dpdk-dev] [PATCH 3/3] net/sfc: support matching on VLAN presence in transfer rules Ivan Malov
@ 2021-04-30 15:56 ` Ferruh Yigit
2021-04-30 17:05 ` Ivan Malov
2021-05-22 19:32 ` [dpdk-dev] [PATCH v2 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
` (8 subsequent siblings)
11 siblings, 1 reply; 23+ messages in thread
From: Ferruh Yigit @ 2021-04-30 15:56 UTC (permalink / raw)
To: Ivan Malov, dev; +Cc: Andrew Rybchenko
On 4/28/2021 10:49 AM, Ivan Malov wrote:
> From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
>
> Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
> Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
> ---
> drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3509 +++++++++++++++--
> .../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
> .../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
> 3 files changed, 3312 insertions(+), 341 deletions(-)
Hi Ivan,
There are some checkpatch spelling warnings, can you please check them?
Also is there a versioning on the MCDI, if so you may want to document the
updated version in driver guide and/or release notes.
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers
2021-04-30 15:56 ` [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ferruh Yigit
@ 2021-04-30 17:05 ` Ivan Malov
2021-05-04 7:50 ` Ferruh Yigit
0 siblings, 1 reply; 23+ messages in thread
From: Ivan Malov @ 2021-04-30 17:05 UTC (permalink / raw)
To: Ferruh Yigit, dev; +Cc: Andrew Rybchenko
Hi Ferruh,
These changes are imported. Furthermore, originally, these files are
auto-generated, so in order to fix spelling I can't just apply my edits
to the imported changes. The fixes are to be made in the original
source, and I believe this should be somehow discussed internally.
So, the changeset is either to be applied "as it is" (meaning that the
fixes are expected to be submitted with future updates) or postponed.
Maybe Andrew can advise.
Yes, I see the spelling warnings, they're pretty much valid. But some of
them are.. questionable. In particular, "misspelling" of the word HIST
in MC_CMD_LTSSM_HIST_MSGSET. For sure, the suggested replacement doesn't
quite fit the intended meaning of the macro.
Thank you.
On 30/04/2021 18:56, Ferruh Yigit wrote:
> On 4/28/2021 10:49 AM, Ivan Malov wrote:
>> From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
>>
>> Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
>> Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
>> ---
>> drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3509 +++++++++++++++--
>> .../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
>> .../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
>> 3 files changed, 3312 insertions(+), 341 deletions(-)
>
> Hi Ivan,
>
> There are some checkpatch spelling warnings, can you please check them?
>
> Also is there a versioning on the MCDI, if so you may want to document the
> updated version in driver guide and/or release notes.
>
--
Ivan M
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers
2021-04-30 17:05 ` Ivan Malov
@ 2021-05-04 7:50 ` Ferruh Yigit
2021-05-04 8:15 ` Andrew Rybchenko
0 siblings, 1 reply; 23+ messages in thread
From: Ferruh Yigit @ 2021-05-04 7:50 UTC (permalink / raw)
To: Ivan Malov, dev; +Cc: Andrew Rybchenko
On 4/30/2021 6:05 PM, Ivan Malov wrote:
> Hi Ferruh,
>
> These changes are imported. Furthermore, originally, these files are
> auto-generated, so in order to fix spelling I can't just apply my edits to the
> imported changes. The fixes are to be made in the original source, and I believe
> this should be somehow discussed internally.
>
> So, the changeset is either to be applied "as it is" (meaning that the fixes are
> expected to be submitted with future updates) or postponed. Maybe Andrew can
> advise.
>
> Yes, I see the spelling warnings, they're pretty much valid. But some of them
> are.. questionable. In particular, "misspelling" of the word HIST in
> MC_CMD_LTSSM_HIST_MSGSET. For sure, the suggested replacement doesn't quite fit
> the intended meaning of the macro.
>
You can ignore invalid warnings.
> Thank you.
>
> On 30/04/2021 18:56, Ferruh Yigit wrote:
>> On 4/28/2021 10:49 AM, Ivan Malov wrote:
>>> From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
>>>
>>> Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
>>> Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
>>> ---
>>> drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3509 +++++++++++++++--
>>> .../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
>>> .../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
>>> 3 files changed, 3312 insertions(+), 341 deletions(-)
>>
>> Hi Ivan,
>>
>> There are some checkpatch spelling warnings, can you please check them?
>>
>> Also is there a versioning on the MCDI, if so you may want to document the
>> updated version in driver guide and/or release notes.
>>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers
2021-05-04 7:50 ` Ferruh Yigit
@ 2021-05-04 8:15 ` Andrew Rybchenko
0 siblings, 0 replies; 23+ messages in thread
From: Andrew Rybchenko @ 2021-05-04 8:15 UTC (permalink / raw)
To: Ferruh Yigit, Ivan Malov; +Cc: dev
Hi Ferruh,
On 5/4/21 10:50 AM, Ferruh Yigit wrote:
> On 4/30/2021 6:05 PM, Ivan Malov wrote:
>> Hi Ferruh,
>>
>> These changes are imported. Furthermore, originally, these files are
>> auto-generated, so in order to fix spelling I can't just apply my edits to the
>> imported changes. The fixes are to be made in the original source, and I believe
>> this should be somehow discussed internally.
>>
>> So, the changeset is either to be applied "as it is" (meaning that the fixes are
>> expected to be submitted with future updates) or postponed. Maybe Andrew can
>> advise.
>>
>> Yes, I see the spelling warnings, they're pretty much valid. But some of them
>> are.. questionable. In particular, "misspelling" of the word HIST in
>> MC_CMD_LTSSM_HIST_MSGSET. For sure, the suggested replacement doesn't quite fit
>> the intended meaning of the macro.
>>
>
> You can ignore invalid warnings.
We'll provide v2 with spell fixes.
Thanks for noticing and paying attention to it.
>> Thank you.
>>
>> On 30/04/2021 18:56, Ferruh Yigit wrote:
>>> On 4/28/2021 10:49 AM, Ivan Malov wrote:
>>>> From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
>>>>
>>>> Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
>>>> Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
>>>> ---
>>>> drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3509 +++++++++++++++--
>>>> .../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
>>>> .../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
>>>> 3 files changed, 3312 insertions(+), 341 deletions(-)
>>>
>>> Hi Ivan,
>>>
>>> There are some checkpatch spelling warnings, can you please check them?
>>>
>>> Also is there a versioning on the MCDI, if so you may want to document the
>>> updated version in driver guide and/or release notes.
I think it is not required.
Thanks,
Andrew.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [dpdk-dev] [PATCH v2 0/3] Match On VLAN Presence In Transfer Flows
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (2 preceding siblings ...)
2021-04-30 15:56 ` [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ferruh Yigit
@ 2021-05-22 19:32 ` Ivan Malov
2021-05-22 19:32 ` [dpdk-dev] [PATCH v2 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (7 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-22 19:32 UTC (permalink / raw)
To: dev; +Cc: Ray Kinsella, Ferruh Yigit
Changes in v2:
* [1/3] no longer triggers spelling warnings
Andrew Rybchenko (1):
common/sfc_efx/base: update MCDI headers
Ivan Malov (2):
common/sfc_efx/base: add MAE VLAN presence match bits
net/sfc: support matching on VLAN presence in transfer rules
drivers/common/sfc_efx/base/efx.h | 18 +
drivers/common/sfc_efx/base/efx_impl.h | 3 +-
drivers/common/sfc_efx/base/efx_mae.c | 235 +-
drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3532 +++++++++++++++--
.../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
.../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
drivers/common/sfc_efx/version.map | 1 +
drivers/net/sfc/sfc_mae.c | 124 +-
drivers/net/sfc/sfc_mae.h | 19 +-
9 files changed, 3708 insertions(+), 368 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v2 1/3] common/sfc_efx/base: update MCDI headers
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (3 preceding siblings ...)
2021-05-22 19:32 ` [dpdk-dev] [PATCH v2 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
@ 2021-05-22 19:32 ` Ivan Malov
2021-05-22 19:32 ` [dpdk-dev] [PATCH v2 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
` (6 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-22 19:32 UTC (permalink / raw)
To: dev; +Cc: Andrew Rybchenko, Ray Kinsella, Ferruh Yigit
From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
---
drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3532 +++++++++++++++--
.../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
.../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
3 files changed, 3331 insertions(+), 345 deletions(-)
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
index 976db37d6..a3c9f076e 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
@@ -6,7 +6,7 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
* rebuild this file with "make mcdi_headers_v5".
*/
@@ -410,6 +410,48 @@
#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */
+/* MC_CMD_FPGA_FLASH_INDEX enum */
+#define MC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */
+#define MC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */
+
+/* MC_CMD_EXTERNAL_MAE_LINK_MODE enum */
+/* enum: Legacy mode as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0
+/* enum: Switchdev mode as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1
+/* enum: Bootstrap mode as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2
+/* enum: Link-mode change is in-progress as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf
+
+/* PCIE_INTERFACE enum: From EF100 onwards, SFC products can have multiple PCIe
+ * interfaces. There is a need to refer to interfaces explicitly from drivers
+ * (for example, a management driver on one interface administering a function
+ * on another interface). This enumeration provides stable identifiers to all
+ * interfaces present on a product. Product documentation will specify which
+ * interfaces exist and their associated identifier. In general, drivers,
+ * should not assign special meanings to specific values. Instead, behaviour
+ * should be determined by NIC configuration, which will identify interfaces
+ * where appropriate.
+ */
+/* enum: Primary host interfaces. Typically (i.e. for all known SFC products)
+ * the interface exposed on the edge connector (or form factor equivalent).
+ */
+#define PCIE_INTERFACE_HOST_PRIMARY 0x0
+/* enum: Riverhead and keystone products have a second PCIe interface to which
+ * an on-NIC ARM module is expected to be connected.
+ */
+#define PCIE_INTERFACE_NIC_EMBEDDED 0x1
+/* enum: For MCDI commands issued over a PCIe interface, this value is
+ * translated into the interface over which the command was issued. Not
+ * meaningful for other MCDI transports.
+ */
+#define PCIE_INTERFACE_CALLER 0xffffffff
+
+/* MC_CLIENT_ID_SPECIFIER enum */
+/* enum: Equivalent to the caller's client ID */
+#define MC_CMD_CLIENT_ID_SELF 0xffffffff
+
/* MAE_FIELD_SUPPORT_STATUS enum */
/* enum: The NIC does not support this field. The driver must ensure that any
* mask associated with this field in a match rule is zeroed. The NIC may
@@ -470,6 +512,20 @@
#define MAE_FIELD_CT_PRIVATE_FLAGS 0x8
/* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
#define MAE_FIELD_IS_FROM_NETWORK 0x9
+/* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
+#define MAE_FIELD_HAS_OVLAN 0xa
+/* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
+#define MAE_FIELD_HAS_IVLAN 0xb
+/* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
+ * when encap
+ */
+#define MAE_FIELD_ENC_HAS_OVLAN 0xc
+/* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
+ * when encap
+ */
+#define MAE_FIELD_ENC_HAS_IVLAN 0xd
+/* enum: Packet is IP fragment */
+#define MAE_FIELD_ENC_IP_FRAG 0xe
#define MAE_FIELD_ETHER_TYPE 0x21 /* enum */
#define MAE_FIELD_VLAN0_TCI 0x22 /* enum */
#define MAE_FIELD_VLAN0_PROTO 0x23 /* enum */
@@ -508,6 +564,10 @@
#define MAE_FIELD_L4_DPORT 0x33
/* enum: Inner when encap */
#define MAE_FIELD_TCP_FLAGS 0x34
+/* enum: TCP packet with any of SYN, FIN or RST flag set */
+#define MAE_FIELD_TCP_SYN_FIN_RST 0x35
+/* enum: Packet is IP fragment with fragment offset 0 */
+#define MAE_FIELD_IP_FIRST_FRAG 0x36
/* enum: The type of encapsulated used for this packet. Value as per
* ENCAP_TYPE_*.
*/
@@ -550,8 +610,8 @@
#define MAE_FIELD_ENC_L4_SPORT 0x52
/* enum: Outer; only present when encap */
#define MAE_FIELD_ENC_L4_DPORT 0x53
-/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Outer; only present when
- * encap
+/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Bottom 24 bits of Key
+ * (when L2GRE) Outer; only present when encap
*/
#define MAE_FIELD_ENC_VNET_ID 0x54
@@ -566,6 +626,14 @@
#define MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */
#define MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */
+/* MAE_MPORT_END enum: Selects which end of the logical link identified by an
+ * MPORT_SELECTOR is targeted by an operation.
+ */
+/* enum: Selects the port on the MAE virtual switch */
+#define MAE_MPORT_END_MAE 0x1
+/* enum: Selects the virtual NIC plugged into the MAE switch */
+#define MAE_MPORT_END_VNIC 0x2
+
/* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF100
* platforms
*/
@@ -647,17 +715,21 @@
#define MCDI_EVENT_TX_ERR_TYPE_OFST 0
#define MCDI_EVENT_TX_ERR_TYPE_LBN 12
#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
-/* enum: Descriptor loader reported failure */
+/* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */
#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
-/* enum: Descriptor ring empty and no EOP seen for packet */
+/* enum: Descriptor ring empty and no EOP seen for packet. Specific to
+ * EF10-family NICs
+ */
#define MCDI_EVENT_TX_ERR_NO_EOP 0x2
-/* enum: Overlength packet */
+/* enum: Overlength packet. Specific to EF10-family NICs. */
#define MCDI_EVENT_TX_ERR_2BIG 0x3
-/* enum: Malformed option descriptor */
+/* enum: Malformed option descriptor. Specific to EF10-family NICs. */
#define MCDI_EVENT_TX_BAD_OPTDESC 0x5
-/* enum: Option descriptor part way through a packet */
+/* enum: Option descriptor part way through a packet. Specific to EF10-family
+ * NICs.
+ */
#define MCDI_EVENT_TX_OPT_IN_PKT 0x8
-/* enum: DMA or PIO data access error */
+/* enum: DMA or PIO data access error. Specific to EF10-family NICs */
#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
#define MCDI_EVENT_TX_ERR_INFO_OFST 0
#define MCDI_EVENT_TX_ERR_INFO_LBN 16
@@ -1270,7 +1342,13 @@
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 4
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LBN 64
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_WIDTH 32
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 4
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LBN 96
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_WIDTH 32
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126
@@ -1384,6 +1462,7 @@
* has additional checks to reject insecure calls.
*/
#define MC_CMD_READ32 0x1
+#define MC_CMD_READ32_MSGSET 0x1
#undef MC_CMD_0x1_PRIVILEGE_CTG
#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -1413,6 +1492,7 @@
* Write multiple 32byte words to MC memory.
*/
#define MC_CMD_WRITE32 0x2
+#define MC_CMD_WRITE32_MSGSET 0x2
#undef MC_CMD_0x2_PRIVILEGE_CTG
#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -1442,6 +1522,7 @@
* has additional checks to reject insecure calls.
*/
#define MC_CMD_COPYCODE 0x3
+#define MC_CMD_COPYCODE_MSGSET 0x3
#undef MC_CMD_0x3_PRIVILEGE_CTG
#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -1505,6 +1586,7 @@
* Select function for function-specific commands.
*/
#define MC_CMD_SET_FUNC 0x4
+#define MC_CMD_SET_FUNC_MSGSET 0x4
#undef MC_CMD_0x4_PRIVILEGE_CTG
#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -1524,6 +1606,7 @@
* Get the instruction address from which the MC booted.
*/
#define MC_CMD_GET_BOOT_STATUS 0x5
+#define MC_CMD_GET_BOOT_STATUS_MSGSET 0x5
#undef MC_CMD_0x5_PRIVILEGE_CTG
#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -1558,6 +1641,7 @@
* fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
*/
#define MC_CMD_GET_ASSERTS 0x6
+#define MC_CMD_GET_ASSERTS_MSGSET 0x6
#undef MC_CMD_0x6_PRIVILEGE_CTG
#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -1682,12 +1766,24 @@
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LBN 2080
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_WIDTH 32
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LBN 2112
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_WIDTH 32
/* MC firmware version number */
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LBN 2144
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_WIDTH 32
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LBN 2176
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_WIDTH 32
/* MC firmware security level */
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
@@ -1705,6 +1801,7 @@
* sensor notifications and MCDI completions
*/
#define MC_CMD_LOG_CTRL 0x7
+#define MC_CMD_LOG_CTRL_MSGSET 0x7
#undef MC_CMD_0x7_PRIVILEGE_CTG
#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -1731,6 +1828,7 @@
* Get version information about adapter components.
*/
#define MC_CMD_GET_VERSION 0x8
+#define MC_CMD_GET_VERSION_MSGSET 0x8
#undef MC_CMD_0x8_PRIVILEGE_CTG
#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -1771,7 +1869,13 @@
#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_OUT_VERSION_LO_WIDTH 32
#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_OUT_VERSION_HI_WIDTH 32
/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
@@ -1787,7 +1891,13 @@
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_WIDTH 32
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
@@ -1811,7 +1921,13 @@
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_WIDTH 32
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32
#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16
@@ -1833,6 +1949,33 @@
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
/* MC firmware unique build ID (as binary SHA-1 value) */
#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52
#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20
@@ -1850,7 +1993,13 @@
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
/* The ID of the SUC chip. This is specific to the platform but typically
* indicates family, memory sizes etc. See SF-116728-SW for further details.
*/
@@ -1864,7 +2013,13 @@
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
/* FPGA version as three numbers. On Riverhead based systems this field uses
* the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
* FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
@@ -1886,12 +2041,496 @@
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64
+/* MC_CMD_GET_VERSION_V3_OUT msgresponse: Extended response providing version
+ * information for all adapter components. For Riverhead based designs, base MC
+ * firmware version fields refer to NMC firmware, while CMC firmware data is in
+ * dedicated CMC fields. Flags indicate which data is present in the response
+ * (depending on which components exist on a particular adapter)
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_LEN 328
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_WIDTH 32
+/* extra info */
+#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_LEN 64
+/* The version of the datapath hardware design as three number - a.b.c */
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_OFST 304
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_NUM 3
+/* The version of the firmware library used to control the datapath as three
+ * number - a.b.c
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_OFST 316
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_NUM 3
+
+/* MC_CMD_GET_VERSION_V4_OUT msgresponse: Extended response providing SoC
+ * version information
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_LEN 392
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_WIDTH 32
+/* extra info */
+#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_LEN 64
+/* The version of the datapath hardware design as three number - a.b.c */
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_OFST 304
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_NUM 3
+/* The version of the firmware library used to control the datapath as three
+ * number - a.b.c
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_OFST 316
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_NUM 3
+/* The SOC boot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_OFST 328
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4
+/* The SOC uboot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_OFST 344
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4
+/* The SOC main rootfs version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
+/* The SOC recovery buildroot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
+
+/* MC_CMD_GET_VERSION_V5_OUT msgresponse: Extended response providing bundle
+ * and board version information
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_LEN 424
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_WIDTH 32
+/* extra info */
+#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_LEN 64
+/* The version of the datapath hardware design as three number - a.b.c */
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_OFST 304
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_NUM 3
+/* The version of the firmware library used to control the datapath as three
+ * number - a.b.c
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_OFST 316
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_NUM 3
+/* The SOC boot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_OFST 328
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4
+/* The SOC uboot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_OFST 344
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4
+/* The SOC main rootfs version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
+/* The SOC recovery buildroot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
+/* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
+ * BOARD_REVISION field
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_OFST 392
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4
+/* Bundle version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_OFST 408
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4
+
/***********************************/
/* MC_CMD_PTP
* Perform PTP operation
*/
#define MC_CMD_PTP 0xb
+#define MC_CMD_PTP_MSGSET 0xb
#undef MC_CMD_0xb_PRIVILEGE_CTG
#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -2066,7 +2705,13 @@
#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
+#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LBN 64
+#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_WIDTH 32
#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
+#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LBN 96
+#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_WIDTH 32
/* enum: Number of fractional bits in frequency adjustment */
#define MC_CMD_PTP_IN_ADJUST_BITS 0x28
/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
@@ -2097,7 +2742,13 @@
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LBN 64
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_WIDTH 32
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LBN 96
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_WIDTH 32
/* enum: Number of fractional bits in frequency adjustment */
/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
@@ -2136,7 +2787,13 @@
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LBN 96
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_WIDTH 32
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LBN 128
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_WIDTH 32
/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
@@ -2252,7 +2909,13 @@
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LBN 64
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_WIDTH 32
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LBN 96
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_WIDTH 32
/* Enum values, see field(s): */
/* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */
@@ -2283,7 +2946,13 @@
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LBN 96
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_WIDTH 32
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LBN 128
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_WIDTH 32
/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
@@ -2745,6 +3414,7 @@
* Read 32bit words from the indirect memory map.
*/
#define MC_CMD_CSR_READ32 0xc
+#define MC_CMD_CSR_READ32_MSGSET 0xc
#undef MC_CMD_0xc_PRIVILEGE_CTG
#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -2778,6 +3448,7 @@
* Write 32bit dwords to the indirect memory map.
*/
#define MC_CMD_CSR_WRITE32 0xd
+#define MC_CMD_CSR_WRITE32_MSGSET 0xd
#undef MC_CMD_0xd_PRIVILEGE_CTG
#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -2811,6 +3482,7 @@
* MCDI command to avoid creating too many MCDI commands.
*/
#define MC_CMD_HP 0x54
+#define MC_CMD_HP_MSGSET 0x54
#undef MC_CMD_0x54_PRIVILEGE_CTG
#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -2834,7 +3506,13 @@
#define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
#define MC_CMD_HP_IN_OCSD_ADDR_LEN 8
#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
+#define MC_CMD_HP_IN_OCSD_ADDR_LO_LEN 4
+#define MC_CMD_HP_IN_OCSD_ADDR_LO_LBN 32
+#define MC_CMD_HP_IN_OCSD_ADDR_LO_WIDTH 32
#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
+#define MC_CMD_HP_IN_OCSD_ADDR_HI_LEN 4
+#define MC_CMD_HP_IN_OCSD_ADDR_HI_LBN 64
+#define MC_CMD_HP_IN_OCSD_ADDR_HI_WIDTH 32
/* The requested update interval, in seconds. (Or the sub-command if ADDR is
* NULL.)
*/
@@ -2858,6 +3536,7 @@
* Get stack information.
*/
#define MC_CMD_STACKINFO 0xf
+#define MC_CMD_STACKINFO_MSGSET 0xf
#undef MC_CMD_0xf_PRIVILEGE_CTG
#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -2884,6 +3563,7 @@
* MDIO register read.
*/
#define MC_CMD_MDIO_READ 0x10
+#define MC_CMD_MDIO_READ_MSGSET 0x10
#undef MC_CMD_0x10_PRIVILEGE_CTG
#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -2932,6 +3612,7 @@
* MDIO register write.
*/
#define MC_CMD_MDIO_WRITE 0x11
+#define MC_CMD_MDIO_WRITE_MSGSET 0x11
#undef MC_CMD_0x11_PRIVILEGE_CTG
#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -2980,6 +3661,7 @@
* Write DBI register(s).
*/
#define MC_CMD_DBI_WRITE 0x12
+#define MC_CMD_DBI_WRITE_MSGSET 0x12
#undef MC_CMD_0x12_PRIVILEGE_CTG
#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3033,6 +3715,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_READ32 0x14
+#define MC_CMD_PORT_READ32_MSGSET 0x14
/* MC_CMD_PORT_READ32_IN msgrequest */
#define MC_CMD_PORT_READ32_IN_LEN 4
@@ -3056,6 +3739,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_WRITE32 0x15
+#define MC_CMD_PORT_WRITE32_MSGSET 0x15
/* MC_CMD_PORT_WRITE32_IN msgrequest */
#define MC_CMD_PORT_WRITE32_IN_LEN 8
@@ -3079,6 +3763,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_READ128 0x16
+#define MC_CMD_PORT_READ128_MSGSET 0x16
/* MC_CMD_PORT_READ128_IN msgrequest */
#define MC_CMD_PORT_READ128_IN_LEN 4
@@ -3102,6 +3787,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_WRITE128 0x17
+#define MC_CMD_PORT_WRITE128_MSGSET 0x17
/* MC_CMD_PORT_WRITE128_IN msgrequest */
#define MC_CMD_PORT_WRITE128_IN_LEN 20
@@ -3150,6 +3836,7 @@
* Returns the MC firmware configuration structure.
*/
#define MC_CMD_GET_BOARD_CFG 0x18
+#define MC_CMD_GET_BOARD_CFG_MSGSET 0x18
#undef MC_CMD_0x18_PRIVILEGE_CTG
#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3225,6 +3912,7 @@
* Read DBI register(s) -- extended functionality
*/
#define MC_CMD_DBI_READX 0x19
+#define MC_CMD_DBI_READX_MSGSET 0x19
#undef MC_CMD_0x19_PRIVILEGE_CTG
#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3239,7 +3927,13 @@
#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
+#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 4
+#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 0
+#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_WIDTH 32
#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
+#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 4
+#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LBN 32
+#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_WIDTH 32
#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127
@@ -3283,6 +3977,7 @@
* Set the 16byte seed for the MC pseudo-random generator.
*/
#define MC_CMD_SET_RAND_SEED 0x1a
+#define MC_CMD_SET_RAND_SEED_MSGSET 0x1a
#undef MC_CMD_0x1a_PRIVILEGE_CTG
#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3302,6 +3997,7 @@
* Retrieve the history of the LTSSM, if the build supports it.
*/
#define MC_CMD_LTSSM_HIST 0x1b
+#define MC_CMD_LTSSM_HIST_MSGSET 0x1b
/* MC_CMD_LTSSM_HIST_IN msgrequest */
#define MC_CMD_LTSSM_HIST_IN_LEN 0
@@ -3330,6 +4026,7 @@
* platforms.
*/
#define MC_CMD_DRV_ATTACH 0x1c
+#define MC_CMD_DRV_ATTACH_MSGSET 0x1c
#undef MC_CMD_0x1c_PRIVILEGE_CTG
#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3524,6 +4221,7 @@
* Route UART output to circular buffer in shared memory instead.
*/
#define MC_CMD_SHMUART 0x1f
+#define MC_CMD_SHMUART_MSGSET 0x1f
/* MC_CMD_SHMUART_IN msgrequest */
#define MC_CMD_SHMUART_IN_LEN 4
@@ -3542,6 +4240,7 @@
* use MC_CMD_ENTITY_RESET instead.
*/
#define MC_CMD_PORT_RESET 0x20
+#define MC_CMD_PORT_RESET_MSGSET 0x20
#undef MC_CMD_0x20_PRIVILEGE_CTG
#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3560,6 +4259,7 @@
* extended version of the deprecated MC_CMD_PORT_RESET with added fields.
*/
#define MC_CMD_ENTITY_RESET 0x20
+#define MC_CMD_ENTITY_RESET_MSGSET 0x20
/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
/* MC_CMD_ENTITY_RESET_IN msgrequest */
@@ -3582,6 +4282,7 @@
* Read instantaneous and minimum flow control thresholds.
*/
#define MC_CMD_PCIE_CREDITS 0x21
+#define MC_CMD_PCIE_CREDITS_MSGSET 0x21
/* MC_CMD_PCIE_CREDITS_IN msgrequest */
#define MC_CMD_PCIE_CREDITS_IN_LEN 8
@@ -3617,6 +4318,7 @@
* Get histogram of RX queue fill level.
*/
#define MC_CMD_RXD_MONITOR 0x22
+#define MC_CMD_RXD_MONITOR_MSGSET 0x22
/* MC_CMD_RXD_MONITOR_IN msgrequest */
#define MC_CMD_RXD_MONITOR_IN_LEN 12
@@ -3676,6 +4378,7 @@
* Copy the given ASCII string out onto UART and/or out of the network port.
*/
#define MC_CMD_PUTS 0x23
+#define MC_CMD_PUTS_MSGSET 0x23
#undef MC_CMD_0x23_PRIVILEGE_CTG
#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3712,6 +4415,7 @@
* 'zombie' state. Locks required: None
*/
#define MC_CMD_GET_PHY_CFG 0x24
+#define MC_CMD_GET_PHY_CFG_MSGSET 0x24
#undef MC_CMD_0x24_PRIVILEGE_CTG
#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3868,6 +4572,7 @@
* Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
*/
#define MC_CMD_START_BIST 0x25
+#define MC_CMD_START_BIST_MSGSET 0x25
#undef MC_CMD_0x25_PRIVILEGE_CTG
#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -3908,6 +4613,7 @@
* EACCES (if PHY_LOCK is not held).
*/
#define MC_CMD_POLL_BIST 0x26
+#define MC_CMD_POLL_BIST_MSGSET 0x26
#undef MC_CMD_0x26_PRIVILEGE_CTG
#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -4077,6 +4783,7 @@
* returns). The driver must still wait for flush done/failure events as usual.
*/
#define MC_CMD_FLUSH_RX_QUEUES 0x27
+#define MC_CMD_FLUSH_RX_QUEUES_MSGSET 0x27
/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
@@ -4099,6 +4806,7 @@
* Returns a bitmask of loopback modes available at each speed.
*/
#define MC_CMD_GET_LOOPBACK_MODES 0x28
+#define MC_CMD_GET_LOOPBACK_MODES_MSGSET 0x28
#undef MC_CMD_0x28_PRIVILEGE_CTG
#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4112,7 +4820,13 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LBN 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_WIDTH 32
/* enum: None. */
#define MC_CMD_LOOPBACK_NONE 0x0
/* enum: Data. */
@@ -4195,28 +4909,52 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LBN 64
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LBN 96
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LBN 128
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LBN 160
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LBN 192
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LBN 224
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LBN 256
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LBN 288
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
@@ -4228,7 +4966,13 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LBN 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_WIDTH 32
/* enum: None. */
/* MC_CMD_LOOPBACK_NONE 0x0 */
/* enum: Data. */
@@ -4311,49 +5055,91 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LBN 64
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LBN 96
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LBN 128
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LBN 160
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LBN 192
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LBN 224
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LBN 256
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LBN 288
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported 25G loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LBN 320
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LBN 352
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported 50 loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LBN 384
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LBN 416
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported 100G loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LBN 448
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LBN 480
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
@@ -4395,6 +5181,7 @@
* ETIME.
*/
#define MC_CMD_GET_LINK 0x29
+#define MC_CMD_GET_LINK_MSGSET 0x29
#undef MC_CMD_0x29_PRIVILEGE_CTG
#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4596,6 +5383,7 @@
* code: 0, EINVAL, ETIME, EAGAIN
*/
#define MC_CMD_SET_LINK 0x2a
+#define MC_CMD_SET_LINK_MSGSET 0x2a
#undef MC_CMD_0x2a_PRIVILEGE_CTG
#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -4686,6 +5474,7 @@
* Set identification LED state. Locks required: None. Return code: 0, EINVAL
*/
#define MC_CMD_SET_ID_LED 0x2b
+#define MC_CMD_SET_ID_LED_MSGSET 0x2b
#undef MC_CMD_0x2b_PRIVILEGE_CTG
#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -4708,6 +5497,7 @@
* Set MAC configuration. Locks required: None. Return code: 0, EINVAL
*/
#define MC_CMD_SET_MAC 0x2c
+#define MC_CMD_SET_MAC_MSGSET 0x2c
#undef MC_CMD_0x2c_PRIVILEGE_CTG
#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4724,7 +5514,13 @@
#define MC_CMD_SET_MAC_IN_ADDR_OFST 8
#define MC_CMD_SET_MAC_IN_ADDR_LEN 8
#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
+#define MC_CMD_SET_MAC_IN_ADDR_LO_LEN 4
+#define MC_CMD_SET_MAC_IN_ADDR_LO_LBN 64
+#define MC_CMD_SET_MAC_IN_ADDR_LO_WIDTH 32
#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
+#define MC_CMD_SET_MAC_IN_ADDR_HI_LEN 4
+#define MC_CMD_SET_MAC_IN_ADDR_HI_LBN 96
+#define MC_CMD_SET_MAC_IN_ADDR_HI_WIDTH 32
#define MC_CMD_SET_MAC_IN_REJECT_OFST 16
#define MC_CMD_SET_MAC_IN_REJECT_LEN 4
#define MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16
@@ -4765,7 +5561,13 @@
#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LBN 64
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_WIDTH 32
#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LBN 96
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_WIDTH 32
#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
#define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16
@@ -4816,6 +5618,129 @@
#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
+/* MC_CMD_SET_MAC_V3_IN msgrequest */
+#define MC_CMD_SET_MAC_V3_IN_LEN 40
+/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
+ * EtherII, VLAN, bug16011 padding).
+ */
+#define MC_CMD_SET_MAC_V3_IN_MTU_OFST 0
+#define MC_CMD_SET_MAC_V3_IN_MTU_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4
+#define MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_ADDR_OFST 8
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LEN 8
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_OFST 8
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LBN 64
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_OFST 12
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LBN 96
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_REJECT_OFST 16
+#define MC_CMD_SET_MAC_V3_IN_REJECT_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_OFST 16
+#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0
+#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_OFST 16
+#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_LBN 1
+#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_FCNTL_OFST 20
+#define MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4
+/* enum: Flow control is off. */
+/* MC_CMD_FCNTL_OFF 0x0 */
+/* enum: Respond to flow control. */
+/* MC_CMD_FCNTL_RESPOND 0x1 */
+/* enum: Respond to and Issue flow control. */
+/* MC_CMD_FCNTL_BIDIR 0x2 */
+/* enum: Auto neg flow control. */
+/* MC_CMD_FCNTL_AUTO 0x3 */
+/* enum: Priority flow control (eftest builds only). */
+/* MC_CMD_FCNTL_QBB 0x4 */
+/* enum: Issue flow control. */
+/* MC_CMD_FCNTL_GENERATE 0x5 */
+#define MC_CMD_SET_MAC_V3_IN_FLAGS_OFST 24
+#define MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_OFST 24
+#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0
+#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_WIDTH 1
+/* Select which parameters to configure. A parameter will only be modified if
+ * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
+ * capabilities then this field is ignored (and all flags are assumed to be
+ * set).
+ */
+#define MC_CMD_SET_MAC_V3_IN_CONTROL_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0
+#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_LBN 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_LBN 2
+#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_LBN 3
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 1
+/* Identifies the MAC to update by the specifying the end of a logical MAE
+ * link. Setting TARGET to MAE_LINK_ENDPOINT_COMPAT is equivalent to using the
+ * previous version of the command (MC_CMD_SET_MAC_EXT). Not all possible
+ * combinations of MPORT_END and MPORT_SELECTOR in TARGET will work in all
+ * circumstances. 1. Some will always work (e.g. a VF can always address its
+ * logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC), 2. Some are not
+ * meaningful and will always fail with EINVAL (e.g. attempting to address the
+ * VNIC end of a link to a physical port), 3. Some are meaningful but require
+ * the MCDI client to have the required permission and fail with EPERM
+ * otherwise (e.g. trying to set the MAC on a VF the caller cannot administer),
+ * and 4. Some could be implementation-specific and fail with ENOTSUP if not
+ * available (no examples exist right now). See SF-123581-TC section 4.3 for
+ * more details.
+ */
+#define MC_CMD_SET_MAC_V3_IN_TARGET_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LEN 8
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LBN 256
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_OFST 36
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LBN 288
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 35
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 256
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 276
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 272
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 34
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_OFST 36
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LEN 8
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LBN 256
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_OFST 36
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LBN 288
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_WIDTH 32
+
/* MC_CMD_SET_MAC_OUT msgresponse */
#define MC_CMD_SET_MAC_OUT_LEN 0
@@ -4839,6 +5764,7 @@
* Returns: 0, ETIME
*/
#define MC_CMD_PHY_STATS 0x2d
+#define MC_CMD_PHY_STATS_MSGSET 0x2d
#undef MC_CMD_0x2d_PRIVILEGE_CTG
#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -4849,7 +5775,13 @@
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_WIDTH 32
/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
@@ -4921,6 +5853,7 @@
* effect. Returns: 0, ETIME
*/
#define MC_CMD_MAC_STATS 0x2e
+#define MC_CMD_MAC_STATS_MSGSET 0x2e
#undef MC_CMD_0x2e_PRIVILEGE_CTG
#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4931,7 +5864,13 @@
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_MAC_STATS_IN_CMD_OFST 8
#define MC_CMD_MAC_STATS_IN_CMD_LEN 4
#define MC_CMD_MAC_STATS_IN_DMA_OFST 8
@@ -4974,7 +5913,13 @@
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
@@ -5130,7 +6075,13 @@
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
/* enum: Start of FEC stats buffer space, Medford2 and up */
#define MC_CMD_MAC_FEC_DMABUF_START 0x61
@@ -5163,7 +6114,13 @@
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
/* enum: Start of CTPIO stats buffer space, Medford2 and up */
#define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
@@ -5237,7 +6194,13 @@
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4
/* enum: Start of V4 stats buffer space */
#define MC_CMD_MAC_V4_DMABUF_START 0x79
@@ -5266,6 +6229,7 @@
* to be documented
*/
#define MC_CMD_SRIOV 0x30
+#define MC_CMD_SRIOV_MSGSET 0x30
/* MC_CMD_SRIOV_IN msgrequest */
#define MC_CMD_SRIOV_IN_LEN 12
@@ -5297,7 +6261,13 @@
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LBN 64
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LBN 96
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
@@ -5308,7 +6278,13 @@
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LBN 160
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LBN 192
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
@@ -5338,6 +6314,7 @@
* Returns: 0, EINVAL (invalid RID)
*/
#define MC_CMD_MEMCPY 0x31
+#define MC_CMD_MEMCPY_MSGSET 0x31
/* MC_CMD_MEMCPY_IN msgrequest */
#define MC_CMD_MEMCPY_IN_LENMIN 32
@@ -5361,6 +6338,7 @@
* Set a WoL filter.
*/
#define MC_CMD_WOL_FILTER_SET 0x32
+#define MC_CMD_WOL_FILTER_SET_MSGSET 0x32
#undef MC_CMD_0x32_PRIVILEGE_CTG
#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -5401,7 +6379,13 @@
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LBN 64
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_WIDTH 32
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LBN 96
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_WIDTH 32
/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
@@ -5476,6 +6460,7 @@
* Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
*/
#define MC_CMD_WOL_FILTER_REMOVE 0x33
+#define MC_CMD_WOL_FILTER_REMOVE_MSGSET 0x33
#undef MC_CMD_0x33_PRIVILEGE_CTG
#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -5495,6 +6480,7 @@
* ENOSYS
*/
#define MC_CMD_WOL_FILTER_RESET 0x34
+#define MC_CMD_WOL_FILTER_RESET_MSGSET 0x34
#undef MC_CMD_0x34_PRIVILEGE_CTG
#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -5515,6 +6501,7 @@
* Set the MCAST hash value without otherwise reconfiguring the MAC
*/
#define MC_CMD_SET_MCAST_HASH 0x35
+#define MC_CMD_SET_MCAST_HASH_MSGSET 0x35
/* MC_CMD_SET_MCAST_HASH_IN msgrequest */
#define MC_CMD_SET_MCAST_HASH_IN_LEN 32
@@ -5533,6 +6520,7 @@
* Locks required: none. Returns: 0
*/
#define MC_CMD_NVRAM_TYPES 0x36
+#define MC_CMD_NVRAM_TYPES_MSGSET 0x36
#undef MC_CMD_0x36_PRIVILEGE_CTG
#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5595,6 +6583,7 @@
* EINVAL (bad type).
*/
#define MC_CMD_NVRAM_INFO 0x37
+#define MC_CMD_NVRAM_INFO_MSGSET 0x37
#undef MC_CMD_0x37_PRIVILEGE_CTG
#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5692,6 +6681,7 @@
* EPERM.
*/
#define MC_CMD_NVRAM_UPDATE_START 0x38
+#define MC_CMD_NVRAM_UPDATE_START_MSGSET 0x38
#undef MC_CMD_0x38_PRIVILEGE_CTG
#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5732,6 +6722,7 @@
* PHY_LOCK required and not held)
*/
#define MC_CMD_NVRAM_READ 0x39
+#define MC_CMD_NVRAM_READ_MSGSET 0x39
#undef MC_CMD_0x39_PRIVILEGE_CTG
#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5803,6 +6794,7 @@
* PHY_LOCK required and not held)
*/
#define MC_CMD_NVRAM_WRITE 0x3a
+#define MC_CMD_NVRAM_WRITE_MSGSET 0x3a
#undef MC_CMD_0x3a_PRIVILEGE_CTG
#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5838,6 +6830,7 @@
* PHY_LOCK required and not held)
*/
#define MC_CMD_NVRAM_ERASE 0x3b
+#define MC_CMD_NVRAM_ERASE_MSGSET 0x3b
#undef MC_CMD_0x3b_PRIVILEGE_CTG
#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5868,6 +6861,7 @@
* the error EPERM.
*/
#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
+#define MC_CMD_NVRAM_UPDATE_FINISH_MSGSET 0x3c
#undef MC_CMD_0x3c_PRIVILEGE_CTG
#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5906,6 +6900,9 @@
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_OFST 8
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_LBN 3
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_WIDTH 1
/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
* response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
@@ -6036,6 +7033,7 @@
* DATALEN=0
*/
#define MC_CMD_REBOOT 0x3d
+#define MC_CMD_REBOOT_MSGSET 0x3d
#undef MC_CMD_0x3d_PRIVILEGE_CTG
#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -6057,6 +7055,7 @@
* thread address.
*/
#define MC_CMD_SCHEDINFO 0x3e
+#define MC_CMD_SCHEDINFO_MSGSET 0x3e
#undef MC_CMD_0x3e_PRIVILEGE_CTG
#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6083,6 +7082,7 @@
* mode to the specified value. Returns the old mode.
*/
#define MC_CMD_REBOOT_MODE 0x3f
+#define MC_CMD_REBOOT_MODE_MSGSET 0x3f
#undef MC_CMD_0x3f_PRIVILEGE_CTG
#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -6141,6 +7141,7 @@
* Locks required: None Returns: 0
*/
#define MC_CMD_SENSOR_INFO 0x41
+#define MC_CMD_SENSOR_INFO_MSGSET 0x41
#undef MC_CMD_0x41_PRIVILEGE_CTG
#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -6380,7 +7381,13 @@
#define MC_CMD_SENSOR_ENTRY_OFST 4
#define MC_CMD_SENSOR_ENTRY_LEN 8
#define MC_CMD_SENSOR_ENTRY_LO_OFST 4
+#define MC_CMD_SENSOR_ENTRY_LO_LEN 4
+#define MC_CMD_SENSOR_ENTRY_LO_LBN 32
+#define MC_CMD_SENSOR_ENTRY_LO_WIDTH 32
#define MC_CMD_SENSOR_ENTRY_HI_OFST 8
+#define MC_CMD_SENSOR_ENTRY_HI_LEN 4
+#define MC_CMD_SENSOR_ENTRY_HI_LBN 64
+#define MC_CMD_SENSOR_ENTRY_HI_WIDTH 32
#define MC_CMD_SENSOR_ENTRY_MINNUM 0
#define MC_CMD_SENSOR_ENTRY_MAXNUM 31
#define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127
@@ -6402,7 +7409,13 @@
/* MC_CMD_SENSOR_ENTRY_OFST 4 */
/* MC_CMD_SENSOR_ENTRY_LEN 8 */
/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
+/* MC_CMD_SENSOR_ENTRY_LO_LEN 4 */
+/* MC_CMD_SENSOR_ENTRY_LO_LBN 32 */
+/* MC_CMD_SENSOR_ENTRY_LO_WIDTH 32 */
/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
+/* MC_CMD_SENSOR_ENTRY_HI_LEN 4 */
+/* MC_CMD_SENSOR_ENTRY_HI_LBN 64 */
+/* MC_CMD_SENSOR_ENTRY_HI_WIDTH 32 */
/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
/* MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */
@@ -6445,6 +7458,7 @@
* STATE_WARNING. Otherwise the board should not be expected to function.
*/
#define MC_CMD_READ_SENSORS 0x42
+#define MC_CMD_READ_SENSORS_MSGSET 0x42
#undef MC_CMD_0x42_PRIVILEGE_CTG
#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -6459,7 +7473,13 @@
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_WIDTH 32
/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
@@ -6471,7 +7491,13 @@
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_WIDTH 32
/* Size in bytes of host buffer. */
#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
@@ -6486,7 +7512,13 @@
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LBN 32
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_WIDTH 32
/* Size in bytes of host buffer. */
#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8
#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
@@ -6540,6 +7572,7 @@
* code: 0
*/
#define MC_CMD_GET_PHY_STATE 0x43
+#define MC_CMD_GET_PHY_STATE_MSGSET 0x43
#undef MC_CMD_0x43_PRIVILEGE_CTG
#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -6563,6 +7596,7 @@
* disable 802.Qbb for a given priority.
*/
#define MC_CMD_SETUP_8021QBB 0x44
+#define MC_CMD_SETUP_8021QBB_MSGSET 0x44
/* MC_CMD_SETUP_8021QBB_IN msgrequest */
#define MC_CMD_SETUP_8021QBB_IN_LEN 32
@@ -6578,6 +7612,7 @@
* Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
*/
#define MC_CMD_WOL_FILTER_GET 0x45
+#define MC_CMD_WOL_FILTER_GET_MSGSET 0x45
#undef MC_CMD_0x45_PRIVILEGE_CTG
#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -6597,6 +7632,7 @@
* Returns: 0, ENOSYS
*/
#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
+#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_MSGSET 0x46
#undef MC_CMD_0x46_PRIVILEGE_CTG
#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -6649,6 +7685,7 @@
* None. Returns: 0, ENOSYS
*/
#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
+#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_MSGSET 0x47
#undef MC_CMD_0x47_PRIVILEGE_CTG
#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -6669,6 +7706,7 @@
* Restore MAC after block reset. Locks required: None. Returns: 0.
*/
#define MC_CMD_MAC_RESET_RESTORE 0x48
+#define MC_CMD_MAC_RESET_RESTORE_MSGSET 0x48
/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
@@ -6684,6 +7722,7 @@
* required: None Returns: 0
*/
#define MC_CMD_TESTASSERT 0x49
+#define MC_CMD_TESTASSERT_MSGSET 0x49
#undef MC_CMD_0x49_PRIVILEGE_CTG
#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -6727,6 +7766,7 @@
* basis. Locks required: None. Returns: 0, EINVAL .
*/
#define MC_CMD_WORKAROUND 0x4a
+#define MC_CMD_WORKAROUND_MSGSET 0x4a
#undef MC_CMD_0x4a_PRIVILEGE_CTG
#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6790,6 +7830,7 @@
* Anything else: currently undefined. Locks required: None. Return code: 0.
*/
#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
+#define MC_CMD_GET_PHY_MEDIA_INFO_MSGSET 0x4b
#undef MC_CMD_0x4b_PRIVILEGE_CTG
#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6821,6 +7862,7 @@
* on the type of partition).
*/
#define MC_CMD_NVRAM_TEST 0x4c
+#define MC_CMD_NVRAM_TEST_MSGSET 0x4c
#undef MC_CMD_0x4c_PRIVILEGE_CTG
#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -6851,6 +7893,7 @@
* they are configured first. Locks required: None. Return code: 0, EINVAL.
*/
#define MC_CMD_MRSFP_TWEAK 0x4d
+#define MC_CMD_MRSFP_TWEAK_MSGSET 0x4d
/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
@@ -6894,6 +7937,7 @@
* of range.
*/
#define MC_CMD_SENSOR_SET_LIMS 0x4e
+#define MC_CMD_SENSOR_SET_LIMS_MSGSET 0x4e
#undef MC_CMD_0x4e_PRIVILEGE_CTG
#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -6925,6 +7969,7 @@
/* MC_CMD_GET_RESOURCE_LIMITS
*/
#define MC_CMD_GET_RESOURCE_LIMITS 0x4f
+#define MC_CMD_GET_RESOURCE_LIMITS_MSGSET 0x4f
/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
@@ -6947,6 +7992,7 @@
* none. Returns: 0, EINVAL (bad type).
*/
#define MC_CMD_NVRAM_PARTITIONS 0x51
+#define MC_CMD_NVRAM_PARTITIONS_MSGSET 0x51
#undef MC_CMD_0x51_PRIVILEGE_CTG
#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6977,6 +8023,7 @@
* none. Returns: 0, EINVAL (bad type).
*/
#define MC_CMD_NVRAM_METADATA 0x52
+#define MC_CMD_NVRAM_METADATA_MSGSET 0x52
#undef MC_CMD_0x52_PRIVILEGE_CTG
#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -7035,6 +8082,7 @@
* Returns the base MAC, count and stride for the requesting function
*/
#define MC_CMD_GET_MAC_ADDRESSES 0x55
+#define MC_CMD_GET_MAC_ADDRESSES_MSGSET 0x55
#undef MC_CMD_0x55_PRIVILEGE_CTG
#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -7066,6 +8114,7 @@
* SF-120509-TC and SF-117282-PS.
*/
#define MC_CMD_CLP 0x56
+#define MC_CMD_CLP_MSGSET 0x56
#undef MC_CMD_0x56_PRIVILEGE_CTG
#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -7188,6 +8237,7 @@
* Perform a MUM operation
*/
#define MC_CMD_MUM 0x57
+#define MC_CMD_MUM_MSGSET 0x57
#undef MC_CMD_0x57_PRIVILEGE_CTG
#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -7604,7 +8654,13 @@
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 4
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LBN 32
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_WIDTH 32
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 4
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LBN 64
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_WIDTH 32
/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
#define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
@@ -7789,7 +8845,13 @@
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 4
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LBN 64
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_WIDTH 32
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 4
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LBN 96
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_WIDTH 32
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126
@@ -7986,6 +9048,7 @@
* sensor_query SPHINX service.
*/
#define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
+#define MC_CMD_DYNAMIC_SENSORS_LIST_MSGSET 0x66
#undef MC_CMD_0x66_PRIVILEGE_CTG
#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8031,6 +9094,7 @@
* `get_descriptions` in the sensor_query SPHINX service.
*/
#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_MSGSET 0x67
#undef MC_CMD_0x67_PRIVILEGE_CTG
#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8080,6 +9144,7 @@
* in the sensor_query SPHINX service.
*/
#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_MSGSET 0x68
#undef MC_CMD_0x68_PRIVILEGE_CTG
#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8117,6 +9182,7 @@
* receive (Riverhead).
*/
#define MC_CMD_EVENT_CTRL 0x69
+#define MC_CMD_EVENT_CTRL_MSGSET 0x69
#undef MC_CMD_0x69_PRIVILEGE_CTG
#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8197,7 +9263,13 @@
#define BUFTBL_ENTRY_RAWADDR_OFST 4
#define BUFTBL_ENTRY_RAWADDR_LEN 8
#define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
+#define BUFTBL_ENTRY_RAWADDR_LO_LEN 4
+#define BUFTBL_ENTRY_RAWADDR_LO_LBN 32
+#define BUFTBL_ENTRY_RAWADDR_LO_WIDTH 32
#define BUFTBL_ENTRY_RAWADDR_HI_OFST 8
+#define BUFTBL_ENTRY_RAWADDR_HI_LEN 4
+#define BUFTBL_ENTRY_RAWADDR_HI_LBN 64
+#define BUFTBL_ENTRY_RAWADDR_HI_WIDTH 32
#define BUFTBL_ENTRY_RAWADDR_LBN 32
#define BUFTBL_ENTRY_RAWADDR_WIDTH 64
@@ -8207,14 +9279,25 @@
#define NVRAM_PARTITION_TYPE_ID_LEN 2
/* enum: Primary MC firmware partition */
#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
+/* enum: NMC firmware partition (this is intentionally an alias of MC_FIRMWARE)
+ */
+#define NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100
/* enum: Secondary MC firmware partition */
#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
/* enum: Expansion ROM partition */
#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
/* enum: Static configuration TLV partition */
#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
+/* enum: Factory configuration TLV partition (this is intentionally an alias of
+ * STATIC_CONFIG)
+ */
+#define NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400
/* enum: Dynamic configuration TLV partition */
#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
+/* enum: User configuration TLV partition (this is intentionally an alias of
+ * DYNAMIC_CONFIG)
+ */
+#define NVRAM_PARTITION_TYPE_USER_CONFIG 0x500
/* enum: Expansion ROM configuration data for port 0 */
#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
@@ -8227,10 +9310,16 @@
#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
/* enum: Non-volatile log output partition */
#define NVRAM_PARTITION_TYPE_LOG 0x700
+/* enum: Non-volatile log output partition for NMC firmware (this is
+ * intentionally an alias of LOG)
+ */
+#define NVRAM_PARTITION_TYPE_NMC_LOG 0x700
/* enum: Non-volatile log output of second core on dual-core device */
#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
/* enum: Device state dump output partition */
#define NVRAM_PARTITION_TYPE_DUMP 0x800
+/* enum: Crash log partition for NMC firmware */
+#define NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801
/* enum: Application license key storage partition */
#define NVRAM_PARTITION_TYPE_LICENSE 0x900
/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
@@ -8247,6 +9336,20 @@
#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
/* enum: Non-volatile log output partition for FC */
#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
+/* enum: FPGA Stage 1 bitstream */
+#define NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05
+/* enum: FPGA Stage 2 bitstream */
+#define NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06
+/* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */
+#define NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07
+/* enum: FPGA User XCLBIN (this is intentionally an alias of FPGA_REGION0) */
+#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07
+/* enum: FPGA jump instruction (a.k.a. boot) partition to select Stage1
+ * bitstream
+ */
+#define NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08
+/* enum: FPGA Validate XCLBIN */
+#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09
/* enum: MUM firmware partition */
#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
/* enum: SUC firmware partition (this is intentionally an alias of
@@ -8255,6 +9358,10 @@
#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
/* enum: MUM Non-volatile log output partition. */
#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
+/* enum: SUC Non-volatile log output partition (this is intentionally an alias
+ * of MUM_LOG).
+ */
+#define NVRAM_PARTITION_TYPE_SUC_LOG 0xc01
/* enum: MUM Application table partition. */
#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
/* enum: MUM boot rom partition. */
@@ -8269,6 +9376,10 @@
#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
/* enum: Used by the expansion ROM for logging */
#define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
+/* enum: Non-volatile log output partition for Expansion ROM (this is
+ * intentionally an alias of PXE_LOG).
+ */
+#define NVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000
/* enum: Used for XIP code of shmbooted images */
#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
/* enum: Spare partition 2 */
@@ -8277,6 +9388,10 @@
* between XJTAG and Manftest.
*/
#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
+/* enum: Deployment configuration TLV partition (this is intentionally an alias
+ * of MANUFACTURING)
+ */
+#define NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300
/* enum: Spare partition 4 */
#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
/* enum: Spare partition 5 */
@@ -8312,14 +9427,43 @@
#define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */
#define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
+/* enum: Test partition on SmartNIC system microcontroller (SUC) */
+#define NVRAM_PARTITION_TYPE_SUC_TEST 0x1f00
+/* enum: System microcontroller access to primary FPGA flash. */
+#define NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01
+/* enum: System microcontroller access to secondary FPGA flash (if present) */
+#define NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02
+/* enum: System microcontroller access to primary System-on-Chip flash */
+#define NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03
+/* enum: System microcontroller access to secondary System-on-Chip flash (if
+ * present)
+ */
+#define NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04
+/* enum: System microcontroller critical failure logs. Contains structured
+ * details of sensors leading up to a critical failure (where the board is shut
+ * down).
+ */
+#define NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05
+/* enum: System-on-Chip configuration information (see XN-200467-PS). */
+#define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07
+/* enum: System-on-Chip update information. */
+#define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003
/* enum: Start of reserved value range (firmware may use for any purpose) */
#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
/* enum: End of reserved value range (firmware may use for any purpose) */
#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
/* enum: Recovery partition map (provided if real map is missing or corrupt) */
#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
+/* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is
+ * intentionally an alias of RECOVERY_MAP)
+ */
+#define NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe
/* enum: Partition map (real map as stored in flash) */
#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
+/* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an
+ * alias of PARTITION_MAP)
+ */
+#define NVRAM_PARTITION_TYPE_FPT 0xffff
#define NVRAM_PARTITION_TYPE_ID_LBN 0
#define NVRAM_PARTITION_TYPE_ID_WIDTH 16
@@ -8368,7 +9512,13 @@
#define LICENSED_FEATURES_MASK_OFST 0
#define LICENSED_FEATURES_MASK_LEN 8
#define LICENSED_FEATURES_MASK_LO_OFST 0
+#define LICENSED_FEATURES_MASK_LO_LEN 4
+#define LICENSED_FEATURES_MASK_LO_LBN 0
+#define LICENSED_FEATURES_MASK_LO_WIDTH 32
#define LICENSED_FEATURES_MASK_HI_OFST 4
+#define LICENSED_FEATURES_MASK_HI_LEN 4
+#define LICENSED_FEATURES_MASK_HI_LBN 32
+#define LICENSED_FEATURES_MASK_HI_WIDTH 32
#define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
@@ -8408,7 +9558,13 @@
#define LICENSED_V3_APPS_MASK_OFST 0
#define LICENSED_V3_APPS_MASK_LEN 8
#define LICENSED_V3_APPS_MASK_LO_OFST 0
+#define LICENSED_V3_APPS_MASK_LO_LEN 4
+#define LICENSED_V3_APPS_MASK_LO_LBN 0
+#define LICENSED_V3_APPS_MASK_LO_WIDTH 32
#define LICENSED_V3_APPS_MASK_HI_OFST 4
+#define LICENSED_V3_APPS_MASK_HI_LEN 4
+#define LICENSED_V3_APPS_MASK_HI_LBN 32
+#define LICENSED_V3_APPS_MASK_HI_WIDTH 32
#define LICENSED_V3_APPS_ONLOAD_OFST 0
#define LICENSED_V3_APPS_ONLOAD_LBN 0
#define LICENSED_V3_APPS_ONLOAD_WIDTH 1
@@ -8466,7 +9622,13 @@
#define LICENSED_V3_FEATURES_MASK_OFST 0
#define LICENSED_V3_FEATURES_MASK_LEN 8
#define LICENSED_V3_FEATURES_MASK_LO_OFST 0
+#define LICENSED_V3_FEATURES_MASK_LO_LEN 4
+#define LICENSED_V3_FEATURES_MASK_LO_LBN 0
+#define LICENSED_V3_FEATURES_MASK_LO_WIDTH 32
#define LICENSED_V3_FEATURES_MASK_HI_OFST 4
+#define LICENSED_V3_FEATURES_MASK_HI_LEN 4
+#define LICENSED_V3_FEATURES_MASK_HI_LBN 32
+#define LICENSED_V3_FEATURES_MASK_HI_WIDTH 32
#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
@@ -8617,6 +9779,7 @@
* Get a dump of the MCPU registers
*/
#define MC_CMD_READ_REGS 0x50
+#define MC_CMD_READ_REGS_MSGSET 0x50
#undef MC_CMD_0x50_PRIVILEGE_CTG
#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -8643,6 +9806,7 @@
* end with an address for each 4k of host memory required to back the EVQ.
*/
#define MC_CMD_INIT_EVQ 0x80
+#define MC_CMD_INIT_EVQ_MSGSET 0x80
#undef MC_CMD_0x80_PRIVILEGE_CTG
#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8657,7 +9821,8 @@
#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
#define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
@@ -8729,7 +9894,13 @@
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LBN 288
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LBN 320
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 64
@@ -8750,7 +9921,8 @@
#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
@@ -8847,7 +10019,13 @@
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LBN 288
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LBN 320
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 64
@@ -8900,6 +10078,7 @@
* the RXQ.
*/
#define MC_CMD_INIT_RXQ 0x81
+#define MC_CMD_INIT_RXQ_MSGSET 0x81
#undef MC_CMD_0x81_PRIVILEGE_CTG
#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8923,7 +10102,8 @@
#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
@@ -8964,7 +10144,13 @@
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
@@ -8988,7 +10174,8 @@
#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
@@ -9062,7 +10249,13 @@
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9085,7 +10278,8 @@
#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
@@ -9159,7 +10353,13 @@
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9211,7 +10411,8 @@
#define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
@@ -9285,7 +10486,13 @@
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9350,7 +10557,8 @@
#define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
@@ -9424,7 +10632,13 @@
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9497,6 +10711,7 @@
/* MC_CMD_INIT_TXQ
*/
#define MC_CMD_INIT_TXQ 0x82
+#define MC_CMD_INIT_TXQ_MSGSET 0x82
#undef MC_CMD_0x82_PRIVILEGE_CTG
#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9521,7 +10736,8 @@
#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
#define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
@@ -9565,7 +10781,13 @@
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
@@ -9586,7 +10808,8 @@
#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
@@ -9648,7 +10871,13 @@
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64
@@ -9674,6 +10903,7 @@
* or the operation will fail with EBUSY
*/
#define MC_CMD_FINI_EVQ 0x83
+#define MC_CMD_FINI_EVQ_MSGSET 0x83
#undef MC_CMD_0x83_PRIVILEGE_CTG
#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9695,6 +10925,7 @@
* Teardown a RXQ.
*/
#define MC_CMD_FINI_RXQ 0x84
+#define MC_CMD_FINI_RXQ_MSGSET 0x84
#undef MC_CMD_0x84_PRIVILEGE_CTG
#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9714,6 +10945,7 @@
* Teardown a TXQ.
*/
#define MC_CMD_FINI_TXQ 0x85
+#define MC_CMD_FINI_TXQ_MSGSET 0x85
#undef MC_CMD_0x85_PRIVILEGE_CTG
#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9733,6 +10965,7 @@
* Generate an event on an EVQ belonging to the function issuing the command.
*/
#define MC_CMD_DRIVER_EVENT 0x86
+#define MC_CMD_DRIVER_EVENT_MSGSET 0x86
#undef MC_CMD_0x86_PRIVILEGE_CTG
#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9746,7 +10979,13 @@
#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
+#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 4
+#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LBN 32
+#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_WIDTH 32
#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
+#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 4
+#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LBN 64
+#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_WIDTH 32
/* MC_CMD_DRIVER_EVENT_OUT msgresponse */
#define MC_CMD_DRIVER_EVENT_OUT_LEN 0
@@ -9760,6 +10999,7 @@
* MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
*/
#define MC_CMD_PROXY_CMD 0x5b
+#define MC_CMD_PROXY_CMD_MSGSET 0x5b
#undef MC_CMD_0x5b_PRIVILEGE_CTG
#define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -9828,6 +11068,7 @@
* a designated admin function
*/
#define MC_CMD_PROXY_CONFIGURE 0x58
+#define MC_CMD_PROXY_CONFIGURE_MSGSET 0x58
#undef MC_CMD_0x58_PRIVILEGE_CTG
#define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -9845,7 +11086,13 @@
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LBN 32
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LBN 64
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
@@ -9855,7 +11102,13 @@
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LBN 128
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LBN 160
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
@@ -9866,7 +11119,13 @@
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LBN 224
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LBN 256
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2, or zero if this buffer is not provided */
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
@@ -9890,7 +11149,13 @@
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LBN 32
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LBN 64
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
@@ -9900,7 +11165,13 @@
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LBN 128
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LBN 160
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
@@ -9911,7 +11182,13 @@
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LBN 224
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LBN 256
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2, or zero if this buffer is not provided */
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
@@ -9936,6 +11213,7 @@
* MC_CMD_PROXY_CONFIGURE).
*/
#define MC_CMD_PROXY_COMPLETE 0x5f
+#define MC_CMD_PROXY_COMPLETE_MSGSET 0x5f
#undef MC_CMD_0x5f_PRIVILEGE_CTG
#define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -9974,6 +11252,7 @@
* cannot do so). The buffer table entries will initially be zeroed.
*/
#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
+#define MC_CMD_ALLOC_BUFTBL_CHUNK_MSGSET 0x87
#undef MC_CMD_0x87_PRIVILEGE_CTG
#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -10005,6 +11284,7 @@
* Reprogram a set of buffer table entries in the specified chunk.
*/
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_MSGSET 0x88
#undef MC_CMD_0x88_PRIVILEGE_CTG
#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -10027,7 +11307,13 @@
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LEN 4
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LBN 96
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_WIDTH 32
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LEN 4
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LBN 128
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_WIDTH 32
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 32
@@ -10040,6 +11326,7 @@
/* MC_CMD_FREE_BUFTBL_CHUNK
*/
#define MC_CMD_FREE_BUFTBL_CHUNK 0x89
+#define MC_CMD_FREE_BUFTBL_CHUNK_MSGSET 0x89
#undef MC_CMD_0x89_PRIVILEGE_CTG
#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -10058,6 +11345,7 @@
* Multiplexed MCDI call for filter operations
*/
#define MC_CMD_FILTER_OP 0x8a
+#define MC_CMD_FILTER_OP_MSGSET 0x8a
#undef MC_CMD_0x8a_PRIVILEGE_CTG
#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -10083,7 +11371,13 @@
#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_IN_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_IN_HANDLE_HI_WIDTH 32
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
@@ -10239,7 +11533,13 @@
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_WIDTH 32
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
@@ -10518,7 +11818,13 @@
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_WIDTH 32
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12
@@ -10779,15 +12085,15 @@
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16
-/* Flags controlling mutations of the user_mark and user_flag fields of
- * matching packets, with logic as follows: if (req.MATCH_BITOR_FLAG == 1)
- * user_flag = req.MATCH_SET_FLAG bit_or user_flag; else user_flag =
- * req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark = 0; else if
- * (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK bit_or user_mark;
- * else user_mark = req.MATCH_SET_MARK; N.B. These flags overlap with the
- * MATCH_ACTION field, which is deprecated in favour of this field. For the
- * cases where these flags induce a valid encoding of the MATCH_ACTION field,
- * the semantics agree.
+/* Flags controlling mutations of the packet and/or metadata when the filter is
+ * matched. The user_mark and user_flag fields' logic is as follows: if
+ * (req.MATCH_BITOR_FLAG == 1) user_flag = req.MATCH_SET_FLAG bit_or user_flag;
+ * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark
+ * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK
+ * bit_or user_mark; else user_mark = req.MATCH_SET_MARK; N.B. These flags
+ * overlap with the MATCH_ACTION field, which is deprecated in favour of this
+ * field. For the cases where these flags induce a valid encoding of the
+ * MATCH_ACTION field, the semantics agree.
*/
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_OFST 172
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4
@@ -10803,6 +12109,9 @@
#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_OFST 172
#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_LBN 3
#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_WIDTH 1
+#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_OFST 172
+#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 4
+#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_WIDTH 1
/* Deprecated: the overlapping MATCH_ACTION_FLAGS field exposes all of the
* functionality of this field in an ABI-backwards-compatible manner, and
* should be used instead. Any future extensions should be made to the
@@ -10848,7 +12157,13 @@
#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_WIDTH 32
/* enum: guaranteed invalid filter handle (low 32 bits) */
#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
/* enum: guaranteed invalid filter handle (high 32 bits) */
@@ -10868,7 +12183,13 @@
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_WIDTH 32
/* Enum values, see field(s): */
/* MC_CMD_FILTER_OP_OUT/HANDLE */
@@ -10878,6 +12199,7 @@
* Get information related to the parser-dispatcher subsystem
*/
#define MC_CMD_GET_PARSER_DISP_INFO 0xe4
+#define MC_CMD_GET_PARSER_DISP_INFO_MSGSET 0xe4
#undef MC_CMD_0xe4_PRIVILEGE_CTG
#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11025,6 +12347,7 @@
* permitted.
*/
#define MC_CMD_PARSER_DISP_RW 0xe5
+#define MC_CMD_PARSER_DISP_RW_MSGSET 0xe5
#undef MC_CMD_0xe5_PRIVILEGE_CTG
#define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11115,6 +12438,7 @@
* Get number of PFs on the device.
*/
#define MC_CMD_GET_PF_COUNT 0xb6
+#define MC_CMD_GET_PF_COUNT_MSGSET 0xb6
#undef MC_CMD_0xb6_PRIVILEGE_CTG
#define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11134,6 +12458,7 @@
* Set number of PFs on the device.
*/
#define MC_CMD_SET_PF_COUNT 0xb7
+#define MC_CMD_SET_PF_COUNT_MSGSET 0xb7
/* MC_CMD_SET_PF_COUNT_IN msgrequest */
#define MC_CMD_SET_PF_COUNT_IN_LEN 4
@@ -11150,6 +12475,7 @@
* Get port assignment for current PCI function.
*/
#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
+#define MC_CMD_GET_PORT_ASSIGNMENT_MSGSET 0xb8
#undef MC_CMD_0xb8_PRIVILEGE_CTG
#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11175,6 +12501,7 @@
* Set port assignment for current PCI function.
*/
#define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
+#define MC_CMD_SET_PORT_ASSIGNMENT_MSGSET 0xb9
#undef MC_CMD_0xb9_PRIVILEGE_CTG
#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11194,6 +12521,7 @@
* Allocate VIs for current PCI function.
*/
#define MC_CMD_ALLOC_VIS 0x8b
+#define MC_CMD_ALLOC_VIS_MSGSET 0x8b
#undef MC_CMD_0x8b_PRIVILEGE_CTG
#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11241,6 +12569,7 @@
* but not freed.
*/
#define MC_CMD_FREE_VIS 0x8c
+#define MC_CMD_FREE_VIS_MSGSET 0x8c
#undef MC_CMD_0x8c_PRIVILEGE_CTG
#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11257,6 +12586,7 @@
* Get SRIOV config for this PF.
*/
#define MC_CMD_GET_SRIOV_CFG 0xba
+#define MC_CMD_GET_SRIOV_CFG_MSGSET 0xba
#undef MC_CMD_0xba_PRIVILEGE_CTG
#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11290,6 +12620,7 @@
* Set SRIOV config for this PF.
*/
#define MC_CMD_SET_SRIOV_CFG 0xbb
+#define MC_CMD_SET_SRIOV_CFG_MSGSET 0xbb
#undef MC_CMD_0xbb_PRIVILEGE_CTG
#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11325,9 +12656,11 @@
/***********************************/
/* MC_CMD_GET_VI_ALLOC_INFO
* Get information about number of VI's and base VI number allocated to this
- * function.
+ * function. This message is not available to dynamic clients created by
+ * MC_CMD_CLIENT_ALLOC.
*/
#define MC_CMD_GET_VI_ALLOC_INFO 0x8d
+#define MC_CMD_GET_VI_ALLOC_INFO_MSGSET 0x8d
#undef MC_CMD_0x8d_PRIVILEGE_CTG
#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11352,9 +12685,12 @@
/***********************************/
/* MC_CMD_DUMP_VI_STATE
- * For CmdClient use. Dump pertinent information on a specific absolute VI.
+ * For CmdClient use. Dump pertinent information on a specific absolute VI. The
+ * VI must be owned by the calling client or one of its ancestors; usership of
+ * the VI (as set by MC_CMD_SET_VI_USER) is not sufficient.
*/
#define MC_CMD_DUMP_VI_STATE 0x8e
+#define MC_CMD_DUMP_VI_STATE_MSGSET 0x8e
#undef MC_CMD_0x8e_PRIVILEGE_CTG
#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11366,7 +12702,7 @@
#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
-#define MC_CMD_DUMP_VI_STATE_OUT_LEN 96
+#define MC_CMD_DUMP_VI_STATE_OUT_LEN 100
/* The PF part of the function owning this VI. */
#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
@@ -11389,12 +12725,24 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LBN 96
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LBN 128
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_WIDTH 32
/* Raw evq timer table data. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LBN 160
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LBN 192
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_WIDTH 32
/* Combined metadata field. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
@@ -11411,22 +12759,46 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LBN 256
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LBN 288
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_WIDTH 32
/* TXDPCPU raw table data for queue. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LBN 320
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LBN 352
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_WIDTH 32
/* TXDPCPU raw table data for queue. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LBN 384
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LBN 416
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_WIDTH 32
/* Combined metadata field. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LBN 448
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LBN 480
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
@@ -11446,22 +12818,46 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LBN 512
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LBN 544
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_WIDTH 32
/* RXDPCPU raw table data for queue. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LBN 576
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LBN 608
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_WIDTH 32
/* Reserved, currently 0. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LBN 640
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LBN 672
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_WIDTH 32
/* Combined metadata field. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LBN 704
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LBN 736
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
@@ -11474,6 +12870,9 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
+/* Current user, as assigned by MC_CMD_SET_VI_USER. */
+#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_OFST 96
+#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_LEN 4
/***********************************/
@@ -11481,6 +12880,7 @@
* Allocate a push I/O buffer for later use with a tx queue.
*/
#define MC_CMD_ALLOC_PIOBUF 0x8f
+#define MC_CMD_ALLOC_PIOBUF_MSGSET 0x8f
#undef MC_CMD_0x8f_PRIVILEGE_CTG
#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -11500,6 +12900,7 @@
* Free a push I/O buffer.
*/
#define MC_CMD_FREE_PIOBUF 0x90
+#define MC_CMD_FREE_PIOBUF_MSGSET 0x90
#undef MC_CMD_0x90_PRIVILEGE_CTG
#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -11516,9 +12917,12 @@
/***********************************/
/* MC_CMD_GET_VI_TLP_PROCESSING
- * Get TLP steering and ordering information for a VI.
+ * Get TLP steering and ordering information for a VI. The caller must have the
+ * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
+ * an ancestor of the current user (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
+#define MC_CMD_GET_VI_TLP_PROCESSING_MSGSET 0xb0
#undef MC_CMD_0xb0_PRIVILEGE_CTG
#define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11555,9 +12959,12 @@
/***********************************/
/* MC_CMD_SET_VI_TLP_PROCESSING
- * Set TLP steering and ordering information for a VI.
+ * Set TLP steering and ordering information for a VI. The caller must have the
+ * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
+ * an ancestor of the current user (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
+#define MC_CMD_SET_VI_TLP_PROCESSING_MSGSET 0xb1
#undef MC_CMD_0xb1_PRIVILEGE_CTG
#define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11597,6 +13004,7 @@
* Get global PCIe steering and transaction processing configuration.
*/
#define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
+#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_MSGSET 0xbc
#undef MC_CMD_0xbc_PRIVILEGE_CTG
#define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11681,6 +13089,7 @@
* Set global PCIe steering and transaction processing configuration.
*/
#define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
+#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_MSGSET 0xbd
#undef MC_CMD_0xbd_PRIVILEGE_CTG
#define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11746,6 +13155,7 @@
* Download a new set of images to the satellite CPUs from the host.
*/
#define MC_CMD_SATELLITE_DOWNLOAD 0x91
+#define MC_CMD_SATELLITE_DOWNLOAD_MSGSET 0x91
#undef MC_CMD_0x91_PRIVILEGE_CTG
#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -11873,6 +13283,7 @@
* reference inherent device capabilities as opposed to current NVRAM config.
*/
#define MC_CMD_GET_CAPABILITIES 0xbe
+#define MC_CMD_GET_CAPABILITIES_MSGSET 0xbe
#undef MC_CMD_0xbe_PRIVILEGE_CTG
#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -14813,6 +16224,18 @@
#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */
#define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160
@@ -15299,6 +16722,18 @@
#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
@@ -15306,7 +16741,13 @@
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LBN 1216
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_WIDTH 32
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LBN 1248
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_WIDTH 32
/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */
#define MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184
@@ -15793,6 +17234,18 @@
#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
@@ -15800,7 +17253,13 @@
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LBN 1216
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_WIDTH 32
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LBN 1248
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_WIDTH 32
/* The minimum size (in table entries) of indirection table to be allocated
* from the pool for an RSS context. Note that the table size used must be a
* power of 2.
@@ -16322,6 +17781,18 @@
#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
@@ -16329,7 +17800,13 @@
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_OFST 152
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LEN 8
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_OFST 152
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LBN 1216
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_WIDTH 32
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_OFST 156
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LBN 1248
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_WIDTH 32
/* The minimum size (in table entries) of indirection table to be allocated
* from the pool for an RSS context. Note that the table size used must be a
* power of 2.
@@ -16386,6 +17863,7 @@
* Encapsulation for a v2 extended command
*/
#define MC_CMD_V2_EXTN 0x7f
+#define MC_CMD_V2_EXTN_MSGSET 0x7f
/* MC_CMD_V2_EXTN_IN msgrequest */
#define MC_CMD_V2_EXTN_IN_LEN 4
@@ -16417,6 +17895,7 @@
* Allocate a pacer bucket (for qau rp or a snapper test)
*/
#define MC_CMD_TCM_BUCKET_ALLOC 0xb2
+#define MC_CMD_TCM_BUCKET_ALLOC_MSGSET 0xb2
#undef MC_CMD_0xb2_PRIVILEGE_CTG
#define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16436,6 +17915,7 @@
* Free a pacer bucket
*/
#define MC_CMD_TCM_BUCKET_FREE 0xb3
+#define MC_CMD_TCM_BUCKET_FREE_MSGSET 0xb3
#undef MC_CMD_0xb3_PRIVILEGE_CTG
#define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16455,6 +17935,7 @@
* Initialise pacer bucket with a given rate
*/
#define MC_CMD_TCM_BUCKET_INIT 0xb4
+#define MC_CMD_TCM_BUCKET_INIT_MSGSET 0xb4
#undef MC_CMD_0xb4_PRIVILEGE_CTG
#define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16489,6 +17970,7 @@
* Initialise txq in pacer with given options or set options
*/
#define MC_CMD_TCM_TXQ_INIT 0xb5
+#define MC_CMD_TCM_TXQ_INIT_MSGSET 0xb5
#undef MC_CMD_0xb5_PRIVILEGE_CTG
#define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16579,6 +18061,7 @@
* Link a push I/O buffer to a TxQ
*/
#define MC_CMD_LINK_PIOBUF 0x92
+#define MC_CMD_LINK_PIOBUF_MSGSET 0x92
#undef MC_CMD_0x92_PRIVILEGE_CTG
#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -16588,7 +18071,7 @@
/* Handle for allocated push I/O buffer. */
#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
-/* Function Local Instance (VI) number. */
+/* Function Local Instance (VI) number which has a TxQ allocated to it. */
#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
@@ -16601,6 +18084,7 @@
* Unlink a push I/O buffer from a TxQ
*/
#define MC_CMD_UNLINK_PIOBUF 0x93
+#define MC_CMD_UNLINK_PIOBUF_MSGSET 0x93
#undef MC_CMD_0x93_PRIVILEGE_CTG
#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -16620,6 +18104,7 @@
* allocate and initialise a v-switch.
*/
#define MC_CMD_VSWITCH_ALLOC 0x94
+#define MC_CMD_VSWITCH_ALLOC_MSGSET 0x94
#undef MC_CMD_0x94_PRIVILEGE_CTG
#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16667,6 +18152,7 @@
* de-allocate a v-switch.
*/
#define MC_CMD_VSWITCH_FREE 0x95
+#define MC_CMD_VSWITCH_FREE_MSGSET 0x95
#undef MC_CMD_0x95_PRIVILEGE_CTG
#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16688,6 +18174,7 @@
* not, then the command returns ENOENT).
*/
#define MC_CMD_VSWITCH_QUERY 0x63
+#define MC_CMD_VSWITCH_QUERY_MSGSET 0x63
#undef MC_CMD_0x63_PRIVILEGE_CTG
#define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16707,6 +18194,7 @@
* allocate a v-port.
*/
#define MC_CMD_VPORT_ALLOC 0x96
+#define MC_CMD_VPORT_ALLOC_MSGSET 0x96
#undef MC_CMD_0x96_PRIVILEGE_CTG
#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16774,6 +18262,7 @@
* de-allocate a v-port.
*/
#define MC_CMD_VPORT_FREE 0x97
+#define MC_CMD_VPORT_FREE_MSGSET 0x97
#undef MC_CMD_0x97_PRIVILEGE_CTG
#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16793,6 +18282,7 @@
* allocate a v-adaptor.
*/
#define MC_CMD_VADAPTOR_ALLOC 0x98
+#define MC_CMD_VADAPTOR_ALLOC_MSGSET 0x98
#undef MC_CMD_0x98_PRIVILEGE_CTG
#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16841,6 +18331,7 @@
* de-allocate a v-adaptor.
*/
#define MC_CMD_VADAPTOR_FREE 0x99
+#define MC_CMD_VADAPTOR_FREE_MSGSET 0x99
#undef MC_CMD_0x99_PRIVILEGE_CTG
#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16860,6 +18351,7 @@
* assign a new MAC address to a v-adaptor.
*/
#define MC_CMD_VADAPTOR_SET_MAC 0x5d
+#define MC_CMD_VADAPTOR_SET_MAC_MSGSET 0x5d
#undef MC_CMD_0x5d_PRIVILEGE_CTG
#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16882,6 +18374,7 @@
* read the MAC address assigned to a v-adaptor.
*/
#define MC_CMD_VADAPTOR_GET_MAC 0x5e
+#define MC_CMD_VADAPTOR_GET_MAC_MSGSET 0x5e
#undef MC_CMD_0x5e_PRIVILEGE_CTG
#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16904,6 +18397,7 @@
* read some config of v-adaptor.
*/
#define MC_CMD_VADAPTOR_QUERY 0x61
+#define MC_CMD_VADAPTOR_QUERY_MSGSET 0x61
#undef MC_CMD_0x61_PRIVILEGE_CTG
#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16932,6 +18426,7 @@
* assign a port to a PCI function.
*/
#define MC_CMD_EVB_PORT_ASSIGN 0x9a
+#define MC_CMD_EVB_PORT_ASSIGN_MSGSET 0x9a
#undef MC_CMD_0x9a_PRIVILEGE_CTG
#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16960,6 +18455,7 @@
* Assign the 64 bit region addresses.
*/
#define MC_CMD_RDWR_A64_REGIONS 0x9b
+#define MC_CMD_RDWR_A64_REGIONS_MSGSET 0x9b
#undef MC_CMD_0x9b_PRIVILEGE_CTG
#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -16999,6 +18495,7 @@
* Allocate an Onload stack ID.
*/
#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
+#define MC_CMD_ONLOAD_STACK_ALLOC_MSGSET 0x9c
#undef MC_CMD_0x9c_PRIVILEGE_CTG
#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -17021,6 +18518,7 @@
* Free an Onload stack ID.
*/
#define MC_CMD_ONLOAD_STACK_FREE 0x9d
+#define MC_CMD_ONLOAD_STACK_FREE_MSGSET 0x9d
#undef MC_CMD_0x9d_PRIVILEGE_CTG
#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -17040,6 +18538,7 @@
* Allocate an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
+#define MC_CMD_RSS_CONTEXT_ALLOC_MSGSET 0x9e
#undef MC_CMD_0x9e_PRIVILEGE_CTG
#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17140,6 +18639,7 @@
* Free an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_FREE 0x9f
+#define MC_CMD_RSS_CONTEXT_FREE_MSGSET 0x9f
#undef MC_CMD_0x9f_PRIVILEGE_CTG
#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17159,6 +18659,7 @@
* Set the Toeplitz hash key for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
+#define MC_CMD_RSS_CONTEXT_SET_KEY_MSGSET 0xa0
#undef MC_CMD_0xa0_PRIVILEGE_CTG
#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17181,6 +18682,7 @@
* Get the Toeplitz hash key for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
+#define MC_CMD_RSS_CONTEXT_GET_KEY_MSGSET 0xa1
#undef MC_CMD_0xa1_PRIVILEGE_CTG
#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17205,6 +18707,7 @@
* when the RSS context is allocated without specifying a table size.
*/
#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
+#define MC_CMD_RSS_CONTEXT_SET_TABLE_MSGSET 0xa2
#undef MC_CMD_0xa2_PRIVILEGE_CTG
#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17229,6 +18732,7 @@
* when the RSS context is allocated without specifying a table size.
*/
#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
+#define MC_CMD_RSS_CONTEXT_GET_TABLE_MSGSET 0xa3
#undef MC_CMD_0xa3_PRIVILEGE_CTG
#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17253,6 +18757,7 @@
* RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
*/
#define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e
+#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_MSGSET 0x13e
#undef MC_CMD_0x13e_PRIVILEGE_CTG
#define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17299,6 +18804,7 @@
* RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
*/
#define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f
+#define MC_CMD_RSS_CONTEXT_READ_TABLE_MSGSET 0x13f
#undef MC_CMD_0x13f_PRIVILEGE_CTG
#define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17338,6 +18844,7 @@
* Set various control flags for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
+#define MC_CMD_RSS_CONTEXT_SET_FLAGS_MSGSET 0xe1
#undef MC_CMD_0xe1_PRIVILEGE_CTG
#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17404,6 +18911,7 @@
* Get various control flags for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
+#define MC_CMD_RSS_CONTEXT_GET_FLAGS_MSGSET 0xe2
#undef MC_CMD_0xe2_PRIVILEGE_CTG
#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17471,6 +18979,7 @@
* Allocate a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
+#define MC_CMD_DOT1P_MAPPING_ALLOC_MSGSET 0xa4
#undef MC_CMD_0xa4_PRIVILEGE_CTG
#define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17504,6 +19013,7 @@
* Free a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_FREE 0xa5
+#define MC_CMD_DOT1P_MAPPING_FREE_MSGSET 0xa5
#undef MC_CMD_0xa5_PRIVILEGE_CTG
#define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17523,6 +19033,7 @@
* Set the mapping table for a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
+#define MC_CMD_DOT1P_MAPPING_SET_TABLE_MSGSET 0xa6
#undef MC_CMD_0xa6_PRIVILEGE_CTG
#define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17547,6 +19058,7 @@
* Get the mapping table for a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
+#define MC_CMD_DOT1P_MAPPING_GET_TABLE_MSGSET 0xa7
#undef MC_CMD_0xa7_PRIVILEGE_CTG
#define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17571,6 +19083,7 @@
* Get Interrupt Vector config for this PF.
*/
#define MC_CMD_GET_VECTOR_CFG 0xbf
+#define MC_CMD_GET_VECTOR_CFG_MSGSET 0xbf
#undef MC_CMD_0xbf_PRIVILEGE_CTG
#define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17596,6 +19109,7 @@
* Set Interrupt Vector config for this PF.
*/
#define MC_CMD_SET_VECTOR_CFG 0xc0
+#define MC_CMD_SET_VECTOR_CFG_MSGSET 0xc0
#undef MC_CMD_0xc0_PRIVILEGE_CTG
#define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17623,6 +19137,7 @@
* Add a MAC address to a v-port
*/
#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
+#define MC_CMD_VPORT_ADD_MAC_ADDRESS_MSGSET 0xa8
#undef MC_CMD_0xa8_PRIVILEGE_CTG
#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17645,6 +19160,7 @@
* Delete a MAC address from a v-port
*/
#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
+#define MC_CMD_VPORT_DEL_MAC_ADDRESS_MSGSET 0xa9
#undef MC_CMD_0xa9_PRIVILEGE_CTG
#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17667,6 +19183,7 @@
* Delete a MAC address from a v-port
*/
#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
+#define MC_CMD_VPORT_GET_MAC_ADDRESSES_MSGSET 0xaa
#undef MC_CMD_0xaa_PRIVILEGE_CTG
#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17701,6 +19218,7 @@
* function will be reset before applying the changes.
*/
#define MC_CMD_VPORT_RECONFIGURE 0xeb
+#define MC_CMD_VPORT_RECONFIGURE_MSGSET 0xeb
#undef MC_CMD_0xeb_PRIVILEGE_CTG
#define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17756,6 +19274,7 @@
* read some config of v-port.
*/
#define MC_CMD_EVB_PORT_QUERY 0x62
+#define MC_CMD_EVB_PORT_QUERY_MSGSET 0x62
#undef MC_CMD_0x62_PRIVILEGE_CTG
#define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17786,6 +19305,7 @@
* lifted in future.
*/
#define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
+#define MC_CMD_DUMP_BUFTBL_ENTRIES_MSGSET 0xab
#undef MC_CMD_0xab_PRIVILEGE_CTG
#define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -17818,6 +19338,7 @@
* Set global RXDP configuration settings
*/
#define MC_CMD_SET_RXDP_CONFIG 0xc1
+#define MC_CMD_SET_RXDP_CONFIG_MSGSET 0xc1
#undef MC_CMD_0xc1_PRIVILEGE_CTG
#define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17848,6 +19369,7 @@
* Get global RXDP configuration settings
*/
#define MC_CMD_GET_RXDP_CONFIG 0xc2
+#define MC_CMD_GET_RXDP_CONFIG_MSGSET 0xc2
#undef MC_CMD_0xc2_PRIVILEGE_CTG
#define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17874,6 +19396,7 @@
* Return the system and PDCPU clock frequencies.
*/
#define MC_CMD_GET_CLOCK 0xac
+#define MC_CMD_GET_CLOCK_MSGSET 0xac
#undef MC_CMD_0xac_PRIVILEGE_CTG
#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17896,6 +19419,7 @@
* Control the system and DPCPU clock frequencies. Changes are lost reboot.
*/
#define MC_CMD_SET_CLOCK 0xad
+#define MC_CMD_SET_CLOCK_MSGSET 0xad
#undef MC_CMD_0xad_PRIVILEGE_CTG
#define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -17982,6 +19506,7 @@
* Send an arbitrary DPCPU message.
*/
#define MC_CMD_DPCPU_RPC 0xae
+#define MC_CMD_DPCPU_RPC_MSGSET 0xae
#undef MC_CMD_0xae_PRIVILEGE_CTG
#define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18100,6 +19625,7 @@
* Trigger an interrupt by prodding the BIU.
*/
#define MC_CMD_TRIGGER_INTERRUPT 0xe3
+#define MC_CMD_TRIGGER_INTERRUPT_MSGSET 0xe3
#undef MC_CMD_0xe3_PRIVILEGE_CTG
#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18119,6 +19645,7 @@
* Special operations to support (for now) shmboot.
*/
#define MC_CMD_SHMBOOT_OP 0xe6
+#define MC_CMD_SHMBOOT_OP_MSGSET 0xe6
#undef MC_CMD_0xe6_PRIVILEGE_CTG
#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -18140,6 +19667,7 @@
* Read multiple 64bit words from capture block memory
*/
#define MC_CMD_CAP_BLK_READ 0xe7
+#define MC_CMD_CAP_BLK_READ_MSGSET 0xe7
#undef MC_CMD_0xe7_PRIVILEGE_CTG
#define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18162,7 +19690,13 @@
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LEN 4
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LBN 0
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_WIDTH 32
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LEN 4
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LBN 32
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_WIDTH 32
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM_MCDI2 127
@@ -18173,6 +19707,7 @@
* Take a dump of the DUT state
*/
#define MC_CMD_DUMP_DO 0xe8
+#define MC_CMD_DUMP_DO_MSGSET 0xe8
#undef MC_CMD_0xe8_PRIVILEGE_CTG
#define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18253,6 +19788,7 @@
* Configure unsolicited dumps
*/
#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
+#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_MSGSET 0xe9
#undef MC_CMD_0xe9_PRIVILEGE_CTG
#define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18322,6 +19858,7 @@
* the parameter is out of range.
*/
#define MC_CMD_SET_PSU 0xea
+#define MC_CMD_SET_PSU_MSGSET 0xea
#undef MC_CMD_0xea_PRIVILEGE_CTG
#define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18348,6 +19885,7 @@
* Get function information. PF and VF number.
*/
#define MC_CMD_GET_FUNCTION_INFO 0xec
+#define MC_CMD_GET_FUNCTION_INFO_MSGSET 0xec
#undef MC_CMD_0xec_PRIVILEGE_CTG
#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18370,6 +19908,7 @@
* reboot.
*/
#define MC_CMD_ENABLE_OFFLINE_BIST 0xed
+#define MC_CMD_ENABLE_OFFLINE_BIST_MSGSET 0xed
#undef MC_CMD_0xed_PRIVILEGE_CTG
#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -18388,6 +19927,7 @@
* forget.
*/
#define MC_CMD_UART_SEND_DATA 0xee
+#define MC_CMD_UART_SEND_DATA_MSGSET 0xee
#undef MC_CMD_0xee_PRIVILEGE_CTG
#define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18426,6 +19966,7 @@
* subject to change and not currently implemented.
*/
#define MC_CMD_UART_RECV_DATA 0xef
+#define MC_CMD_UART_RECV_DATA_MSGSET 0xef
#undef MC_CMD_0xef_PRIVILEGE_CTG
#define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18475,6 +20016,7 @@
* Read data programmed into the device One-Time-Programmable (OTP) Fuses
*/
#define MC_CMD_READ_FUSES 0xf0
+#define MC_CMD_READ_FUSES_MSGSET 0xf0
#undef MC_CMD_0xf0_PRIVILEGE_CTG
#define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18510,6 +20052,7 @@
* Get or set KR Serdes RXEQ and TX Driver settings
*/
#define MC_CMD_KR_TUNE 0xf1
+#define MC_CMD_KR_TUNE_MSGSET 0xf1
#undef MC_CMD_0xf1_PRIVILEGE_CTG
#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -19066,6 +20609,7 @@
* Get or set PCIE Serdes RXEQ and TX Driver settings
*/
#define MC_CMD_PCIE_TUNE 0xf2
+#define MC_CMD_PCIE_TUNE_MSGSET 0xf2
#undef MC_CMD_0xf2_PRIVILEGE_CTG
#define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -19323,6 +20867,7 @@
* - not used for V3 licensing
*/
#define MC_CMD_LICENSING 0xf3
+#define MC_CMD_LICENSING_MSGSET 0xf3
#undef MC_CMD_0xf3_PRIVILEGE_CTG
#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19379,6 +20924,7 @@
* - V3 licensing (Medford)
*/
#define MC_CMD_LICENSING_V3 0xd0
+#define MC_CMD_LICENSING_V3_MSGSET 0xd0
#undef MC_CMD_0xd0_PRIVILEGE_CTG
#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19429,7 +20975,13 @@
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LBN 192
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_WIDTH 32
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LBN 224
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_WIDTH 32
/* reserved for future use */
#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
@@ -19437,7 +20989,13 @@
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LBN 448
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_WIDTH 32
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LBN 480
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_WIDTH 32
/* reserved for future use */
#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
@@ -19449,6 +21007,7 @@
* partition - V3 licensing (Medford)
*/
#define MC_CMD_LICENSING_GET_ID_V3 0xd1
+#define MC_CMD_LICENSING_GET_ID_V3_MSGSET 0xd1
#undef MC_CMD_0xd1_PRIVILEGE_CTG
#define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19482,6 +21041,7 @@
* This will fail on a single-core system.
*/
#define MC_CMD_MC2MC_PROXY 0xf4
+#define MC_CMD_MC2MC_PROXY_MSGSET 0xf4
#undef MC_CMD_0xf4_PRIVILEGE_CTG
#define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19500,6 +21060,7 @@
* or a reboot of the MC.) Not used for V3 licensing
*/
#define MC_CMD_GET_LICENSED_APP_STATE 0xf5
+#define MC_CMD_GET_LICENSED_APP_STATE_MSGSET 0xf5
#undef MC_CMD_0xf5_PRIVILEGE_CTG
#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19528,6 +21089,7 @@
* operation or a reboot of the MC.) Used for V3 licensing (Medford)
*/
#define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_MSGSET 0xd2
#undef MC_CMD_0xd2_PRIVILEGE_CTG
#define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19540,7 +21102,13 @@
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LEN 4
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LBN 0
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_WIDTH 32
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LEN 4
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LBN 32
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_WIDTH 32
/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */
#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
@@ -19560,6 +21128,7 @@
* operation or a reboot of the MC.) Used for V3 licensing (Medford)
*/
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_MSGSET 0xd3
#undef MC_CMD_0xd3_PRIVILEGE_CTG
#define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19572,7 +21141,13 @@
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LBN 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_WIDTH 32
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LBN 32
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_WIDTH 32
/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8
@@ -19580,7 +21155,13 @@
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LBN 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_WIDTH 32
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LBN 32
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_WIDTH 32
/***********************************/
@@ -19589,6 +21170,7 @@
* licensing.
*/
#define MC_CMD_LICENSED_APP_OP 0xf6
+#define MC_CMD_LICENSED_APP_OP_MSGSET 0xf6
#undef MC_CMD_0xf6_PRIVILEGE_CTG
#define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19672,6 +21254,7 @@
* (Medford)
*/
#define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_MSGSET 0xd4
#undef MC_CMD_0xd4_PRIVILEGE_CTG
#define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19685,7 +21268,13 @@
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LEN 4
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LBN 384
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_WIDTH 32
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LEN 4
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LBN 416
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_WIDTH 32
/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */
#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116
@@ -19725,6 +21314,7 @@
* Mask features - V3 licensing (Medford)
*/
#define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_MSGSET 0xd5
#undef MC_CMD_0xd5_PRIVILEGE_CTG
#define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -19735,7 +21325,13 @@
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LEN 4
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LBN 0
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_WIDTH 32
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LEN 4
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LBN 32
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_WIDTH 32
/* whether to turn on or turn off the masked features */
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
@@ -19757,6 +21353,7 @@
* erased when the adapter is power cycled
*/
#define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
+#define MC_CMD_LICENSING_V3_TEMPORARY_MSGSET 0xd6
#undef MC_CMD_0xd6_PRIVILEGE_CTG
#define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -19815,7 +21412,13 @@
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LEN 4
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LBN 32
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_WIDTH 32
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LEN 4
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LBN 64
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_WIDTH 32
/***********************************/
@@ -19827,6 +21430,7 @@
* delivered to a specific queue, or a set of queues with RSS.
*/
#define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
+#define MC_CMD_SET_PORT_SNIFF_CONFIG_MSGSET 0xf7
#undef MC_CMD_0xf7_PRIVILEGE_CTG
#define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -19870,6 +21474,7 @@
* the configuration.
*/
#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
+#define MC_CMD_GET_PORT_SNIFF_CONFIG_MSGSET 0xf8
#undef MC_CMD_0xf8_PRIVILEGE_CTG
#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19908,6 +21513,7 @@
* Change configuration related to the parser-dispatcher subsystem.
*/
#define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
+#define MC_CMD_SET_PARSER_DISP_CONFIG_MSGSET 0xf9
#undef MC_CMD_0xf9_PRIVILEGE_CTG
#define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19953,6 +21559,7 @@
* Read configuration related to the parser-dispatcher subsystem.
*/
#define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
+#define MC_CMD_GET_PARSER_DISP_CONFIG_MSGSET 0xfa
#undef MC_CMD_0xfa_PRIVILEGE_CTG
#define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19997,6 +21604,7 @@
* dedicated as TX sniff receivers.
*/
#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
+#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_MSGSET 0xfb
#undef MC_CMD_0xfb_PRIVILEGE_CTG
#define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20037,6 +21645,7 @@
* the configuration.
*/
#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
+#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_MSGSET 0xfc
#undef MC_CMD_0xfc_PRIVILEGE_CTG
#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20072,6 +21681,7 @@
* Per queue rx error stats.
*/
#define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
+#define MC_CMD_RMON_STATS_RX_ERRORS_MSGSET 0xfe
#undef MC_CMD_0xfe_PRIVILEGE_CTG
#define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20104,6 +21714,7 @@
* Find out about available PCIE resources
*/
#define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
+#define MC_CMD_GET_PCIE_RESOURCE_INFO_MSGSET 0xfd
#undef MC_CMD_0xfd_PRIVILEGE_CTG
#define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20143,6 +21754,7 @@
* Find out about available port modes
*/
#define MC_CMD_GET_PORT_MODES 0xff
+#define MC_CMD_GET_PORT_MODES_MSGSET 0xff
#undef MC_CMD_0xff_PRIVILEGE_CTG
#define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20199,6 +21811,7 @@
* the new port mode, as the override does not affect PF configuration.
*/
#define MC_CMD_OVERRIDE_PORT_MODE 0x137
+#define MC_CMD_OVERRIDE_PORT_MODE_MSGSET 0x137
#undef MC_CMD_0x137_PRIVILEGE_CTG
#define MC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20223,6 +21836,7 @@
* Sample voltages on the ATB
*/
#define MC_CMD_READ_ATB 0x100
+#define MC_CMD_READ_ATB_MSGSET 0x100
#undef MC_CMD_0x100_PRIVILEGE_CTG
#define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20253,6 +21867,7 @@
* enums here must correspond with those in MC_CMD_WORKAROUND.
*/
#define MC_CMD_GET_WORKAROUNDS 0x59
+#define MC_CMD_GET_WORKAROUNDS_MSGSET 0x59
#undef MC_CMD_0x59_PRIVILEGE_CTG
#define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20290,6 +21905,7 @@
* Read/set privileges of an arbitrary PCIe function
*/
#define MC_CMD_PRIVILEGE_MASK 0x5a
+#define MC_CMD_PRIVILEGE_MASK_MSGSET 0x5a
#undef MC_CMD_0x5a_PRIVILEGE_CTG
#define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20351,6 +21967,20 @@
#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
/* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */
#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000
+/* enum: This Function/client may call MC_CMD_CLIENT_ALLOC to create new
+ * dynamic client children of itself.
+ */
+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALLOC_CLIENT 0x20000
+/* enum: A dynamic client with this privilege may perform all the same DMA
+ * operations as the function client from which it is descended.
+ */
+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_FUNC_DMA 0x40000
+/* enum: A client with this privilege may perform DMA as any PCIe function on
+ * the device and to on-device DDR. It allows clients to use TX-DESC2CMPT-DESC
+ * descriptors, and to use TX-SEG-DESC and TX-MEM2MEM-DESC with an address
+ * space override (i.e. with the ADDR_SPC_EN bit set).
+ */
+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ARBITRARY_DMA 0x80000
/* enum: Set this bit to indicate that a new privilege mask is to be set,
* otherwise the command will only read the existing mask.
*/
@@ -20368,6 +21998,7 @@
* Read/set link state mode of a VF
*/
#define MC_CMD_LINK_STATE_MODE 0x5c
+#define MC_CMD_LINK_STATE_MODE_MSGSET 0x5c
#undef MC_CMD_0x5c_PRIVILEGE_CTG
#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20407,6 +22038,7 @@
* parameter to MC_CMD_INIT_RXQ.
*/
#define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
+#define MC_CMD_GET_SNAPSHOT_LENGTH_MSGSET 0x101
#undef MC_CMD_0x101_PRIVILEGE_CTG
#define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20429,6 +22061,7 @@
* Additional fuse diagnostics
*/
#define MC_CMD_FUSE_DIAGS 0x102
+#define MC_CMD_FUSE_DIAGS_MSGSET 0x102
#undef MC_CMD_0x102_PRIVILEGE_CTG
#define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20483,6 +22116,7 @@
* included in one of the masks provided.
*/
#define MC_CMD_PRIVILEGE_MODIFY 0x60
+#define MC_CMD_PRIVILEGE_MODIFY_MSGSET 0x60
#undef MC_CMD_0x60_PRIVILEGE_CTG
#define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20527,6 +22161,7 @@
* Read XPM memory
*/
#define MC_CMD_XPM_READ_BYTES 0x103
+#define MC_CMD_XPM_READ_BYTES_MSGSET 0x103
#undef MC_CMD_0x103_PRIVILEGE_CTG
#define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20559,6 +22194,7 @@
* Write XPM memory
*/
#define MC_CMD_XPM_WRITE_BYTES 0x104
+#define MC_CMD_XPM_WRITE_BYTES_MSGSET 0x104
#undef MC_CMD_0x104_PRIVILEGE_CTG
#define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20591,6 +22227,7 @@
* Read XPM sector
*/
#define MC_CMD_XPM_READ_SECTOR 0x105
+#define MC_CMD_XPM_READ_SECTOR_MSGSET 0x105
#undef MC_CMD_0x105_PRIVILEGE_CTG
#define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20631,6 +22268,7 @@
* Write XPM sector
*/
#define MC_CMD_XPM_WRITE_SECTOR 0x106
+#define MC_CMD_XPM_WRITE_SECTOR_MSGSET 0x106
#undef MC_CMD_0x106_PRIVILEGE_CTG
#define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20677,6 +22315,7 @@
* Invalidate XPM sector
*/
#define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
+#define MC_CMD_XPM_INVALIDATE_SECTOR_MSGSET 0x107
#undef MC_CMD_0x107_PRIVILEGE_CTG
#define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20696,6 +22335,7 @@
* Blank-check XPM memory and report bad locations
*/
#define MC_CMD_XPM_BLANK_CHECK 0x108
+#define MC_CMD_XPM_BLANK_CHECK_MSGSET 0x108
#undef MC_CMD_0x108_PRIVILEGE_CTG
#define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20733,6 +22373,7 @@
* Blank-check and repair XPM memory
*/
#define MC_CMD_XPM_REPAIR 0x109
+#define MC_CMD_XPM_REPAIR_MSGSET 0x109
#undef MC_CMD_0x109_PRIVILEGE_CTG
#define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20756,6 +22397,7 @@
* be performed on an unprogrammed part.
*/
#define MC_CMD_XPM_DECODER_TEST 0x10a
+#define MC_CMD_XPM_DECODER_TEST_MSGSET 0x10a
#undef MC_CMD_0x10a_PRIVILEGE_CTG
#define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20776,6 +22418,7 @@
* first available location to use, or fail with ENOSPC if none left.
*/
#define MC_CMD_XPM_WRITE_TEST 0x10b
+#define MC_CMD_XPM_WRITE_TEST_MSGSET 0x10b
#undef MC_CMD_0x10b_PRIVILEGE_CTG
#define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20797,6 +22440,7 @@
* does match, otherwise it will respond with success before it jumps to IMEM.
*/
#define MC_CMD_EXEC_SIGNED 0x10c
+#define MC_CMD_EXEC_SIGNED_MSGSET 0x10c
#undef MC_CMD_0x10c_PRIVILEGE_CTG
#define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -20827,6 +22471,7 @@
* MC_CMD_EXEC_SIGNED.
*/
#define MC_CMD_PREPARE_SIGNED 0x10d
+#define MC_CMD_PREPARE_SIGNED_MSGSET 0x10d
#undef MC_CMD_0x10d_PRIVILEGE_CTG
#define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -20850,6 +22495,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_SET_SECURITY_RULE 0x10f
+#define MC_CMD_SET_SECURITY_RULE_MSGSET 0x10f
#undef MC_CMD_0x10f_PRIVILEGE_CTG
#define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21040,6 +22686,7 @@
* development. This note will be removed once it is regarded as stable.
*/
#define MC_CMD_RESET_SECURITY_RULES 0x110
+#define MC_CMD_RESET_SECURITY_RULES_MSGSET 0x110
#undef MC_CMD_0x110_PRIVILEGE_CTG
#define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21066,6 +22713,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111
+#define MC_CMD_GET_SECURITY_RULESET_VERSION_MSGSET 0x111
#undef MC_CMD_0x111_PRIVILEGE_CTG
#define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -21096,6 +22744,7 @@
* removed once it is regarded as stable.
*/
#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112
+#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_MSGSET 0x112
#undef MC_CMD_0x112_PRIVILEGE_CTG
#define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21134,6 +22783,7 @@
* removed once it is regarded as stable.
*/
#define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113
+#define MC_CMD_SECURITY_RULE_COUNTER_FREE_MSGSET 0x113
#undef MC_CMD_0x113_PRIVILEGE_CTG
#define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21169,6 +22819,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_SUBNET_MAP_SET_NODE 0x114
+#define MC_CMD_SUBNET_MAP_SET_NODE_MSGSET 0x114
#undef MC_CMD_0x114_PRIVILEGE_CTG
#define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21224,6 +22875,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115
+#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_MSGSET 0x115
#undef MC_CMD_0x115_PRIVILEGE_CTG
#define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21258,6 +22910,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116
+#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_MSGSET 0x116
#undef MC_CMD_0x116_PRIVILEGE_CTG
#define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21311,6 +22964,7 @@
* cause all functions to see a reset. (Available on Medford only.)
*/
#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
+#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_MSGSET 0x117
#undef MC_CMD_0x117_PRIVILEGE_CTG
#define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -21357,6 +23011,7 @@
* priority.
*/
#define MC_CMD_RX_BALANCING 0x118
+#define MC_CMD_RX_BALANCING_MSGSET 0x118
#undef MC_CMD_0x118_PRIVILEGE_CTG
#define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21386,6 +23041,7 @@
* info in respect to the binding protocol.
*/
#define MC_CMD_TSA_BIND 0x119
+#define MC_CMD_TSA_BIND_MSGSET 0x119
#undef MC_CMD_0x119_PRIVILEGE_CTG
#define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -21951,6 +23607,7 @@
* OP_GET_CACHED_VERSION. All other sub-operations are prohibited.
*/
#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a
+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_MSGSET 0x11a
#undef MC_CMD_0x11a_PRIVILEGE_CTG
#define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22007,6 +23664,7 @@
* if the tag is already present.
*/
#define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
+#define MC_CMD_NVRAM_PRIVATE_APPEND_MSGSET 0x11c
#undef MC_CMD_0x11c_PRIVILEGE_CTG
#define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22041,6 +23699,7 @@
* correctly at ATE.
*/
#define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
+#define MC_CMD_XPM_VERIFY_CONTENTS_MSGSET 0x11b
#undef MC_CMD_0x11b_PRIVILEGE_CTG
#define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22084,6 +23743,7 @@
* and TMR_RELOAD_ACT_NS).
*/
#define MC_CMD_SET_EVQ_TMR 0x120
+#define MC_CMD_SET_EVQ_TMR_MSGSET 0x120
#undef MC_CMD_0x120_PRIVILEGE_CTG
#define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22122,6 +23782,7 @@
* Query properties about the event queue timers.
*/
#define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
+#define MC_CMD_GET_EVQ_TMR_PROPERTIES_MSGSET 0x122
#undef MC_CMD_0x122_PRIVILEGE_CTG
#define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22191,6 +23852,7 @@
* non used switch buffers.
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_MSGSET 0x11d
#undef MC_CMD_0x11d_PRIVILEGE_CTG
#define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22198,7 +23860,8 @@
/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
@@ -22243,6 +23906,7 @@
* previously allocated common pools.
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_MSGSET 0x11e
#undef MC_CMD_0x11e_PRIVILEGE_CTG
#define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22296,6 +23960,7 @@
* ready to be re-used.
*/
#define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
+#define MC_CMD_TEARDOWN_TX_VFIFO_VF_MSGSET 0x11f
#undef MC_CMD_0x11f_PRIVILEGE_CTG
#define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22316,6 +23981,7 @@
* it ready to be re-used.
*/
#define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
+#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_MSGSET 0x121
#undef MC_CMD_0x121_PRIVILEGE_CTG
#define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22344,6 +24010,7 @@
* or 0 if there has not been a previous rekey.
*/
#define MC_CMD_REKEY 0x123
+#define MC_CMD_REKEY_MSGSET 0x123
#undef MC_CMD_0x123_PRIVILEGE_CTG
#define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22368,6 +24035,7 @@
* not yet assigned.
*/
#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
+#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_MSGSET 0x124
#undef MC_CMD_0x124_PRIVILEGE_CTG
#define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22396,6 +24064,7 @@
* the required bits were not set.
*/
#define MC_CMD_SET_SECURITY_FUSES 0x126
+#define MC_CMD_SET_SECURITY_FUSES_MSGSET 0x126
#undef MC_CMD_0x126_PRIVILEGE_CTG
#define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22438,6 +24107,7 @@
* SF-117371-SW
*/
#define MC_CMD_TSA_INFO 0x127
+#define MC_CMD_TSA_INFO_MSGSET 0x127
#undef MC_CMD_0x127_PRIVILEGE_CTG
#define MC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22614,6 +24284,7 @@
* Doxbox reference SF-117371-SW
*/
#define MC_CMD_HOST_INFO 0x128
+#define MC_CMD_HOST_INFO_MSGSET 0x128
#undef MC_CMD_0x128_PRIVILEGE_CTG
#define MC_CMD_0x128_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22681,6 +24352,7 @@
* section 'Adapter Information'
*/
#define MC_CMD_TSAN_INFO 0x129
+#define MC_CMD_TSAN_INFO_MSGSET 0x129
#undef MC_CMD_0x129_PRIVILEGE_CTG
#define MC_CMD_0x129_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22780,6 +24452,7 @@
* TSA adapter statistics operations.
*/
#define MC_CMD_TSA_STATISTICS 0x130
+#define MC_CMD_TSA_STATISTICS_MSGSET 0x130
#undef MC_CMD_0x130_PRIVILEGE_CTG
#define MC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22884,14 +24557,26 @@
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LEN 8
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_LBN 0
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_OFST 4
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_LBN 32
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_WIDTH 64
/* Rx statistics counter */
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_OFST 8
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LEN 8
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_OFST 8
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_LBN 64
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_OFST 12
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_LBN 96
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64
@@ -22904,6 +24589,7 @@
* installing TSA binding certificates. See SF-117631-TC.
*/
#define MC_CMD_ERASE_INITIAL_NIC_SECRET 0x131
+#define MC_CMD_ERASE_INITIAL_NIC_SECRET_MSGSET 0x131
#undef MC_CMD_0x131_PRIVILEGE_CTG
#define MC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22921,6 +24607,7 @@
* NIC for TSA binding.
*/
#define MC_CMD_TSA_CONFIG 0x64
+#define MC_CMD_TSA_CONFIG_MSGSET 0x64
#undef MC_CMD_0x64_PRIVILEGE_CTG
#define MC_CMD_0x64_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23038,6 +24725,7 @@
* to a TSA adapter.
*/
#define MC_CMD_TSA_IPADDR 0x65
+#define MC_CMD_TSA_IPADDR_MSGSET 0x65
#undef MC_CMD_0x65_PRIVILEGE_CTG
#define MC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23089,7 +24777,13 @@
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_OFST 8
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LEN 8
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_OFST 8
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_LBN 64
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_OFST 12
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_LBN 96
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MINNUM 1
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM 30
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM_MCDI2 126
@@ -23119,7 +24813,13 @@
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_OFST 8
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LEN 8
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_OFST 8
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_LBN 64
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_OFST 12
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_LBN 96
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MINNUM 1
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM 30
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM_MCDI2 126
@@ -23135,6 +24835,7 @@
* disabled.
*/
#define MC_CMD_SECURE_NIC_INFO 0x132
+#define MC_CMD_SECURE_NIC_INFO_MSGSET 0x132
#undef MC_CMD_0x132_PRIVILEGE_CTG
#define MC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23228,6 +24929,7 @@
* parameters in request or response.
*/
#define MC_CMD_TSA_TEST 0x125
+#define MC_CMD_TSA_TEST_MSGSET 0x125
#undef MC_CMD_0x125_PRIVILEGE_CTG
#define MC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23249,6 +24951,7 @@
* rule-set transitions.
*/
#define MC_CMD_TSA_RULESET_OVERRIDE 0x12a
+#define MC_CMD_TSA_RULESET_OVERRIDE_MSGSET 0x12a
#undef MC_CMD_0x12a_PRIVILEGE_CTG
#define MC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23281,6 +24984,7 @@
* Specific usage is determined by the TYPE field.
*/
#define MC_CMD_TSAC_REQUEST 0x12b
+#define MC_CMD_TSAC_REQUEST_MSGSET 0x12b
#undef MC_CMD_0x12b_PRIVILEGE_CTG
#define MC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23305,6 +25009,7 @@
* Get the version of the SUC
*/
#define MC_CMD_SUC_VERSION 0x134
+#define MC_CMD_SUC_VERSION_MSGSET 0x134
#undef MC_CMD_0x134_PRIVILEGE_CTG
#define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23350,6 +25055,7 @@
* Operations to support manftest on SUC based systems.
*/
#define MC_CMD_SUC_MANFTEST 0x135
+#define MC_CMD_SUC_MANFTEST_MSGSET 0x135
#undef MC_CMD_0x135_PRIVILEGE_CTG
#define MC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23546,6 +25252,7 @@
* Request a certificate.
*/
#define MC_CMD_GET_CERTIFICATE 0x12c
+#define MC_CMD_GET_CERTIFICATE_MSGSET 0x12c
#undef MC_CMD_0x12c_PRIVILEGE_CTG
#define MC_CMD_0x12c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23620,6 +25327,7 @@
* Get a global value which applies to all PCI functions
*/
#define MC_CMD_GET_NIC_GLOBAL 0x12d
+#define MC_CMD_GET_NIC_GLOBAL_MSGSET 0x12d
#undef MC_CMD_0x12d_PRIVILEGE_CTG
#define MC_CMD_0x12d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23647,6 +25355,7 @@
* appropriate error otherwise (see key descriptions).
*/
#define MC_CMD_SET_NIC_GLOBAL 0x12e
+#define MC_CMD_SET_NIC_GLOBAL_MSGSET 0x12e
#undef MC_CMD_0x12e_PRIVILEGE_CTG
#define MC_CMD_0x12e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23694,6 +25403,7 @@
* firmware buffer for later extraction.
*/
#define MC_CMD_LTSSM_TRACE_POLL 0x12f
+#define MC_CMD_LTSSM_TRACE_POLL_MSGSET 0x12f
#undef MC_CMD_0x12f_PRIVILEGE_CTG
#define MC_CMD_0x12f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23731,7 +25441,13 @@
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_OFST 8
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LEN 8
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_OFST 8
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_LEN 4
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_LBN 64
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_WIDTH 32
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_OFST 12
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_LEN 4
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_LBN 96
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_WIDTH 32
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MINNUM 0
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM 30
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM_MCDI2 126
@@ -23765,6 +25481,7 @@
* firmware variant.
*/
#define MC_CMD_TELEMETRY_ENABLE 0x138
+#define MC_CMD_TELEMETRY_ENABLE_MSGSET 0x138
#undef MC_CMD_0x138_PRIVILEGE_CTG
#define MC_CMD_0x138_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23856,6 +25573,7 @@
* Reference - SF-120569-SW Telemetry Firmware Design.
*/
#define MC_CMD_TELEMETRY_CONFIG 0x139
+#define MC_CMD_TELEMETRY_CONFIG_MSGSET 0x139
#undef MC_CMD_0x139_PRIVILEGE_CTG
#define MC_CMD_0x139_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23925,6 +25643,7 @@
* due to resource constraints, returns ENOSPC.
*/
#define MC_CMD_GET_RX_PREFIX_ID 0x13b
+#define MC_CMD_GET_RX_PREFIX_ID_MSGSET 0x13b
#undef MC_CMD_0x13b_PRIVILEGE_CTG
#define MC_CMD_0x13b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23935,7 +25654,13 @@
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LEN 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LBN 0
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_WIDTH 32
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LEN 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LBN 32
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_WIDTH 32
#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0
#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0
#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1
@@ -24056,6 +25781,7 @@
* created with that prefix id
*/
#define MC_CMD_QUERY_RX_PREFIX_ID 0x13c
+#define MC_CMD_QUERY_RX_PREFIX_ID_MSGSET 0x13c
#undef MC_CMD_0x13c_PRIVILEGE_CTG
#define MC_CMD_0x13c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24092,6 +25818,7 @@
* A command to perform various bundle-related operations on insecure cards.
*/
#define MC_CMD_BUNDLE 0x13d
+#define MC_CMD_BUNDLE_MSGSET 0x13d
#undef MC_CMD_0x13d_PRIVILEGE_CTG
#define MC_CMD_0x13d_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -24154,6 +25881,7 @@
* Read all VPD starting from a given address
*/
#define MC_CMD_GET_VPD 0x165
+#define MC_CMD_GET_VPD_MSGSET 0x165
#undef MC_CMD_0x165_PRIVILEGE_CTG
#define MC_CMD_0x165_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24185,6 +25913,7 @@
* Provide information about the NC-SI stack
*/
#define MC_CMD_GET_NCSI_INFO 0x167
+#define MC_CMD_GET_NCSI_INFO_MSGSET 0x167
#undef MC_CMD_0x167_PRIVILEGE_CTG
#define MC_CMD_0x167_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24256,6 +25985,7 @@
* System lockdown, when enabled firmware updates are blocked.
*/
#define MC_CMD_FIRMWARE_SET_LOCKDOWN 0x16f
+#define MC_CMD_FIRMWARE_SET_LOCKDOWN_MSGSET 0x16f
#undef MC_CMD_0x16f_PRIVILEGE_CTG
#define MC_CMD_0x16f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -24278,6 +26008,7 @@
* documentation.
*/
#define MC_CMD_GET_TEST_FEATURES 0x1ac
+#define MC_CMD_GET_TEST_FEATURES_MSGSET 0x1ac
#undef MC_CMD_0x1ac_PRIVILEGE_CTG
#define MC_CMD_0x1ac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24300,6 +26031,253 @@
#define MC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM 63
#define MC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM_MCDI2 255
+
+/***********************************/
+/* MC_CMD_FPGA
+ * A command to perform various fpga-related operations on platforms that
+ * include FPGAs. Note that some platforms may only support a subset of these
+ * operations.
+ */
+#define MC_CMD_FPGA 0x1bf
+#define MC_CMD_FPGA_MSGSET 0x1bf
+#undef MC_CMD_0x1bf_PRIVILEGE_CTG
+
+#define MC_CMD_0x1bf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FPGA_IN msgrequest */
+#define MC_CMD_FPGA_IN_LEN 4
+/* Sub-command code */
+#define MC_CMD_FPGA_IN_OP_OFST 0
+#define MC_CMD_FPGA_IN_OP_LEN 4
+/* enum: Get the FPGA version string. */
+#define MC_CMD_FPGA_IN_OP_GET_VERSION 0x0
+/* enum: Read bitmask of features supported in the FPGA image. */
+#define MC_CMD_FPGA_IN_OP_GET_CAPABILITIES 0x1
+/* enum: Perform a FPGA reset. */
+#define MC_CMD_FPGA_IN_OP_RESET 0x2
+/* enum: Set active flash device. */
+#define MC_CMD_FPGA_IN_OP_SELECT_FLASH 0x3
+/* enum: Get active flash device. */
+#define MC_CMD_FPGA_IN_OP_GET_ACTIVE_FLASH 0x4
+/* enum: Configure internal link i.e. the FPGA port facing the ASIC. */
+#define MC_CMD_FPGA_IN_OP_SET_INTERNAL_LINK 0x5
+/* enum: Read internal link configuration. */
+#define MC_CMD_FPGA_IN_OP_GET_INTERNAL_LINK 0x6
+
+/* MC_CMD_FPGA_OP_GET_VERSION_IN msgrequest: Get the FPGA version string. A
+ * free-format string is returned in response to this command. Any checks on
+ * supported FPGA operations are based on the response to
+ * MC_CMD_FPGA_OP_GET_CAPABILITIES.
+ */
+#define MC_CMD_FPGA_OP_GET_VERSION_IN_LEN 4
+/* Sub-command code. Must be OP_GET_VERSION */
+#define MC_CMD_FPGA_OP_GET_VERSION_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_VERSION_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_VERSION_OUT msgresponse: Returns the version string. */
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LENMIN 0
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LENMAX 252
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LEN(num) (0+1*(num))
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_NUM(len) (((len)-0)/1)
+/* Null-terminated string containing version information. */
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_OFST 0
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_LEN 1
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MINNUM 0
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MAXNUM 252
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MAXNUM_MCDI2 1020
+
+/* MC_CMD_FPGA_OP_GET_CAPABILITIES_IN msgrequest: Read bitmask of features
+ * supported in the FPGA image.
+ */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_IN_LEN 4
+/* Sub-command code. Must be OP_GET_CAPABILITIES */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT msgresponse: Returns the version string.
+ */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_LEN 4
+/* Bit-mask of supported features. */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_CAPABILITIES_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_CAPABILITIES_LEN 4
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_LBN 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_WIDTH 1
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_LBN 1
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_WIDTH 1
+
+/* MC_CMD_FPGA_OP_RESET_IN msgrequest: Perform a FPGA reset operation where
+ * supported.
+ */
+#define MC_CMD_FPGA_OP_RESET_IN_LEN 4
+/* Sub-command code. Must be OP_RESET */
+#define MC_CMD_FPGA_OP_RESET_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_RESET_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_RESET_OUT msgresponse */
+#define MC_CMD_FPGA_OP_RESET_OUT_LEN 0
+
+/* MC_CMD_FPGA_OP_SELECT_FLASH_IN msgrequest: Set active FPGA flash device.
+ * Returns EINVAL if selected flash index does not exist on the platform under
+ * test.
+ */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_LEN 8
+/* Sub-command code. Must be OP_SELECT_FLASH */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_OP_LEN 4
+/* Flash device identifier. */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_FLASH_ID_OFST 4
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_FLASH_ID_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_FPGA_FLASH_INDEX */
+
+/* MC_CMD_FPGA_OP_SELECT_FLASH_OUT msgresponse */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_OUT_LEN 0
+
+/* MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN msgrequest: Get active FPGA flash device.
+ */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_LEN 4
+/* Sub-command code. Must be OP_GET_ACTIVE_FLASH */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT msgresponse: Returns flash identifier
+ * for current active flash.
+ */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_LEN 4
+/* Flash device identifier. */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_FLASH_ID_OFST 0
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_FLASH_ID_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_FPGA_FLASH_INDEX */
+
+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN msgrequest: Configure FPGA internal
+ * port, facing the ASIC
+ */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LEN 12
+/* Sub-command code. Must be OP_SET_INTERNAL_LINK */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_OP_LEN 4
+/* Flags */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLAGS_OFST 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLAGS_LEN 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_OFST 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_LBN 0
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_WIDTH 2
+/* enum: Unmodified, same as last state set by firmware */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_AUTO 0x0
+/* enum: Configure link-up */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_UP 0x1
+/* enum: Configure link-down */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_DOWN 0x2
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_OFST 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_LBN 2
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_WIDTH 1
+/* Link speed to be applied on FPGA internal port MAC. */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_SPEED_OFST 8
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_SPEED_LEN 4
+
+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_OUT msgresponse */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_OUT_LEN 0
+
+/* MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN msgrequest: Read FPGA internal port
+ * configuration and status
+ */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_LEN 4
+/* Sub-command code. Must be OP_GET_INTERNAL_LINK */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT msgresponse: Response format for read
+ * FPGA internal port configuration and status
+ */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LEN 8
+/* Flags */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_FLAGS_OFST 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_FLAGS_LEN 4
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_OFST 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_LBN 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_WIDTH 2
+/* Enum values, see field(s): */
+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN/FLAGS */
+/* Link speed set on FPGA internal port MAC. */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_SPEED_OFST 4
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_SPEED_LEN 4
+
+
+/***********************************/
+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE
+ * This command is expected to be used on a U25 board with an MAE in the FPGA.
+ * It does not modify the operational state of the NIC. The modes are described
+ * in XN-200039-TC - U25 OVS packet formats.
+ */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE 0x1c0
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_MSGSET 0x1c0
+#undef MC_CMD_0x1c0_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_IN msgrequest */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_IN_LEN 0
+
+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT msgresponse */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_LEN 4
+/* The current link mode */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_MODE_OFST 0
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_MODE_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_EXTERNAL_MAE_LINK_MODE */
+
+
+/***********************************/
+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE
+ * This command is expected to be used on a U25 board with an MAE in the FPGA.
+ * The modes are described in XN-200039-TC - U25 OVS packet formats. This
+ * command will set the link between the FPGA and the X2 to the specified new
+ * mode. It will first enter bootstrap mode, make sure there are no packets in
+ * flight and then enter the requested mode. In order to make sure there are no
+ * packets in flight, it will flush the X2 TX path, the FPGA RX path from the
+ * X2, the FPGA TX path to the X2 and the X2 RX path. The driver is responsible
+ * for making sure there are no TX or RX descriptors posted on any TXQ or RXQ
+ * associated with the affected port before invoking this command. This command
+ * is run implicitly with MODE set to LEGACY when MC_CMD_DRV_ATTACH is
+ * executed.
+ */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE 0x1c1
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_MSGSET 0x1c1
+#undef MC_CMD_0x1c1_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN msgrequest */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_LEN 4
+/* The new link mode. */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_MODE_OFST 0
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_MODE_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_EXTERNAL_MAE_LINK_MODE */
+
+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_OUT msgresponse */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_OUT_LEN 0
+
+/* CLIENT_HANDLE structuredef: A client is an abstract entity that can make
+ * requests of the device and that can own resources managed by the device.
+ * Examples of clients include PCIe functions and dynamic clients. A client
+ * handle is a 32b opaque value used to refer to a client. Further details can
+ * be found within XN-200418-TC.
+ */
+#define CLIENT_HANDLE_LEN 4
+#define CLIENT_HANDLE_OPAQUE_OFST 0
+#define CLIENT_HANDLE_OPAQUE_LEN 4
+/* enum: A client handle guaranteed never to refer to a real client. */
+#define CLIENT_HANDLE_NULL 0xffffffff
+/* enum: Used to refer to the calling client. */
+#define CLIENT_HANDLE_SELF 0xfffffffe
+#define CLIENT_HANDLE_OPAQUE_LBN 0
+#define CLIENT_HANDLE_OPAQUE_WIDTH 32
+
/* CLOCK_INFO structuredef: Information about a single hardware clock */
#define CLOCK_INFO_LEN 28
/* Enumeration that uniquely identifies the clock */
@@ -24333,7 +26311,13 @@
#define CLOCK_INFO_FREQUENCY_OFST 4
#define CLOCK_INFO_FREQUENCY_LEN 8
#define CLOCK_INFO_FREQUENCY_LO_OFST 4
+#define CLOCK_INFO_FREQUENCY_LO_LEN 4
+#define CLOCK_INFO_FREQUENCY_LO_LBN 32
+#define CLOCK_INFO_FREQUENCY_LO_WIDTH 32
#define CLOCK_INFO_FREQUENCY_HI_OFST 8
+#define CLOCK_INFO_FREQUENCY_HI_LEN 4
+#define CLOCK_INFO_FREQUENCY_HI_LBN 64
+#define CLOCK_INFO_FREQUENCY_HI_WIDTH 32
#define CLOCK_INFO_FREQUENCY_LBN 32
#define CLOCK_INFO_FREQUENCY_WIDTH 64
/* Human-readable ASCII name for clock, with NUL termination */
@@ -24343,12 +26327,62 @@
#define CLOCK_INFO_NAME_LBN 96
#define CLOCK_INFO_NAME_WIDTH 8
+/* SCHED_CREDIT_CHECK_RESULT structuredef */
+#define SCHED_CREDIT_CHECK_RESULT_LEN 16
+/* The instance of the scheduler. Refer to XN-200389-AW for the location of
+ * these schedulers in the hardware.
+ */
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LEN 1
+#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_A 0x0 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_A 0x1 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_B 0x2 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_C 0x3 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_TX 0x4 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_D 0x5 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_REPLAY 0x6 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_WIDTH 8
+/* The type of node that this result refers to. */
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_OFST 1
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LEN 1
+/* enum: Destination node */
+#define SCHED_CREDIT_CHECK_RESULT_DEST 0x0
+/* enum: Source node */
+#define SCHED_CREDIT_CHECK_RESULT_SOURCE 0x1
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LBN 8
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_WIDTH 8
+/* Level of node in scheduler hierarchy (level 0 is the bottom of the
+ * hierarchy, increasing towards the root node).
+ */
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_OFST 2
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LEN 2
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LBN 16
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_WIDTH 16
+/* Node index */
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_OFST 4
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LEN 4
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LBN 32
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_WIDTH 32
+/* The number of credits the node is expected to have. */
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_OFST 8
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LEN 4
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LBN 64
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_WIDTH 32
+/* The number of credits the node actually had. */
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_OFST 12
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LBN 96
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_WIDTH 32
+
/***********************************/
/* MC_CMD_GET_CLOCKS_INFO
* Get information about the device clocks
*/
#define MC_CMD_GET_CLOCKS_INFO 0x166
+#define MC_CMD_GET_CLOCKS_INFO_MSGSET 0x166
#undef MC_CMD_0x166_PRIVILEGE_CTG
#define MC_CMD_0x166_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24387,6 +26421,7 @@
* returns ENOSPC if the caller's table is full.
*/
#define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d
+#define MC_CMD_VNIC_ENCAP_RULE_ADD_MSGSET 0x16d
#undef MC_CMD_0x16d_PRIVILEGE_CTG
#define MC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24469,6 +26504,7 @@
* if the input HANDLE doesn't correspond to an existing rule.
*/
#define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e
+#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_MSGSET 0x16e
#undef MC_CMD_0x16e_PRIVILEGE_CTG
#define MC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24508,303 +26544,568 @@
#define UUID_NODE_LBN 80
#define UUID_NODE_WIDTH 48
-/* MC_CMD_DEVEL_DUMP_VI_ENTRY structuredef */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_LEN 28
-/* Type of entry */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_C2H 0x0 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_H2C 0x1 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_C2H 0x2 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_H2C 0x3 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_C2H 0x4 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_H2C 0x5 /* enum */
-/* enum: First QDMA writeback/completion queue. Used for ef100, C2H VDPA and
- * plain virtio.
- */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_WRB 0x6
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_PFTCH 0x7 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_QTBL 0x100 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_C2H_QTBL 0x101 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_VIO 0x10a /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LBN 0
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_WIDTH 32
-/* Internal QDMA/dmac queue number for this entry */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_OFST 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LBN 32
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_WIDTH 32
-/* Size of entry data */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_OFST 8
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LBN 64
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_WIDTH 32
-/* Offset of entry data from start of MCDI message response payload */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_OFST 12
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LBN 96
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_WIDTH 32
-/* Absolute VI of the entry, or 0xffffffff if not available/applicable */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_OFST 16
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_NO_ABS_VI 0xffffffff /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LBN 128
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_WIDTH 32
-/* Reserved */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_OFST 20
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LEN 8
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LO_OFST 20
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_HI_OFST 24
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LBN 160
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_WIDTH 64
-
-
-/***********************************/
-/* MC_CMD_DEVEL_DUMP_VI
- * Dump various parts of the hardware's state for a VI.
- */
-#define MC_CMD_DEVEL_DUMP_VI 0x1b5
-#undef MC_CMD_0x1b5_PRIVILEGE_CTG
-
-#define MC_CMD_0x1b5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
-
-/* MC_CMD_DEVEL_DUMP_VI_IN msgrequest */
-#define MC_CMD_DEVEL_DUMP_VI_IN_LEN 4
-/* Absolute queue id of queue to dump state for */
-#define MC_CMD_DEVEL_DUMP_VI_IN_QID_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_IN_QID_LEN 4
-
-/* MC_CMD_DEVEL_DUMP_VI_IN_V2 msgrequest */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_LEN 20
-/* Which queue to dump. The meaning of this field dependes on ADDRESS_MODE. */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ID_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ID_LEN 4
-/* Method of referring to the queue to dump */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_OFST 4
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_LEN 4
-/* enum: First field refers to queue number as understood by QDMA/DMAC hardware
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_QUEUE_NUMBER 0x0
-/* enum: First field refers to absolute VI number */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ABS_VI 0x1
-/* enum: First field refers to function-relative VI number on the command's
- * function
+/* PLUGIN_EXTENSION structuredef: Used within MC_CMD_PLUGIN_GET_ALL to describe
+ * an individual extension.
+ */
+#define PLUGIN_EXTENSION_LEN 20
+#define PLUGIN_EXTENSION_UUID_OFST 0
+#define PLUGIN_EXTENSION_UUID_LEN 16
+#define PLUGIN_EXTENSION_UUID_LBN 0
+#define PLUGIN_EXTENSION_UUID_WIDTH 128
+#define PLUGIN_EXTENSION_ADMIN_GROUP_OFST 16
+#define PLUGIN_EXTENSION_ADMIN_GROUP_LEN 1
+#define PLUGIN_EXTENSION_ADMIN_GROUP_LBN 128
+#define PLUGIN_EXTENSION_ADMIN_GROUP_WIDTH 8
+#define PLUGIN_EXTENSION_FLAG_ENABLED_LBN 136
+#define PLUGIN_EXTENSION_FLAG_ENABLED_WIDTH 1
+#define PLUGIN_EXTENSION_RESERVED_LBN 137
+#define PLUGIN_EXTENSION_RESERVED_WIDTH 23
+
+/* DESC_ADDR_REGION structuredef: Describes a contiguous region of DESC_ADDR
+ * space that maps to a contiguous region of TRGT_ADDR space. Addresses
+ * DESC_ADDR in the range [DESC_ADDR_BASE:DESC_ADDR_BASE + 1 <<
+ * WINDOW_SIZE_LOG2) map to TRGT_ADDR = DESC_ADDR - DESC_ADDR_BASE +
+ * TRGT_ADDR_BASE.
+ */
+#define DESC_ADDR_REGION_LEN 32
+/* The start of the region in DESC_ADDR space. */
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_OFST 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LEN 8
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_OFST 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LEN 4
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LBN 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_WIDTH 32
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_OFST 4
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LEN 4
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LBN 32
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_WIDTH 32
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LBN 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_WIDTH 64
+/* The start of the region in TRGT_ADDR space. Drivers can set this via
+ * MC_CMD_SET_DESC_ADDR_REGIONS.
+ */
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_OFST 8
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LEN 8
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_OFST 8
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LEN 4
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LBN 64
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_WIDTH 32
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_OFST 12
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LEN 4
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LBN 96
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_WIDTH 32
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LBN 64
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_WIDTH 64
+/* The size of the region. */
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_OFST 16
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LEN 4
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LBN 128
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_WIDTH 32
+/* The alignment restriction on TRGT_ADDR. TRGT_ADDR values set by the driver
+ * must be a multiple of 1 << TRGT_ADDR_ALIGN_LOG2.
+ */
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_OFST 20
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LEN 4
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LBN 160
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_WIDTH 32
+#define DESC_ADDR_REGION_RSVD_OFST 24
+#define DESC_ADDR_REGION_RSVD_LEN 8
+#define DESC_ADDR_REGION_RSVD_LO_OFST 24
+#define DESC_ADDR_REGION_RSVD_LO_LEN 4
+#define DESC_ADDR_REGION_RSVD_LO_LBN 192
+#define DESC_ADDR_REGION_RSVD_LO_WIDTH 32
+#define DESC_ADDR_REGION_RSVD_HI_OFST 28
+#define DESC_ADDR_REGION_RSVD_HI_LEN 4
+#define DESC_ADDR_REGION_RSVD_HI_LBN 224
+#define DESC_ADDR_REGION_RSVD_HI_WIDTH 32
+#define DESC_ADDR_REGION_RSVD_LBN 192
+#define DESC_ADDR_REGION_RSVD_WIDTH 64
+
+
+/***********************************/
+/* MC_CMD_GET_DESC_ADDR_INFO
+ * Returns a description of the mapping from DESC_ADDR to TRGT_ADDR for the calling function's address space.
+ */
+#define MC_CMD_GET_DESC_ADDR_INFO 0x1b7
+#define MC_CMD_GET_DESC_ADDR_INFO_MSGSET 0x1b7
+#undef MC_CMD_0x1b7_PRIVILEGE_CTG
+
+#define MC_CMD_0x1b7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_DESC_ADDR_INFO_IN msgrequest */
+#define MC_CMD_GET_DESC_ADDR_INFO_IN_LEN 0
+
+/* MC_CMD_GET_DESC_ADDR_INFO_OUT msgresponse */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_LEN 4
+/* The type of mapping; see SF-nnnnnn-xx (EF100 driver writer's guide, once
+ * written) for details of each type.
+ */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_OFST 0
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_LEN 4
+/* enum: TRGT_ADDR = DESC_ADDR */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT 0x0
+/* enum: DESC_ADDR has one or more regions that map into TRGT_ADDR. The base
+ * TRGT_ADDR for each region is programmable via MCDI.
+ */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED 0x1
+
+
+/***********************************/
+/* MC_CMD_GET_DESC_ADDR_REGIONS
+ * Returns a list of the DESC_ADDR regions for the calling function's address space. Only valid if that function's address space has the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
+ */
+#define MC_CMD_GET_DESC_ADDR_REGIONS 0x1b8
+#define MC_CMD_GET_DESC_ADDR_REGIONS_MSGSET 0x1b8
+#undef MC_CMD_0x1b8_PRIVILEGE_CTG
+
+#define MC_CMD_0x1b8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_DESC_ADDR_REGIONS_IN msgrequest */
+#define MC_CMD_GET_DESC_ADDR_REGIONS_IN_LEN 0
+
+/* MC_CMD_GET_DESC_ADDR_REGIONS_OUT msgresponse */
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMIN 32
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX 224
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX_MCDI2 992
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LEN(num) (0+32*(num))
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)
+/* An array of DESC_ADDR_REGION strutures. The number of entries in the array
+ * indicates the number of available regions.
+ */
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_OFST 0
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_LEN 32
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MINNUM 1
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM 7
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM_MCDI2 31
+
+
+/***********************************/
+/* MC_CMD_SET_DESC_ADDR_REGIONS
+ * Set the base TRGT_ADDR for a set of DESC_ADDR regions for the calling function's address space. Only valid if that function's address space had the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
+ */
+#define MC_CMD_SET_DESC_ADDR_REGIONS 0x1b9
+#define MC_CMD_SET_DESC_ADDR_REGIONS_MSGSET 0x1b9
+#undef MC_CMD_0x1b9_PRIVILEGE_CTG
+
+#define MC_CMD_0x1b9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_DESC_ADDR_REGIONS_IN msgrequest */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMIN 16
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX 248
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX_MCDI2 1016
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LEN(num) (8+8*(num))
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_NUM(len) (((len)-8)/8)
+/* A bitmask indicating which regions should have their base TRGT_ADDR updated.
+ * To update the base TRGR_ADDR for a DESC_ADDR region, the corresponding bit
+ * should be set to 1.
+ */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_OFST 0
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_LEN 4
+/* Reserved field; must be set to zero. */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_OFST 4
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_LEN 4
+/* An array of values used to updated the base TRGT_ADDR for DESC_ADDR regions.
+ * Array indices corresponding to region numbers (i.e. the array is sparse, and
+ * included entries for regions even if the corresponding SET_REGION_MASK bit
+ * is zero).
*/
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI 0x2
-/* enum: First field refers to function-relative VI number on a specified
- * function
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI_PROXY 0x3
-/* Type of VI. Not needed if ADDRESS_MODE is QUEUE_NUMBER. */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_OFST 8
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_LEN 4
-/* enum: Return only entries used for ef100 queues (a single hardware queue) */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_EF100 0x0
-/* enum: Return entries used for virtio (Potentially two hardware queues,
- * depending on hardware implementation)
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VIRTIO 0x1
-/* Only if ADDRESS_MODE is REL_VI_PROXY. Interface of function the queue is on.
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_OFST 8
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LEN 8
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_OFST 8
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LEN 4
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LBN 64
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_WIDTH 32
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_OFST 12
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LEN 4
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LBN 96
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_WIDTH 32
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MINNUM 1
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM 30
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM_MCDI2 126
+
+/* MC_CMD_SET_DESC_ADDR_REGIONS_OUT msgresponse */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_CLIENT_CMD
+ * Execute an arbitrary MCDI command on behalf of a different client. The
+ * consequences of the command (e.g. ownership of any resources created) apply
+ * to the indicated client rather than the function client which actually sent
+ * this command. All inherent permission checks are also performed on the
+ * indicated client. The given client must be a descendant of the requestor.
+ * The command to be proxied follows immediately afterward in the host buffer
+ * (or on the UART). Chaining multiple MC_CMD_CLIENT_CMD is unnecessary and not
+ * supported. New dynamic clients may be created with MC_CMD_CLIENT_ALLOC.
*/
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_OFST 12
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_LEN 4
-/* Enum values, see field(s): */
-/* DEVEL_PCIE_INTERFACE */
-/* Only if ADDRESS_MODE is REL_VI_PROXY. PF number of the function the queue is
- * on.
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PF_OFST 16
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PF_LEN 2
-/* Only if ADDRESS_MODE is REL_VI_PROXY. VF number of the function the queue is
- * on.
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VF_OFST 18
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VF_LEN 2
-/* enum: The function is on a PF, not a VF. */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VF_NULL 0xffff
-
-/* MC_CMD_DEVEL_DUMP_VI_OUT msgresponse */
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LENMIN 4
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LENMAX 252
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LENMAX_MCDI2 1012
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LEN(num) (0+1*(num))
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_NUM(len) (((len)-0)/1)
-/* Number of dump entries returned */
-#define MC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_LBN 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_WIDTH 8
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_MINNUM 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM 252
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM_MCDI2 1020
-/* Array of MC_CMD_DEVEL_DUMP_VI_ENTRY structures of length NUM_ENTRIES */
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_OFST 4
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_LEN 28
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MINNUM 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM 8
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM_MCDI2 36
-
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structuredef */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_LEN 16
-/* What register this is */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_OFST 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LEN 4
-/* enum: Catchall for registers that aren't in this enum. Nothing should be in
- * this long-term
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_UNKNOWN 0xffffffff
-/* enum: S2IC Converter Debug Packet Counter register. Informs number of
- * packets passed through Converter.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_H2C_S2IC_DBG_PKT_CNT 0x0
-/* enum: IC2S Converter Debug Packet Counter register. Informs number of
- * packets passed through Converter.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_C2H_IC2S_DBG_PKT_CNT 0x1
-/* enum: Event Controller Tx path Debug register. Count of Moderator Tx events,
- * not incl D2C, VirtIO, Dproxy.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DEBUG 0x2
-/* enum: Event Controller Rx path Debug register. Count of Moderator Rx events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_DEBUG 0x3
-/* enum: Event Controller Debug register. Count of Total EVC events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TOTAL_DEBUG 0x4
-/* enum: Same info as EVC_RX_DEBUG; collected at different location in design
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EF100_DEBUG 0x5
-/* enum: Same info as EVC_TX_DEBUG; collected at different location in design
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_EF100_DEBUG 0x6
-/* enum: Event Controller Debug register. Count of Tx VirtIO events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTIO_DEBUG 0x7
-/* enum: Event Controller Debug register. Count of Tx Descriptor Proxy events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DPRXY_DEBUG 0x8
-/* enum: Event Controller Debug register. Count of Tx VirtQ Descriptor Proxy
- * events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_DPRXY_DEBUG 0x9
-/* enum: Event Controller Debug register. Count of Tx Descriptor-to-Completion
- * events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_D2C_DEBUG 0xa
-/* enum: Event Controller Debug register. Count of Tx VirtIO Descriptor-to-
- * Completion events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_D2C_DEBUG 0xb
-/* enum: Event Controller Debug register. Count of Tx Timestamp events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_TSTAMP_DEBUG 0xc
-/* enum: Event Controller Debug register. Count of Rx EvQ Timeout events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EVQ_TIMEOUT_DEBUG 0xd
-/* enum: Event Controller Debug register. Count of MC events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_MC_DEBUG 0xe
-/* enum: Event Controller Debug register. Count of EQDMA VirtIO Control events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_EQDMA_VIO_CTL_DEBUG 0xf
-/* enum: Counter of QDMA Dropped C2H packets. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_DMAC_C2H_DROP_CTR_REG 0x10
-/* enum: Number of packets received by c host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_IN_TBL 0x11
-/* enum: Number of packets sent by c host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_OUT_TBL 0x12
-/* enum: Number of packets received by c plugin fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_P_PACKETS_IN_TBL 0x13
-/* enum: Number of packets received by b host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_H_PACKETS_IN_TBL 0x14
-/* enum: Number of packets received by b net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_N_PACKETS_IN_TBL 0x15
-/* enum: Number of packets received by b host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PH_PACKETS_IN_TBL 0x16
-/* enum: Number of packets received by b net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PN_PACKETS_IN_TBL 0x17
-/* enum: Number of packets sent by b net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PACKETS_OUT_TBL 0x18
-/* enum: Number of packets received by c net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_IN_TBL 0x19
-/* enum: Number of packets sent by c net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_OUT_TBL 0x1a
-/* enum: Number of packets received by ha fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_IN_TBL 0x1b
-/* enum: Number of packets received by ha host shadow fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PH_PACKETS_IN_TBL 0x1c
-/* enum: Number of packets received by ha fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_OUT_TBL 0x1d
-/* enum: Number of packets received by d hub fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_IN_TBL 0x1e
-/* enum: Number of packets received by d hub plugin fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_P_PACKETS_IN_TBL 0x1f
-/* enum: Number of packets received by d hub plugin fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_O_PACKETS_IN_TBL 0x20
-/* enum: Number of packets sent to dmac. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_OUT_TBL 0x21
-/* enum: Number of packets received by na fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_IN_TBL 0x22
-/* enum: Number of packets dropped by na fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_DROPPED_TBL 0x23
-/* enum: Number of packets sent by na fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_OUT_TBL 0x24
-/* enum: Number of packets received by rp hub fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_IN_TBL 0x25
-/* enum: Number of packets removed from fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_OUT_TBL 0x26
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LBN 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_WIDTH 32
-/* If REG is a table, the table row. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_OFST 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LEN 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LBN 32
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_WIDTH 32
-/* Address of the register (as seen by the MC) */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_OFST 8
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LEN 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LBN 64
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_WIDTH 32
-/* Value of the register */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_OFST 12
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LEN 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LBN 96
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_WIDTH 32
-
-
-/***********************************/
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS
- * Dump an assortment of hopefully useful riverhead debug registers
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS 0x1b6
-#undef MC_CMD_0x1b6_PRIVILEGE_CTG
-
-#define MC_CMD_0x1b6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
-
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN msgrequest */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_LEN 4
-/* Which page of registers to retrieve. Page 0 always exists, later pages may
- * also exist if there are too many registers to fit in a single mcdi response.
- * NUM_PAGES in the response will tell you how many there are.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_OFST 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_LEN 4
-
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT msgresponse */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMIN 8
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX 248
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX_MCDI2 1016
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LEN(num) (8+16*(num))
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_NUM(len) (((len)-8)/16)
-/* Number of registers dumped in this response */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_OFST 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_LEN 4
-/* How many pages of registers are available to extract */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_OFST 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_LEN 4
-/* Array of MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structs, one for each register
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_OFST 8
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_LEN 16
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MINNUM 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM 15
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM_MCDI2 63
+#define MC_CMD_CLIENT_CMD 0x1ba
+#define MC_CMD_CLIENT_CMD_MSGSET 0x1ba
+#undef MC_CMD_0x1ba_PRIVILEGE_CTG
+
+#define MC_CMD_0x1ba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CLIENT_CMD_IN msgrequest */
+#define MC_CMD_CLIENT_CMD_IN_LEN 4
+/* The client as which to execute the following command. */
+#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_OFST 0
+#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_LEN 4
+
+/* MC_CMD_CLIENT_CMD_OUT msgresponse */
+#define MC_CMD_CLIENT_CMD_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_CLIENT_ALLOC
+ * Create a new client object. Clients are a system for delineating NIC
+ * resource ownership, such that groups of resources may be torn down as a
+ * unit. See also MC_CMD_CLIENT_CMD. See XN-200265-TC for background, concepts
+ * and a glossary. Clients created by this command are known as "dynamic
+ * clients". The newly-created client is a child of the client which sent this
+ * command. The caller must have the GRP_ALLOC_CLIENT privilege. The new client
+ * initially has no permission to do anything; see
+ * MC_CMD_DEVEL_CLIENT_PRIVILEGE_MODIFY.
+ */
+#define MC_CMD_CLIENT_ALLOC 0x1bb
+#define MC_CMD_CLIENT_ALLOC_MSGSET 0x1bb
+#undef MC_CMD_0x1bb_PRIVILEGE_CTG
+
+#define MC_CMD_0x1bb_PRIVILEGE_CTG SRIOV_CTG_ALLOC_CLIENT
+
+/* MC_CMD_CLIENT_ALLOC_IN msgrequest */
+#define MC_CMD_CLIENT_ALLOC_IN_LEN 0
+
+/* MC_CMD_CLIENT_ALLOC_OUT msgresponse */
+#define MC_CMD_CLIENT_ALLOC_OUT_LEN 4
+/* The ID of the new client object which has been created. */
+#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_OFST 0
+#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_LEN 4
+
+
+/***********************************/
+/* MC_CMD_CLIENT_FREE
+ * Destroy and release an existing client object. All resources owned by that
+ * client (including its child clients, and thus all resources owned by the
+ * entire family tree) are freed.
+ */
+#define MC_CMD_CLIENT_FREE 0x1bc
+#define MC_CMD_CLIENT_FREE_MSGSET 0x1bc
+#undef MC_CMD_0x1bc_PRIVILEGE_CTG
+
+#define MC_CMD_0x1bc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CLIENT_FREE_IN msgrequest */
+#define MC_CMD_CLIENT_FREE_IN_LEN 4
+/* The ID of the client to be freed. This client must be a descendant of the
+ * requestor. A client cannot free itself.
+ */
+#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_OFST 0
+#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_LEN 4
+
+/* MC_CMD_CLIENT_FREE_OUT msgresponse */
+#define MC_CMD_CLIENT_FREE_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_SET_VI_USER
+ * Assign partial rights over this VI to another client. VIs have an 'owner'
+ * and a 'user'. The owner is the client which allocated the VI
+ * (MC_CMD_ALLOC_VIS) and cannot be changed. The user is the client which has
+ * permission to create queues and other resources on that VI. Initially
+ * user==owner, but the user can be changed by this command; the resources thus
+ * created are then owned by the user-client. Only the VI owner can call this
+ * command, and the request will fail if there are any outstanding child
+ * resources (e.g. queues) currently allocated from this VI.
+ */
+#define MC_CMD_SET_VI_USER 0x1be
+#define MC_CMD_SET_VI_USER_MSGSET 0x1be
+#undef MC_CMD_0x1be_PRIVILEGE_CTG
+
+#define MC_CMD_0x1be_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_VI_USER_IN msgrequest */
+#define MC_CMD_SET_VI_USER_IN_LEN 8
+/* Function-relative VI number to modify. */
+#define MC_CMD_SET_VI_USER_IN_INSTANCE_OFST 0
+#define MC_CMD_SET_VI_USER_IN_INSTANCE_LEN 4
+/* Client ID to become the new user. This must be a descendant of the owning
+ * client, the owning client itself, or the special value MC_CMD_CLIENT_ID_SELF
+ * which is synonymous with the owning client.
+ */
+#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_OFST 4
+#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_LEN 4
+
+/* MC_CMD_SET_VI_USER_OUT msgresponse */
+#define MC_CMD_SET_VI_USER_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES
+ * A device reports a set of MAC addresses for each client to use, known as the
+ * "permanent MAC addresses". Those MAC addresses are provided by the client's
+ * administrator, e.g. via MC_CMD_SET_CLIENT_MAC_ADDRESSES, and are intended as
+ * a hint to that client which MAC address its administrator would like to use
+ * to identity itself. This API exists solely to allow communication of MAC
+ * address from administrator to adminstree, and has no inherent interaction
+ * with switching within the device. There is no guarantee that a client will
+ * be able to send traffic with a source MAC address taken from the list of MAC
+ * address reported, nor is there a guarantee that a client will be able to
+ * resource traffic with a destination MAC taken from the list of MAC
+ * addresses. Likewise, there is no guarantee that a client will not be able to
+ * use a MAC address not present in the list. Restrictions on switching are
+ * controlled either through the EVB API if operating in EVB mode, or via MAE
+ * rules if host software is directly managing the MAE. In order to allow
+ * tenants to use this API whilst a provider is using the EVB API, the MAC
+ * addresses reported by MC_CMD_GET_CLIENT_MAC_ADDRESSES will be augmented with
+ * any MAC addresses associated with the vPort assigned to the caller. In order
+ * to allow tenants to use the EVB API whilst a provider is using this API, if
+ * a client queries the MAC addresses for a vPort using the host_evb_port_id
+ * EVB_PORT_ASSIGNED, that list of MAC addresses will be augmented with the MAC
+ * addresses assigned to the calling client. This query can either be explicit
+ * (i.e. MC_CMD_VPORT_GET_MAC_ADDRESSES) or implicit (e.g. creation of a
+ * vAdaptor with a NULL/automatic MAC address). Changing the MAC address on a
+ * vAdaptor only affects VNIC steering filters; it has no effect on the MAC
+ * addresses assigned to the vAdaptor's owner. VirtIO clients behave as EVB
+ * clients. On VirtIO device reset, a vAdaptor is created with an automatic MAC
+ * address. Querying the VirtIO device's MAC address queries the underlying
+ * vAdaptor's MAC address. Setting the VirtIO device's MAC address sets the
+ * underlying vAdaptor's MAC addresses.
+ */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES 0x1c4
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_MSGSET 0x1c4
+#undef MC_CMD_0x1c4_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN msgrequest */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN 4
+/* A handle for the client for whom MAC address should be obtained. Use
+ * CLIENT_HANDLE_SELF to obtain the MAC addresses assigned to the calling
+ * client.
+ */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
+
+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMIN 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX 252
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(num) (0+6*(num))
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)
+/* An array of MAC addresses assigned to the client. */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_OFST 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_LEN 6
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MINNUM 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM 42
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM_MCDI2 170
+
+
+/***********************************/
+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES
+ * Set the permanent MAC addresses for a client. The caller must by an
+ * administrator of the target client. See MC_CMD_GET_CLIENT_MAC_ADDRESSES for
+ * additional detail.
+ */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES 0x1c5
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_MSGSET 0x1c5
+#undef MC_CMD_0x1c5_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN msgrequest */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMIN 4
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX 250
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX_MCDI2 1018
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LEN(num) (4+6*(num))
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_NUM(len) (((len)-4)/6)
+/* A handle for the client for whom MAC addresses should be set */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
+/* An array of MAC addresses to assign to the client. */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_OFST 4
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_LEN 6
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MINNUM 0
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM 41
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM_MCDI2 169
+
+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_BOARD_ATTR
+ * Retrieve physical build-level board attributes as configured at
+ * manufacturing stage. Fields originate from EEPROM and per-platform constants
+ * in firmware. Fields are used in development to identify/ differentiate
+ * boards based on build levels/parameters, and also in manufacturing to cross
+ * check "what was programmed in manufacturing" is same as "what firmware
+ * thinks has been programmed" as there are two layers to translation within
+ * firmware before the attributes reach this MCDI handler. Some parameters are
+ * retrieved as part of other commands and therefore not replicated here. See
+ * GET_VERSION_OUT.
+ */
+#define MC_CMD_GET_BOARD_ATTR 0x1c6
+#define MC_CMD_GET_BOARD_ATTR_MSGSET 0x1c6
+#undef MC_CMD_0x1c6_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_BOARD_ATTR_IN msgrequest */
+#define MC_CMD_GET_BOARD_ATTR_IN_LEN 0
+
+/* MC_CMD_GET_BOARD_ATTR_OUT msgresponse */
+#define MC_CMD_GET_BOARD_ATTR_OUT_LEN 16
+/* Defines board capabilities and validity of attributes returned in this
+ * response-message.
+ */
+#define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_LBN 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_LBN 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_LBN 2
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_LEN 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_LBN 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_LBN 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_LBN 16
+#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_WIDTH 8
+/* enum: The FPGA voltage on the adapter can be set to low */
+#define MC_CMD_FPGA_VOLTAGE_LOW 0x0
+/* enum: The FPGA voltage on the adapter can be set to regular */
+#define MC_CMD_FPGA_VOLTAGE_REG 0x1
+/* enum: The FPGA voltage on the adapter can be set to high */
+#define MC_CMD_FPGA_VOLTAGE_HIGH 0x2
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_LBN 24
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_WIDTH 8
+/* An array of cage types on the board */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_OFST 8
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_LEN 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_NUM 8
+/* enum: The cages are not known */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_UNKNOWN 0x0
+/* enum: The cages are SFP/SFP+ */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_SFP 0x1
+/* enum: The cages are QSFP/QSFP+ */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_QSFP 0x2
+
+
+/***********************************/
+/* MC_CMD_GET_SOC_STATE
+ * Retrieve current state of the System-on-Chip. This command is valid when
+ * MC_CMD_GET_BOARD_ATTR:HAS_SOC is set.
+ */
+#define MC_CMD_GET_SOC_STATE 0x1c7
+#define MC_CMD_GET_SOC_STATE_MSGSET 0x1c7
+#undef MC_CMD_0x1c7_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_SOC_STATE_IN msgrequest */
+#define MC_CMD_GET_SOC_STATE_IN_LEN 0
+
+/* MC_CMD_GET_SOC_STATE_OUT msgresponse */
+#define MC_CMD_GET_SOC_STATE_OUT_LEN 12
+/* Status flags for the SoC */
+#define MC_CMD_GET_SOC_STATE_OUT_FLAGS_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_LBN 0
+#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_WIDTH 1
+#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_LBN 1
+#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_WIDTH 1
+#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_LBN 2
+#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_WIDTH 1
+/* Status fields for the SoC */
+#define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_OFST 4
+#define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_LEN 4
+#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_OFST 4
+#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_LBN 0
+#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_WIDTH 8
+/* enum: Power on (set by SUC on power up) */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOT 0x0
+/* enum: Running bootloader */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOTLOADER 0x1
+/* enum: Bootloader has started OS. OS is booting */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_START 0x2
+/* enum: OS is running */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_RUNNING 0x3
+/* enum: Maintenance OS is running */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_MAINTENANCE 0x4
+/* Number of SoC resets since power on */
+#define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_OFST 8
+#define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_LEN 4
+
+
+/***********************************/
+/* MC_CMD_CHECK_SCHEDULER_CREDITS
+ * For debugging purposes. For each source and destination node in the hardware
+ * schedulers, check whether the number of credits is as it should be. This
+ * should only be used when the NIC is idle, because collection is not atomic
+ * and because the expected credit counts are only meaningful when no traffic
+ * is flowing.
+ */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS 0x1c8
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_MSGSET 0x1c8
+#undef MC_CMD_0x1c8_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
+
+/* MC_CMD_CHECK_SCHEDULER_CREDITS_IN msgrequest */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_LEN 8
+/* Flags for the request */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_OFST 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_LEN 4
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_OFST 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_LBN 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_WIDTH 1
+/* If there are too many results to fit into an MCDI response, they're split
+ * into pages. This field specifies which (0-indexed) page to request. A
+ * request with PAGE=0 will snapshot the results, and subsequent requests with
+ * PAGE>0 will return data from the most recent snapshot. The GENERATION field
+ * in the response allows callers to verify that all responses correspond to
+ * the same snapshot.
+ */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_OFST 4
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_LEN 4
+
+/* MC_CMD_CHECK_SCHEDULER_CREDITS_OUT msgresponse */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMIN 16
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX 240
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX_MCDI2 1008
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LEN(num) (16+16*(num))
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_NUM(len) (((len)-16)/16)
+/* The total number of results (across all pages). */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_OFST 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_LEN 4
+/* The number of pages that the response is split across. */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_OFST 4
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_LEN 4
+/* The number of results in this response. */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_OFST 8
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_LEN 4
+/* Result generation count. Incremented any time a request is made with PAGE=0.
+ */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_OFST 12
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_LEN 4
+/* The results, as an array of SCHED_CREDIT_CHECK_RESULT structures. */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_OFST 16
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_LEN 16
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM 14
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM_MCDI2 62
/* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are
* defined in SF-120734-TC with more information in SF-122717-TC.
@@ -24839,6 +27140,7 @@
* Get a list of the virtio features supported by the device.
*/
#define MC_CMD_VIRTIO_GET_FEATURES 0x168
+#define MC_CMD_VIRTIO_GET_FEATURES_MSGSET 0x168
#undef MC_CMD_0x168_PRIVILEGE_CTG
#define MC_CMD_0x168_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24867,7 +27169,13 @@
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LEN 8
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LEN 4
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LBN 0
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_WIDTH 32
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LEN 4
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LBN 32
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_WIDTH 32
/***********************************/
@@ -24877,6 +27185,7 @@
* the driver fails to request a feature which the device requires.
*/
#define MC_CMD_VIRTIO_TEST_FEATURES 0x169
+#define MC_CMD_VIRTIO_TEST_FEATURES_MSGSET 0x169
#undef MC_CMD_0x169_PRIVILEGE_CTG
#define MC_CMD_0x169_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24898,7 +27207,13 @@
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_OFST 8
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LEN 8
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_OFST 8
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LEN 4
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LBN 64
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_WIDTH 32
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_OFST 12
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LEN 4
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LBN 96
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_WIDTH 32
/* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */
#define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0
@@ -24912,6 +27227,7 @@
* invalid.
*/
#define MC_CMD_VIRTIO_INIT_QUEUE 0x16a
+#define MC_CMD_VIRTIO_INIT_QUEUE_MSGSET 0x16a
#undef MC_CMD_0x16a_PRIVILEGE_CTG
#define MC_CMD_0x16a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24956,17 +27272,35 @@
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_OFST 16
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_OFST 16
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LBN 128
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_OFST 20
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LBN 160
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_WIDTH 32
/* Address of the available ring in the virtqueue. */
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_OFST 24
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_OFST 24
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LBN 192
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_OFST 28
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LBN 224
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_WIDTH 32
/* Address of the used ring in the virtqueue. */
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_OFST 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_OFST 32
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LBN 256
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_OFST 36
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LBN 288
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_WIDTH 32
/* PASID to use on PCIe transactions involving this queue. Ignored if the
* USE_PASID flag is not set.
*/
@@ -24990,7 +27324,13 @@
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_OFST 48
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_OFST 48
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LBN 384
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_OFST 52
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LBN 416
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_WIDTH 32
/* Enum values, see field(s): */
/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_OUT/FEATURES */
/* The initial producer index for this queue's used ring. If this queue is
@@ -25023,6 +27363,7 @@
* Destroy a virtio virtqueue
*/
#define MC_CMD_VIRTIO_FINI_QUEUE 0x16b
+#define MC_CMD_VIRTIO_FINI_QUEUE_MSGSET 0x16b
#undef MC_CMD_0x16b_PRIVILEGE_CTG
#define MC_CMD_0x16b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -25063,6 +27404,7 @@
* queue(s) to be allocated.
*/
#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c
+#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_MSGSET 0x16c
#undef MC_CMD_0x16c_PRIVILEGE_CTG
#define MC_CMD_0x16c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -25132,12 +27474,18 @@
#define PCIE_FUNCTION_VF_NULL 0xffff
#define PCIE_FUNCTION_VF_LBN 16
#define PCIE_FUNCTION_VF_WIDTH 16
-/* PCIe interface of the function */
+/* PCIe interface of the function. Values should be taken from the
+ * PCIE_INTERFACE enum
+ */
#define PCIE_FUNCTION_INTF_OFST 4
#define PCIE_FUNCTION_INTF_LEN 4
-/* enum: Host PCIe interface */
+/* enum: Host PCIe interface. (Alias for HOST_PRIMARY, provided for backwards
+ * compatibility)
+ */
#define PCIE_FUNCTION_INTF_HOST 0x0
-/* enum: Application Processor interface */
+/* enum: Application Processor interface (alias for NIC_EMBEDDED, provided for
+ * backwards compatibility)
+ */
#define PCIE_FUNCTION_INTF_AP 0x1
#define PCIE_FUNCTION_INTF_LBN 32
#define PCIE_FUNCTION_INTF_WIDTH 32
@@ -25157,6 +27505,7 @@
* MC_CMD_DESC_PROXY_FUNC_COMMIT_IN.
*/
#define MC_CMD_DESC_PROXY_FUNC_CREATE 0x172
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_MSGSET 0x172
#undef MC_CMD_0x172_PRIVILEGE_CTG
#define MC_CMD_0x172_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25170,7 +27519,19 @@
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LEN 8
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LBN 0
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_WIDTH 32
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LBN 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_WIDTH 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_OFST 0
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_OFST 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_LEN 4
/* The personality to set. The meanings of the personalities are defined in
* SF-120734-TC with more information in SF-122717-TC. At present, we only
* support proxying for VIRTIO_BLK
@@ -25194,7 +27555,19 @@
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LEN 8
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LBN 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_WIDTH 32
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LBN 64
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_WIDTH 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_OFST 6
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_LEN 4
/***********************************/
@@ -25205,6 +27578,7 @@
* ownership is released.
*/
#define MC_CMD_DESC_PROXY_FUNC_DESTROY 0x173
+#define MC_CMD_DESC_PROXY_FUNC_DESTROY_MSGSET 0x173
#undef MC_CMD_0x173_PRIVILEGE_CTG
#define MC_CMD_0x173_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25235,7 +27609,13 @@
#define VIRTIO_BLK_CONFIG_FEATURES_OFST 0
#define VIRTIO_BLK_CONFIG_FEATURES_LEN 8
#define VIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0
+#define VIRTIO_BLK_CONFIG_FEATURES_LO_LEN 4
+#define VIRTIO_BLK_CONFIG_FEATURES_LO_LBN 0
+#define VIRTIO_BLK_CONFIG_FEATURES_LO_WIDTH 32
#define VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4
+#define VIRTIO_BLK_CONFIG_FEATURES_HI_LEN 4
+#define VIRTIO_BLK_CONFIG_FEATURES_HI_LBN 32
+#define VIRTIO_BLK_CONFIG_FEATURES_HI_WIDTH 32
#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0
#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0
#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1
@@ -25308,7 +27688,13 @@
#define VIRTIO_BLK_CONFIG_CAPACITY_OFST 8
#define VIRTIO_BLK_CONFIG_CAPACITY_LEN 8
#define VIRTIO_BLK_CONFIG_CAPACITY_LO_OFST 8
+#define VIRTIO_BLK_CONFIG_CAPACITY_LO_LEN 4
+#define VIRTIO_BLK_CONFIG_CAPACITY_LO_LBN 64
+#define VIRTIO_BLK_CONFIG_CAPACITY_LO_WIDTH 32
#define VIRTIO_BLK_CONFIG_CAPACITY_HI_OFST 12
+#define VIRTIO_BLK_CONFIG_CAPACITY_HI_LEN 4
+#define VIRTIO_BLK_CONFIG_CAPACITY_HI_LBN 96
+#define VIRTIO_BLK_CONFIG_CAPACITY_HI_WIDTH 32
#define VIRTIO_BLK_CONFIG_CAPACITY_LBN 64
#define VIRTIO_BLK_CONFIG_CAPACITY_WIDTH 64
/* Maximum size of any single segment. Only valid when VIRTIO_BLK_F_SIZE_MAX is
@@ -25445,6 +27831,7 @@
* not persisted until the caller commits with MC_CMD_DESC_PROXY_FUNC_COMMIT_IN
*/
#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174
+#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_MSGSET 0x174
#undef MC_CMD_0x174_PRIVILEGE_CTG
#define MC_CMD_0x174_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25485,6 +27872,7 @@
* delivered to callers MCDI event queue.
*/
#define MC_CMD_DESC_PROXY_FUNC_COMMIT 0x175
+#define MC_CMD_DESC_PROXY_FUNC_COMMIT_MSGSET 0x175
#undef MC_CMD_0x175_PRIVILEGE_CTG
#define MC_CMD_0x175_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25518,6 +27906,7 @@
* cycle. Returns ENODEV if no function with given label exists.
*/
#define MC_CMD_DESC_PROXY_FUNC_OPEN 0x176
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_MSGSET 0x176
#undef MC_CMD_0x176_PRIVILEGE_CTG
#define MC_CMD_0x176_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25543,7 +27932,19 @@
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LEN 8
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LBN 32
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_WIDTH 32
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LBN 64
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_WIDTH 32
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_OFST 6
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_LEN 4
/* Function personality */
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_OFST 12
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4
@@ -25588,6 +27989,7 @@
* error (for virtio, DEVICE_NEEDS_RESET flag would be set on the host side)
*/
#define MC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1
+#define MC_CMD_DESC_PROXY_FUNC_CLOSE_MSGSET 0x1a1
#undef MC_CMD_0x1a1_PRIVILEGE_CTG
#define MC_CMD_0x1a1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25607,9 +28009,27 @@
#define DESC_PROXY_FUNC_MAP_FUNC_OFST 0
#define DESC_PROXY_FUNC_MAP_FUNC_LEN 8
#define DESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0
+#define DESC_PROXY_FUNC_MAP_FUNC_LO_LEN 4
+#define DESC_PROXY_FUNC_MAP_FUNC_LO_LBN 0
+#define DESC_PROXY_FUNC_MAP_FUNC_LO_WIDTH 32
#define DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4
+#define DESC_PROXY_FUNC_MAP_FUNC_HI_LEN 4
+#define DESC_PROXY_FUNC_MAP_FUNC_HI_LBN 32
+#define DESC_PROXY_FUNC_MAP_FUNC_HI_WIDTH 32
#define DESC_PROXY_FUNC_MAP_FUNC_LBN 0
#define DESC_PROXY_FUNC_MAP_FUNC_WIDTH 64
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_OFST 0
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_LEN 2
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_LBN 0
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_WIDTH 16
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_OFST 2
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_LEN 2
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_LBN 16
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_WIDTH 16
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_OFST 4
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_LEN 4
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_LBN 32
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_WIDTH 32
/* Function personality */
#define DESC_PROXY_FUNC_MAP_PERSONALITY_OFST 8
#define DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4
@@ -25631,6 +28051,7 @@
* Enumerate existing descriptor proxy functions
*/
#define MC_CMD_DESC_PROXY_FUNC_ENUM 0x177
+#define MC_CMD_DESC_PROXY_FUNC_ENUM_MSGSET 0x177
#undef MC_CMD_0x177_PRIVILEGE_CTG
#define MC_CMD_0x177_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25670,6 +28091,7 @@
* function.
*/
#define MC_CMD_DESC_PROXY_FUNC_ENABLE 0x178
+#define MC_CMD_DESC_PROXY_FUNC_ENABLE_MSGSET 0x178
#undef MC_CMD_0x178_PRIVILEGE_CTG
#define MC_CMD_0x178_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25702,6 +28124,7 @@
* Disable descriptor proxying for function
*/
#define MC_CMD_DESC_PROXY_FUNC_DISABLE 0x179
+#define MC_CMD_DESC_PROXY_FUNC_DISABLE_MSGSET 0x179
#undef MC_CMD_0x179_PRIVILEGE_CTG
#define MC_CMD_0x179_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25725,6 +28148,7 @@
* descriptors.
*/
#define MC_CMD_GET_ADDR_SPC_ID 0x1a0
+#define MC_CMD_GET_ADDR_SPC_ID_MSGSET 0x1a0
#undef MC_CMD_0x1a0_PRIVILEGE_CTG
#define MC_CMD_0x1a0_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25769,7 +28193,19 @@
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LEN 8
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LBN 32
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_WIDTH 32
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_OFST 8
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LBN 64
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_WIDTH 32
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_OFST 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_LEN 2
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_OFST 6
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_LEN 2
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_OFST 8
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_LEN 4
/* PASID value. Only valid if TYPE is PCI_FUNC_PASID. */
#define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_OFST 12
#define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4
@@ -25789,7 +28225,72 @@
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LEN 8
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LBN 0
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_WIDTH 32
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LBN 32
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_GET_CLIENT_HANDLE
+ * Obtain a handle for a client given a description of that client. N.B. this
+ * command is subject to change given the open discussion about how PCIe
+ * functions should be referenced on an iEP (integrated endpoint: functions
+ * span multiple buses) and multihost (multiple PCIe interfaces) system.
+ */
+#define MC_CMD_GET_CLIENT_HANDLE 0x1c3
+#define MC_CMD_GET_CLIENT_HANDLE_MSGSET 0x1c3
+#undef MC_CMD_0x1c3_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_CLIENT_HANDLE_IN msgrequest */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_LEN 12
+/* Type of client to get a client handle for */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_OFST 0
+#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_LEN 4
+/* enum: Obtain a client handle for a PCIe function-type client. */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC 0x0
+/* PCIe Function ID (as struct PCIE_FUNCTION). Valid when TYPE==FUNC. Use: -
+ * INTF=CALLER, PF=PF_NULL, VF=VF_NULL to refer to the calling function -
+ * INTF=CALLER, PF=PF_NULL, VF=... to refer to a VF child of the calling PF or
+ * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
+ * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
+ * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF
+ * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
+ * interface where ... refers to a small integer for the VF/PF fields, and to
+ * values from the PCIE_INTERFACE enum for for the INTF field. It's only
+ * meaningful to use INTF=CALLER within a structure that's an argument to
+ * MC_CMD_DEVEL_GET_CLIENT_HANDLE.
+ */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_OFST 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LEN 8
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_OFST 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LEN 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LBN 32
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_WIDTH 32
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_OFST 8
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LEN 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LBN 64
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_WIDTH 32
+/* enum: NULL value for the INTF field of struct PCIE_FUNCTION. Provided for
+ * backwards compatibility only, callers should use PCIE_INTERFACE_CALLER.
+ */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_LEN 2
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_OFST 6
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_LEN 2
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_OFST 8
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_LEN 4
+
+/* MC_CMD_GET_CLIENT_HANDLE_OUT msgresponse */
+#define MC_CMD_GET_CLIENT_HANDLE_OUT_LEN 4
+#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_OFST 0
+#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_LEN 4
/* MAE_FIELD_FLAGS structuredef */
#define MAE_FIELD_FLAGS_LEN 4
@@ -25937,6 +28438,40 @@
#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LEN 1
#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LBN 1096
#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_LBN 0
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_LBN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_LBN 2
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LBN 1104
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LBN 1104
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_LBN 0
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_LBN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_LBN 2
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LBN 1112
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LBN 1112
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_WIDTH 8
#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_OFST 140
#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4
#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LBN 1120
@@ -26623,9 +29158,24 @@
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_OFST 344
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_LBN 3
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_WIDTH 1
-#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_OFST 344
-#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_LBN 4
-#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_WIDTH 28
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_LBN 4
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_LBN 5
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_LBN 6
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_LBN 7
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_LBN 8
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_LBN 9
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_WIDTH 1
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LBN 2752
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_WIDTH 32
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST 348
@@ -26707,16 +29257,34 @@
#define MAE_MPORT_SELECTOR_TYPE_WIDTH 8
/* enum: The MPORT connected to a given physical port */
#define MAE_MPORT_SELECTOR_TYPE_PPORT 0x2
-/* enum: The MPORT assigned to a given PCIe function */
+/* enum: The MPORT assigned to a given PCIe function. Deprecated in favour of
+ * MH_FUNC.
+ */
#define MAE_MPORT_SELECTOR_TYPE_FUNC 0x3
/* enum: An mport_id */
#define MAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4
+/* enum: The MPORT assigned to a given PCIe function (see also FWRIVERHD-1108)
+ */
+#define MAE_MPORT_SELECTOR_TYPE_MH_FUNC 0x5
+/* enum: This is guaranteed never to be a valid selector type */
+#define MAE_MPORT_SELECTOR_TYPE_INVALID 0xff
#define MAE_MPORT_SELECTOR_MPORT_ID_OFST 0
#define MAE_MPORT_SELECTOR_MPORT_ID_LBN 0
#define MAE_MPORT_SELECTOR_MPORT_ID_WIDTH 24
#define MAE_MPORT_SELECTOR_PPORT_ID_OFST 0
#define MAE_MPORT_SELECTOR_PPORT_ID_LBN 0
#define MAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_OFST 0
+#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define MAE_MPORT_SELECTOR_HOST_PRIMARY 0x1 /* enum */
+#define MAE_MPORT_SELECTOR_NIC_EMBEDDED 0x2 /* enum */
+/* enum: Deprecated, use CALLER_INTF instead. */
+#define MAE_MPORT_SELECTOR_CALLER 0xf
+#define MAE_MPORT_SELECTOR_CALLER_INTF 0xf /* enum */
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_OFST 0
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_LBN 16
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_WIDTH 8
@@ -26737,15 +29305,56 @@
* function.
*/
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff
+/* enum: Same as PF_ID_CALLER, but for use in the smaller MH_PF_ID field. Only
+ * valid if FUNC_INTF_ID is CALLER.
+ */
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_CALLER 0xf
#define MAE_MPORT_SELECTOR_FLAT_LBN 0
#define MAE_MPORT_SELECTOR_FLAT_WIDTH 32
+/* MAE_LINK_ENDPOINT_SELECTOR structuredef: Structure that identifies a real or
+ * virtual network port by MAE port and link end
+ */
+#define MAE_LINK_ENDPOINT_SELECTOR_LEN 8
+/* The MAE MPORT of interest */
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_WIDTH 32
+/* Which end of the link identified by MPORT to consider */
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_OFST 4
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LEN 4
+/* Enum values, see field(s): */
+/* MAE_MPORT_END */
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LBN 32
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_WIDTH 32
+/* A field for accessing the endpoint selector as a collection of bits */
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_OFST 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LEN 8
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_OFST 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LEN 4
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LBN 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_WIDTH 32
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_OFST 4
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LEN 4
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LBN 32
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_WIDTH 32
+/* enum: Set FLAT to this value to obtain backward-compatible behaviour in
+ * commands that have been extended to take a MAE_LINK_ENDPOINT_SELECTOR
+ * argument. New commands that are designed to take such an argument from the
+ * start will not support this.
+ */
+#define MAE_LINK_ENDPOINT_SELECTOR_MAE_LINK_ENDPOINT_COMPAT 0x0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LBN 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_WIDTH 64
+
/***********************************/
/* MC_CMD_MAE_GET_CAPS
* Describes capabilities of the MAE (Match-Action Engine)
*/
#define MC_CMD_MAE_GET_CAPS 0x140
+#define MC_CMD_MAE_GET_CAPS_MSGSET 0x140
#undef MC_CMD_0x140_PRIVILEGE_CTG
#define MC_CMD_0x140_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -26772,6 +29381,9 @@
#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4
#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_LBN 2
#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
+#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_OFST 4
+#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_LBN 3
+#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
/* The total number of counters available to allocate. */
#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_OFST 8
#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4
@@ -26823,6 +29435,7 @@
* Get a level of support for match fields when used in match-action rules
*/
#define MC_CMD_MAE_GET_AR_CAPS 0x141
+#define MC_CMD_MAE_GET_AR_CAPS_MSGSET 0x141
#undef MC_CMD_0x141_PRIVILEGE_CTG
#define MC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26855,6 +29468,7 @@
* Get a level of support for fields used in outer rule keys.
*/
#define MC_CMD_MAE_GET_OR_CAPS 0x142
+#define MC_CMD_MAE_GET_OR_CAPS_MSGSET 0x142
#undef MC_CMD_0x142_PRIVILEGE_CTG
#define MC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26885,6 +29499,7 @@
* Rules.
*/
#define MC_CMD_MAE_COUNTER_ALLOC 0x143
+#define MC_CMD_MAE_COUNTER_ALLOC_MSGSET 0x143
#undef MC_CMD_0x143_PRIVILEGE_CTG
#define MC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26928,6 +29543,7 @@
* Free match-action-engine counters
*/
#define MC_CMD_MAE_COUNTER_FREE 0x144
+#define MC_CMD_MAE_COUNTER_FREE_MSGSET 0x144
#undef MC_CMD_0x144_PRIVILEGE_CTG
#define MC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26995,6 +29611,7 @@
* delivering packets to the current queue first.
*/
#define MC_CMD_MAE_COUNTERS_STREAM_START 0x151
+#define MC_CMD_MAE_COUNTERS_STREAM_START_MSGSET 0x151
#undef MC_CMD_0x151_PRIVILEGE_CTG
#define MC_CMD_0x151_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27031,6 +29648,7 @@
* Stop streaming counter values to the specified RxQ.
*/
#define MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152
+#define MC_CMD_MAE_COUNTERS_STREAM_STOP_MSGSET 0x152
#undef MC_CMD_0x152_PRIVILEGE_CTG
#define MC_CMD_0x152_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27060,6 +29678,7 @@
* MAE_COUNTERS_PACKETISER_STREAM_START/PACKET_SIZE and rung the doorbell.
*/
#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153
+#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_MSGSET 0x153
#undef MC_CMD_0x153_PRIVILEGE_CTG
#define MC_CMD_0x153_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27076,9 +29695,15 @@
/***********************************/
/* MC_CMD_MAE_ENCAP_HEADER_ALLOC
- * Allocate encap action metadata
+ * Allocate an encapsulation header to be used in an Action Rule response. The
+ * header must be constructed as a valid packet with 0-length payload.
+ * Specifically, the L3/L4 lengths & checksums will only be incrementally fixed
+ * by the NIC, rather than recomputed entirely. Currently only IPv4, IPv6 and
+ * UDP are supported. If the maximum number of headers have already been
+ * allocated then the command will fail with MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148
+#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_MSGSET 0x148
#undef MC_CMD_0x148_PRIVILEGE_CTG
#define MC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27109,9 +29734,10 @@
/***********************************/
/* MC_CMD_MAE_ENCAP_HEADER_UPDATE
- * Update encap action metadata
+ * Update encap action metadata. See comments for MAE_ENCAP_HEADER_ALLOC.
*/
#define MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149
+#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_MSGSET 0x149
#undef MC_CMD_0x149_PRIVILEGE_CTG
#define MC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27141,6 +29767,7 @@
* Free encap action metadata
*/
#define MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a
+#define MC_CMD_MAE_ENCAP_HEADER_FREE_MSGSET 0x14a
#undef MC_CMD_0x14a_PRIVILEGE_CTG
#define MC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27176,9 +29803,12 @@
/* MC_CMD_MAE_MAC_ADDR_ALLOC
* Allocate MAC address. Hardware implementations have MAC addresses programmed
* into an indirection table, and clients should take care not to allocate the
- * same MAC address twice (but instead reuse its ID).
+ * same MAC address twice (but instead reuse its ID). If the maximum number of
+ * MAC addresses have already been allocated then the command will fail with
+ * MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e
+#define MC_CMD_MAE_MAC_ADDR_ALLOC_MSGSET 0x15e
#undef MC_CMD_0x15e_PRIVILEGE_CTG
#define MC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27204,6 +29834,7 @@
* Free MAC address.
*/
#define MC_CMD_MAE_MAC_ADDR_FREE 0x15f
+#define MC_CMD_MAE_MAC_ADDR_FREE_MSGSET 0x15f
#undef MC_CMD_0x15f_PRIVILEGE_CTG
#define MC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27238,9 +29869,12 @@
/***********************************/
/* MC_CMD_MAE_ACTION_SET_ALLOC
* Allocate an action set, which can be referenced either in response to an
- * Action Rule, or as part of an Action Set List.
+ * Action Rule, or as part of an Action Set List. If the maxmimum number of
+ * action sets have already been allocated then the command will fail with
+ * MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ACTION_SET_ALLOC 0x14d
+#define MC_CMD_MAE_ACTION_SET_ALLOC_MSGSET 0x14d
#undef MC_CMD_0x14d_PRIVILEGE_CTG
#define MC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27267,6 +29901,15 @@
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_LBN 11
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_LBN 12
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_LBN 13
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_LBN 14
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_LEN 2
@@ -27313,8 +29956,135 @@
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_OFST 40
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4
+/* MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN msgrequest: Only supported if
+ * MAE_ACTION_SET_ALLOC_V2_SUPPORTED is advertised in
+ * MC_CMD_GET_CAPABILITIES_V7_OUT.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LEN 51
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_LEN 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_LBN 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_WIDTH 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_LBN 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_WIDTH 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_LBN 8
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_LBN 9
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_LBN 10
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_LBN 11
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_LBN 12
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_LBN 13
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_LBN 14
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
+/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_LEN 2
+/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_OFST 6
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_LEN 2
+/* If VLAN_PUSH == 2, inner TCI value to be inserted. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_OFST 8
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_LEN 2
+/* If VLAN_PUSH == 2, inner TPID value to be inserted. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_OFST 10
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_LEN 2
+/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_OFST 12
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_LEN 4
+/* Set to ENCAP_HEADER_ID_NULL to request no encap action */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_OFST 16
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_LEN 4
+/* An m-port selector identifying the m-port that the modified packet should be
+ * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the
+ * packet.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_OFST 20
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4
+/* Allows an action set to trigger several counter updates. Set to
+ * COUNTER_LIST_ID_NULL to request no counter action.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_OFST 24
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4
+/* If a driver only wished to update one counter within this action set, then
+ * it can supply a COUNTER_ID instead of allocating a single-element counter
+ * list. This field should be set to COUNTER_ID_NULL if this behaviour is not
+ * required. It is not valid to supply a non-NULL value for both
+ * COUNTER_LIST_ID and COUNTER_ID.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_OFST 28
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_OFST 32
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4
+/* Set to MAC_ID_NULL to request no source MAC replacement. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_OFST 36
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_LEN 4
+/* Set to MAC_ID_NULL to request no destination MAC replacement. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_OFST 40
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_LEN 4
+/* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_OFST 44
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_LEN 4
+/* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
+ * within IPv4 and IPv6 headers.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_LEN 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_LBN 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_LBN 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_LBN 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_LBN 3
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_WIDTH 6
+/* Actions for modifying the Explicit Congestion Notification (ECN) bits within
+ * IPv4 and IPv6 headers.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_LEN 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_LBN 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_LBN 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_LBN 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_LBN 3
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_WIDTH 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_LBN 5
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_LBN 6
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_WIDTH 1
+
/* MC_CMD_MAE_ACTION_SET_ALLOC_OUT msgresponse */
#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4
+/* The MSB of the AS_ID is guaranteed to be clear if the ID is not
+ * ACTION_SET_ID_NULL. This allows an AS_ID to be distinguished from an ASL_ID
+ * returned from MC_CMD_MAE_ACTION_SET_LIST_ALLOC.
+ */
#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0
#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4
/* enum: An action set ID that is guaranteed never to represent an action set
@@ -27326,6 +30096,7 @@
/* MC_CMD_MAE_ACTION_SET_FREE
*/
#define MC_CMD_MAE_ACTION_SET_FREE 0x14e
+#define MC_CMD_MAE_ACTION_SET_FREE_MSGSET 0x14e
#undef MC_CMD_0x14e_PRIVILEGE_CTG
#define MC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27361,9 +30132,12 @@
/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC
* Allocate an action set list (ASL) that can be referenced by an ID. The ASL
* ID can be used when inserting an action rule, so that for each packet
- * matching the rule every action set in the list is applied.
+ * matching the rule every action set in the list is applied. If the maximum
+ * number of ASLs have already been allocated then the command will fail with
+ * MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f
+#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_MSGSET 0x14f
#undef MC_CMD_0x14f_PRIVILEGE_CTG
#define MC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27394,6 +30168,9 @@
/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT msgresponse */
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4
+/* The MSB of the ASL_ID is guaranteed to be set. This allows an ASL_ID to be
+ * distinguished from an AS_ID returned from MC_CMD_MAE_ACTION_SET_ALLOC.
+ */
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4
/* enum: An action set list ID that is guaranteed never to represent an action
@@ -27407,6 +30184,7 @@
* Free match-action-engine redirect_lists
*/
#define MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150
+#define MC_CMD_MAE_ACTION_SET_LIST_FREE_MSGSET 0x150
#undef MC_CMD_0x150_PRIVILEGE_CTG
#define MC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27441,9 +30219,11 @@
/***********************************/
/* MC_CMD_MAE_OUTER_RULE_INSERT
* Inserts an Outer Rule, which controls encapsulation parsing, and may
- * influence the Lookup Sequence.
+ * influence the Lookup Sequence. If the maximum number of rules have already
+ * been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_OUTER_RULE_INSERT 0x15a
+#define MC_CMD_MAE_OUTER_RULE_INSERT_MSGSET 0x15a
#undef MC_CMD_0x15a_PRIVILEGE_CTG
#define MC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27504,6 +30284,7 @@
/* MC_CMD_MAE_OUTER_RULE_REMOVE
*/
#define MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b
+#define MC_CMD_MAE_OUTER_RULE_REMOVE_MSGSET 0x15b
#undef MC_CMD_0x15b_PRIVILEGE_CTG
#define MC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27583,9 +30364,11 @@
/* MC_CMD_MAE_ACTION_RULE_INSERT
* Insert a rule specify that packets matching a filter be processed according
* to a previous allocated action. Masks can be set as indicated by
- * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES.
+ * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES. If the maximum number of rules have
+ * already been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ACTION_RULE_INSERT 0x15c
+#define MC_CMD_MAE_ACTION_RULE_INSERT_MSGSET 0x15c
#undef MC_CMD_0x15c_PRIVILEGE_CTG
#define MC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27627,6 +30410,7 @@
* ENOTSUP, in which case the driver should DELETE/INSERT.
*/
#define MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d
+#define MC_CMD_MAE_ACTION_RULE_UPDATE_MSGSET 0x15d
#undef MC_CMD_0x15d_PRIVILEGE_CTG
#define MC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27648,6 +30432,7 @@
/* MC_CMD_MAE_ACTION_RULE_DELETE
*/
#define MC_CMD_MAE_ACTION_RULE_DELETE 0x155
+#define MC_CMD_MAE_ACTION_RULE_DELETE_MSGSET 0x155
#undef MC_CMD_0x155_PRIVILEGE_CTG
#define MC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27684,6 +30469,7 @@
* Return the m-port corresponding to a selector.
*/
#define MC_CMD_MAE_MPORT_LOOKUP 0x160
+#define MC_CMD_MAE_MPORT_LOOKUP_MSGSET 0x160
#undef MC_CMD_0x160_PRIVILEGE_CTG
#define MC_CMD_0x160_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -27705,6 +30491,7 @@
* match or delivery argument.
*/
#define MC_CMD_MAE_MPORT_ALLOC 0x163
+#define MC_CMD_MAE_MPORT_ALLOC_MSGSET 0x163
#undef MC_CMD_0x163_PRIVILEGE_CTG
#define MC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27812,6 +30599,7 @@
* Free a m-port which was previously allocated by the driver.
*/
#define MC_CMD_MAE_MPORT_FREE 0x164
+#define MC_CMD_MAE_MPORT_FREE_MSGSET 0x164
#undef MC_CMD_0x164_PRIVILEGE_CTG
#define MC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27847,6 +30635,9 @@
#define MAE_MPORT_DESC_CAN_DELETE_OFST 8
#define MAE_MPORT_DESC_CAN_DELETE_LBN 2
#define MAE_MPORT_DESC_CAN_DELETE_WIDTH 1
+#define MAE_MPORT_DESC_IS_ZOMBIE_OFST 8
+#define MAE_MPORT_DESC_IS_ZOMBIE_LBN 3
+#define MAE_MPORT_DESC_IS_ZOMBIE_WIDTH 1
#define MAE_MPORT_DESC_CALLER_FLAGS_LBN 64
#define MAE_MPORT_DESC_CALLER_FLAGS_WIDTH 32
/* Not the ideal name; it's really the type of thing connected to the m-port */
@@ -27869,7 +30660,13 @@
#define MAE_MPORT_DESC_RESERVED_OFST 32
#define MAE_MPORT_DESC_RESERVED_LEN 8
#define MAE_MPORT_DESC_RESERVED_LO_OFST 32
+#define MAE_MPORT_DESC_RESERVED_LO_LEN 4
+#define MAE_MPORT_DESC_RESERVED_LO_LBN 256
+#define MAE_MPORT_DESC_RESERVED_LO_WIDTH 32
#define MAE_MPORT_DESC_RESERVED_HI_OFST 36
+#define MAE_MPORT_DESC_RESERVED_HI_LEN 4
+#define MAE_MPORT_DESC_RESERVED_HI_LBN 288
+#define MAE_MPORT_DESC_RESERVED_HI_WIDTH 32
#define MAE_MPORT_DESC_RESERVED_LBN 256
#define MAE_MPORT_DESC_RESERVED_WIDTH 64
/* Logical port index. Only valid when type NET Port. */
@@ -27916,8 +30713,11 @@
/***********************************/
/* MC_CMD_MAE_MPORT_ENUMERATE
+ * Deprecated in favour of MAE_MPORT_READ_JOURNAL. Support for this command
+ * will be removed at some future point.
*/
#define MC_CMD_MAE_MPORT_ENUMERATE 0x17c
+#define MC_CMD_MAE_MPORT_ENUMERATE_MSGSET 0x17c
#undef MC_CMD_0x17c_PRIVILEGE_CTG
#define MC_CMD_0x17c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -27945,4 +30745,50 @@
#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM 244
#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1012
+
+/***********************************/
+/* MC_CMD_MAE_MPORT_READ_JOURNAL
+ * Firmware maintains a per-client journal of mport creations and deletions.
+ * This journal is clear-on-read, i.e. repeated calls of this command will
+ * drain the buffer. Whenever the caller resets its function via FLR or
+ * MC_CMD_ENTITY_RESET, the journal is regenerated from a blank start.
+ */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL 0x147
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_MSGSET 0x147
+#undef MC_CMD_0x147_PRIVILEGE_CTG
+
+#define MC_CMD_0x147_PRIVILEGE_CTG SRIOV_CTG_MAE
+
+/* MC_CMD_MAE_MPORT_READ_JOURNAL_IN msgrequest */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_LEN 4
+/* Any unused flags are reserved and must be set to zero. */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_OFST 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_LEN 4
+
+/* MC_CMD_MAE_MPORT_READ_JOURNAL_OUT msgresponse */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMIN 12
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX 252
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LEN(num) (12+1*(num))
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_NUM(len) (((len)-12)/1)
+/* Any unused flags are reserved and must be ignored. */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_OFST 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_LEN 4
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_OFST 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_LBN 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_WIDTH 1
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_OFST 4
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_LEN 4
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_OFST 8
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_LEN 4
+/* Any array of MAE_MPORT_DESC structures. The MAE_MPORT_DESC structure may
+ * grow in future version of this command. Drivers should use a stride of
+ * SIZEOF_MPORT_DESC. Fields beyond SIZEOF_MPORT_DESC are not present.
+ */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_OFST 12
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_LEN 1
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MINNUM 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM 240
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1008
+
#endif /* _SIENA_MC_DRIVER_PCOL_H */
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h
index f7c89fabc..c45f678c2 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h
@@ -6,7 +6,7 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
* rebuild this file with "make mcdi_headers_v5".
*/
@@ -20,6 +20,7 @@
* Perform an FC operation
*/
#define MC_CMD_FC 0x9
+#define MC_CMD_FC_MSGSET 0x9
/* MC_CMD_FC_IN msgrequest */
#define MC_CMD_FC_IN_LEN 4
@@ -212,7 +213,13 @@
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LEN 4
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LBN 128
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_WIDTH 32
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LEN 4
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LBN 160
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_WIDTH 32
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_OFST 24
@@ -784,12 +791,24 @@
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LBN 96
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LBN 128
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_WIDTH 32
/* AOE address from which to transfer data */
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LBN 160
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LBN 192
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_WIDTH 32
/* Length of AOE transfer (total) */
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4
@@ -916,7 +935,13 @@
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LEN 4
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LBN 96
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_WIDTH 32
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LEN 4
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LBN 128
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_WIDTH 32
#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4
@@ -1016,7 +1041,13 @@
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LEN 4
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LBN 96
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LEN 4
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LBN 128
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_WIDTH 32
/* Port number of PTP packet for which timestamp required */
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4
@@ -1320,7 +1351,13 @@
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LEN 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LBN 32
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_WIDTH 32
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LEN 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LBN 64
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_WIDTH 32
/* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */
#define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8
@@ -1347,7 +1384,13 @@
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS
#define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */
#define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */
@@ -1382,7 +1425,13 @@
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS
#define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */
#define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */
@@ -1415,7 +1464,13 @@
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK
/* MC_CMD_FC_OUT_MAC msgresponse */
@@ -1636,7 +1691,13 @@
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LBN 128
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_WIDTH 32
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LBN 160
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_WIDTH 32
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28
@@ -1976,12 +2037,24 @@
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LBN 64
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LBN 96
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_WIDTH 32
/* Length of address map */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LBN 128
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LBN 160
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_WIDTH 32
/* Component information field */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24
#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4
@@ -1989,7 +2062,13 @@
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LBN 224
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LBN 256
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_WIDTH 32
/* Name of the component */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36
#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1
@@ -2132,7 +2211,13 @@
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LBN 96
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LBN 128
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_WIDTH 32
/* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */
#define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)
@@ -2153,7 +2238,13 @@
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LBN 32
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LBN 64
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK
/* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */
@@ -2222,12 +2313,24 @@
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LBN 32
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LBN 64
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_WIDTH 32
/* AOE address from which to transfer data */
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LBN 96
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LBN 128
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_WIDTH 32
/* Length of AOE transfer (total) */
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4
@@ -2243,12 +2346,24 @@
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LBN 288
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LBN 320
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_WIDTH 32
/* When active, end read time */
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LBN 352
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LBN 384
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_WIDTH 32
/* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */
#define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0
@@ -2263,7 +2378,13 @@
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LEN 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LBN 32
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_WIDTH 32
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LEN 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LBN 64
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_WIDTH 32
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16
@@ -2311,7 +2432,13 @@
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LBN 0
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LBN 32
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_WIDTH 32
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127
@@ -2391,6 +2518,7 @@
* AOE operations on MC
*/
#define MC_CMD_AOE 0xa
+#define MC_CMD_AOE_MSGSET 0xa
/* MC_CMD_AOE_IN msgrequest */
#define MC_CMD_AOE_IN_LEN 4
@@ -2580,7 +2708,13 @@
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LEN 4
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LBN 64
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LEN 4
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LBN 96
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4
#define MC_CMD_AOE_IN_MAC_STATS_DMA_OFST 16
@@ -3024,7 +3158,13 @@
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
/* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h
index be570bc0a..e8fbb6f94 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h
@@ -6,7 +6,7 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
* rebuild this file with "make mcdi_headers_v5".
*
* The version of this file has MCDI strings really used in the libefx.
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v2 2/3] common/sfc_efx/base: add MAE VLAN presence match bits
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (4 preceding siblings ...)
2021-05-22 19:32 ` [dpdk-dev] [PATCH v2 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
@ 2021-05-22 19:32 ` Ivan Malov
2021-05-22 19:32 ` [dpdk-dev] [PATCH v2 3/3] net/sfc: support matching on VLAN presence in transfer rules Ivan Malov
` (5 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-22 19:32 UTC (permalink / raw)
To: dev
Cc: Ray Kinsella, Ferruh Yigit, Andrew Rybchenko, Andy Moreton, Neil Horman
Introduce necessary infrastructure for these fields to
be set, validated and compared during class comparison.
Enumeration and mappings envisaged are MCDI-compatible.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
---
drivers/common/sfc_efx/base/efx.h | 18 ++
drivers/common/sfc_efx/base/efx_impl.h | 3 +-
drivers/common/sfc_efx/base/efx_mae.c | 235 ++++++++++++++++++++++++-
drivers/common/sfc_efx/version.map | 1 +
4 files changed, 254 insertions(+), 3 deletions(-)
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 771fe5a17..8e13075b0 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -4103,6 +4103,10 @@ efx_mae_match_spec_fini(
__in efx_mae_match_spec_t *spec);
typedef enum efx_mae_field_id_e {
+ /*
+ * Fields which can be set by efx_mae_match_spec_field_set()
+ * or by using dedicated field-specific helper APIs.
+ */
EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
EFX_MAE_FIELD_ETHER_TYPE_BE,
EFX_MAE_FIELD_ETH_SADDR_BE,
@@ -4140,6 +4144,12 @@ typedef enum efx_mae_field_id_e {
EFX_MAE_FIELD_ENC_VNET_ID_BE,
EFX_MAE_FIELD_OUTER_RULE_ID,
+ /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
+ EFX_MAE_FIELD_HAS_OVLAN,
+ EFX_MAE_FIELD_HAS_IVLAN,
+ EFX_MAE_FIELD_ENC_HAS_OVLAN,
+ EFX_MAE_FIELD_ENC_HAS_IVLAN,
+
EFX_MAE_FIELD_NIDS
} efx_mae_field_id_t;
@@ -4198,6 +4208,14 @@ efx_mae_match_spec_field_set(
__in size_t mask_size,
__in_bcount(mask_size) const uint8_t *mask);
+/* The corresponding mask will be set to B_TRUE. */
+LIBEFX_API
+extern __checkReturn efx_rc_t
+efx_mae_match_spec_bit_set(
+ __in efx_mae_match_spec_t *spec,
+ __in efx_mae_field_id_t field_id,
+ __in boolean_t value);
+
/* If the mask argument is NULL, the API will use full mask by default. */
LIBEFX_API
extern __checkReturn efx_rc_t
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 4a513171a..8b63cfb37 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1720,7 +1720,8 @@ struct efx_mae_match_spec_s {
efx_mae_rule_type_t emms_type;
uint32_t emms_prio;
union emms_mask_value_pairs {
- uint8_t action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
+ uint8_t action[
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN];
uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN];
} emms_mask_value_pairs;
};
diff --git a/drivers/common/sfc_efx/base/efx_mae.c b/drivers/common/sfc_efx/base/efx_mae.c
index c1784211e..569748804 100644
--- a/drivers/common/sfc_efx/base/efx_mae.c
+++ b/drivers/common/sfc_efx/base/efx_mae.c
@@ -465,6 +465,10 @@ typedef enum efx_mae_field_cap_id_e {
EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
+ EFX_MAE_FIELD_ID_HAS_OVLAN = MAE_FIELD_HAS_OVLAN,
+ EFX_MAE_FIELD_ID_HAS_IVLAN = MAE_FIELD_HAS_IVLAN,
+ EFX_MAE_FIELD_ID_ENC_HAS_OVLAN = MAE_FIELD_ENC_HAS_OVLAN,
+ EFX_MAE_FIELD_ID_ENC_HAS_IVLAN = MAE_FIELD_ENC_HAS_IVLAN,
EFX_MAE_FIELD_CAP_NIDS
} efx_mae_field_cap_id_t;
@@ -591,6 +595,65 @@ static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
#undef EFX_MAE_MV_DESC_ALT
#undef EFX_MAE_MV_DESC
+};
+
+/*
+ * The following structure is a means to describe an MAE bit.
+ * The information in it is meant to be used internally by
+ * APIs for addressing a given flag in a mask-value pairs
+ * structure and for validation purposes.
+ */
+typedef struct efx_mae_mv_bit_desc_s {
+ /*
+ * Arrays using this struct are indexed by field IDs.
+ * Fields which aren't meant to be referenced by these
+ * arrays comprise gaps (invalid entries). Below field
+ * helps to identify such entries.
+ */
+ boolean_t emmbd_entry_is_valid;
+ efx_mae_field_cap_id_t emmbd_bit_cap_id;
+ size_t emmbd_value_ofst;
+ unsigned int emmbd_value_lbn;
+ size_t emmbd_mask_ofst;
+ unsigned int emmbd_mask_lbn;
+} efx_mae_mv_bit_desc_t;
+
+static const efx_mae_mv_bit_desc_t __efx_mae_outer_rule_mv_bit_desc_set[] = {
+#define EFX_MAE_MV_BIT_DESC(_name) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ B_TRUE, \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_LBN, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_LBN, \
+ }
+
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
+
+#undef EFX_MAE_MV_BIT_DESC
+};
+
+static const efx_mae_mv_bit_desc_t __efx_mae_action_rule_mv_bit_desc_set[] = {
+#define EFX_MAE_MV_BIT_DESC(_name) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ B_TRUE, \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
+ }
+
+ EFX_MAE_MV_BIT_DESC(HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(HAS_IVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
+
+#undef EFX_MAE_MV_BIT_DESC
};
__checkReturn efx_rc_t
@@ -789,6 +852,70 @@ efx_mae_match_spec_field_set(
EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mae_match_spec_bit_set(
+ __in efx_mae_match_spec_t *spec,
+ __in efx_mae_field_id_t field_id,
+ __in boolean_t value)
+{
+ const efx_mae_mv_bit_desc_t *bit_descp;
+ unsigned int bit_desc_set_nentries;
+ unsigned int byte_idx;
+ unsigned int bit_idx;
+ uint8_t *mvp;
+ efx_rc_t rc;
+
+ switch (spec->emms_type) {
+ case EFX_MAE_RULE_OUTER:
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
+ bit_descp = &__efx_mae_outer_rule_mv_bit_desc_set[field_id];
+ mvp = spec->emms_mask_value_pairs.outer;
+ break;
+ case EFX_MAE_RULE_ACTION:
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
+ bit_descp = &__efx_mae_action_rule_mv_bit_desc_set[field_id];
+ mvp = spec->emms_mask_value_pairs.action;
+ break;
+ default:
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if ((unsigned int)field_id >= bit_desc_set_nentries) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE) {
+ rc = EINVAL;
+ goto fail3;
+ }
+
+ byte_idx = bit_descp->emmbd_value_ofst + bit_descp->emmbd_value_lbn / 8;
+ bit_idx = bit_descp->emmbd_value_lbn % 8;
+
+ if (value != B_FALSE)
+ mvp[byte_idx] |= (1U << bit_idx);
+ else
+ mvp[byte_idx] &= ~(1U << bit_idx);
+
+ byte_idx = bit_descp->emmbd_mask_ofst + bit_descp->emmbd_mask_lbn / 8;
+ bit_idx = bit_descp->emmbd_mask_lbn % 8;
+ mvp[byte_idx] |= (1U << bit_idx);
+
+ return (0);
+
fail3:
EFSYS_PROBE(fail3);
fail2:
@@ -905,6 +1032,8 @@ efx_mae_match_spec_is_valid(
const efx_mae_field_cap_t *field_caps;
const efx_mae_mv_desc_t *desc_setp;
unsigned int desc_set_nentries;
+ const efx_mae_mv_bit_desc_t *bit_desc_setp;
+ unsigned int bit_desc_set_nentries;
boolean_t is_valid = B_TRUE;
efx_mae_field_id_t field_id;
const uint8_t *mvp;
@@ -915,6 +1044,9 @@ efx_mae_match_spec_is_valid(
desc_setp = __efx_mae_outer_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
mvp = spec->emms_mask_value_pairs.outer;
break;
case EFX_MAE_RULE_ACTION:
@@ -922,6 +1054,9 @@ efx_mae_match_spec_is_valid(
desc_setp = __efx_mae_action_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
mvp = spec->emms_mask_value_pairs.action;
break;
default:
@@ -989,6 +1124,48 @@ efx_mae_match_spec_is_valid(
break;
}
+ if (is_valid == B_FALSE)
+ return (B_FALSE);
+ }
+
+ for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
+ ++field_id) {
+ const efx_mae_mv_bit_desc_t *bit_descp =
+ &bit_desc_setp[field_id];
+ unsigned int byte_idx =
+ bit_descp->emmbd_mask_ofst +
+ bit_descp->emmbd_mask_lbn / 8;
+ unsigned int bit_idx =
+ bit_descp->emmbd_mask_lbn % 8;
+ efx_mae_field_cap_id_t bit_cap_id =
+ bit_descp->emmbd_bit_cap_id;
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE)
+ continue; /* Skip array gap */
+
+ if ((unsigned int)bit_cap_id >= field_ncaps) {
+ /* No capability for this bit = unsupported. */
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
+ if (is_valid == B_FALSE)
+ break;
+ else
+ continue;
+ }
+
+ switch (field_caps[bit_cap_id].emfc_support) {
+ case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
+ is_valid = B_TRUE;
+ break;
+ case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) != 0);
+ break;
+ case MAE_FIELD_SUPPORTED_MATCH_NEVER:
+ case MAE_FIELD_UNSUPPORTED:
+ default:
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
+ break;
+ }
+
if (is_valid == B_FALSE)
break;
}
@@ -1542,6 +1719,8 @@ efx_mae_match_specs_class_cmp(
const efx_mae_field_cap_t *field_caps;
const efx_mae_mv_desc_t *desc_setp;
unsigned int desc_set_nentries;
+ const efx_mae_mv_bit_desc_t *bit_desc_setp;
+ unsigned int bit_desc_set_nentries;
boolean_t have_same_class = B_TRUE;
efx_mae_field_id_t field_id;
const uint8_t *mvpl;
@@ -1554,6 +1733,9 @@ efx_mae_match_specs_class_cmp(
desc_setp = __efx_mae_outer_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
mvpl = left->emms_mask_value_pairs.outer;
mvpr = right->emms_mask_value_pairs.outer;
break;
@@ -1562,6 +1744,9 @@ efx_mae_match_specs_class_cmp(
desc_setp = __efx_mae_action_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
mvpl = left->emms_mask_value_pairs.action;
mvpr = right->emms_mask_value_pairs.action;
break;
@@ -1634,6 +1819,52 @@ efx_mae_match_specs_class_cmp(
}
}
+ if (have_same_class == B_FALSE)
+ goto done;
+
+ for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
+ ++field_id) {
+ const efx_mae_mv_bit_desc_t *bit_descp =
+ &bit_desc_setp[field_id];
+ efx_mae_field_cap_id_t bit_cap_id =
+ bit_descp->emmbd_bit_cap_id;
+ unsigned int byte_idx;
+ unsigned int bit_idx;
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE)
+ continue; /* Skip array gap */
+
+ if ((unsigned int)bit_cap_id >= field_ncaps)
+ break;
+
+ byte_idx =
+ bit_descp->emmbd_mask_ofst +
+ bit_descp->emmbd_mask_lbn / 8;
+ bit_idx =
+ bit_descp->emmbd_mask_lbn % 8;
+
+ if (field_caps[bit_cap_id].emfc_mask_affects_class &&
+ (mvpl[byte_idx] & (1U << bit_idx)) !=
+ (mvpr[byte_idx] & (1U << bit_idx))) {
+ have_same_class = B_FALSE;
+ break;
+ }
+
+ byte_idx =
+ bit_descp->emmbd_value_ofst +
+ bit_descp->emmbd_value_lbn / 8;
+ bit_idx =
+ bit_descp->emmbd_value_lbn % 8;
+
+ if (field_caps[bit_cap_id].emfc_match_affects_class &&
+ (mvpl[byte_idx] & (1U << bit_idx)) !=
+ (mvpr[byte_idx] & (1U << bit_idx))) {
+ have_same_class = B_FALSE;
+ break;
+ }
+ }
+
+done:
*have_same_classp = have_same_class;
return (0);
@@ -2282,10 +2513,10 @@ efx_mae_action_rule_insert(
* MCDI request and are thus safe to be copied directly to the buffer.
*/
EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
- MAE_FIELD_MASK_VALUE_PAIRS_LEN);
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
memcpy(payload + offset, spec->emms_mask_value_pairs.action,
- MAE_FIELD_MASK_VALUE_PAIRS_LEN);
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
efx_mcdi_execute(enp, &req);
diff --git a/drivers/common/sfc_efx/version.map b/drivers/common/sfc_efx/version.map
index 5e724fd10..75da5aa5c 100644
--- a/drivers/common/sfc_efx/version.map
+++ b/drivers/common/sfc_efx/version.map
@@ -106,6 +106,7 @@ INTERNAL {
efx_mae_fini;
efx_mae_get_limits;
efx_mae_init;
+ efx_mae_match_spec_bit_set;
efx_mae_match_spec_field_set;
efx_mae_match_spec_fini;
efx_mae_match_spec_init;
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v2 3/3] net/sfc: support matching on VLAN presence in transfer rules
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (5 preceding siblings ...)
2021-05-22 19:32 ` [dpdk-dev] [PATCH v2 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
@ 2021-05-22 19:32 ` Ivan Malov
2021-05-24 11:18 ` [dpdk-dev] [PATCH v3 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
` (4 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-22 19:32 UTC (permalink / raw)
To: dev; +Cc: Ray Kinsella, Ferruh Yigit, Andrew Rybchenko, Andy Moreton
Take into account VLAN presence fields in items ETH and VLAN.
Provided that the item ETH does not match on the EtherType,
the pattern behaviour will be as follows:
- ETH (mask->has_vlan = 0) | IPv4 = match both tagged and untagged;
- ETH (mask->has_vlan = 1) | IPv4 = match as per spec->has_vlan;
- ETH (mask->has_vlan = 0) | VLAN | IPv4 = match only tagged.
Similar logic applies to double tagging.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
---
drivers/net/sfc/sfc_mae.c | 124 ++++++++++++++++++++++++++++++++------
drivers/net/sfc/sfc_mae.h | 19 +++++-
2 files changed, 123 insertions(+), 20 deletions(-)
diff --git a/drivers/net/sfc/sfc_mae.c b/drivers/net/sfc/sfc_mae.c
index a2c0aa143..33bff275c 100644
--- a/drivers/net/sfc/sfc_mae.c
+++ b/drivers/net/sfc/sfc_mae.c
@@ -728,6 +728,7 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
RTE_BE16(RTE_ETHER_TYPE_QINQ2),
RTE_BE16(RTE_ETHER_TYPE_QINQ3),
};
+ bool enforce_tag_presence[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {0};
unsigned int nb_supported_tpids = RTE_DIM(supported_tpids);
unsigned int ethertype_idx;
const uint8_t *valuep;
@@ -753,6 +754,22 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
ethertype_idx < pdata->nb_vlan_tags; ++ethertype_idx) {
unsigned int tpid_idx;
+ /*
+ * This loop can have only two iterations. On the second one,
+ * drop outer tag presence enforcement bit because the inner
+ * tag presence automatically assumes that for the outer tag.
+ */
+ enforce_tag_presence[0] = B_FALSE;
+
+ if (ethertypes[ethertype_idx].mask == RTE_BE16(0)) {
+ if (pdata->tci_masks[ethertype_idx] == RTE_BE16(0))
+ enforce_tag_presence[ethertype_idx] = B_TRUE;
+
+ /* No match on this field, and no value check. */
+ nb_supported_tpids = 1;
+ continue;
+ }
+
/* Exact match is supported only. */
if (ethertypes[ethertype_idx].mask != RTE_BE16(0xffff)) {
rc = EINVAL;
@@ -812,6 +829,24 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
}
}
+ if (enforce_tag_presence[0] || pdata->has_ovlan_mask) {
+ rc = efx_mae_match_spec_bit_set(ctx->match_spec,
+ fremap[EFX_MAE_FIELD_HAS_OVLAN],
+ enforce_tag_presence[0] ||
+ pdata->has_ovlan_value);
+ if (rc != 0)
+ goto fail;
+ }
+
+ if (enforce_tag_presence[1] || pdata->has_ivlan_mask) {
+ rc = efx_mae_match_spec_bit_set(ctx->match_spec,
+ fremap[EFX_MAE_FIELD_HAS_IVLAN],
+ enforce_tag_presence[1] ||
+ pdata->has_ivlan_value);
+ if (rc != 0)
+ goto fail;
+ }
+
valuep = (const uint8_t *)&pdata->l3_next_proto_value;
maskp = (const uint8_t *)&pdata->l3_next_proto_mask;
rc = efx_mae_match_spec_field_set(ctx->match_spec,
@@ -1154,6 +1189,7 @@ sfc_mae_rule_parse_item_eth(const struct rte_flow_item *item,
sfc_mae_item_build_supp_mask(flocs_eth, RTE_DIM(flocs_eth),
&supp_mask, sizeof(supp_mask));
+ supp_mask.has_vlan = 1;
rc = sfc_flow_parse_init(item,
(const void **)&spec, (const void **)&mask,
@@ -1172,14 +1208,23 @@ sfc_mae_rule_parse_item_eth(const struct rte_flow_item *item,
item_spec = (const struct rte_flow_item_eth *)spec;
item_mask = (const struct rte_flow_item_eth *)mask;
+ /*
+ * Remember various match criteria in the parsing context.
+ * sfc_mae_rule_process_pattern_data() will consider them
+ * altogether when the rest of the items have been parsed.
+ */
ethertypes[0].value = item_spec->type;
ethertypes[0].mask = item_mask->type;
+ if (item_mask->has_vlan) {
+ pdata->has_ovlan_mask = B_TRUE;
+ if (item_spec->has_vlan)
+ pdata->has_ovlan_value = B_TRUE;
+ }
} else {
/*
- * The specification is empty. This is wrong in the case
- * when there are more network patterns in line. Other
- * than that, any Ethernet can match. All of that is
- * checked at the end of parsing.
+ * The specification is empty. The overall pattern
+ * validity will be enforced at the end of parsing.
+ * See sfc_mae_rule_process_pattern_data().
*/
return 0;
}
@@ -1229,6 +1274,16 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
{
struct sfc_mae_parse_ctx *ctx_mae = ctx->mae;
struct sfc_mae_pattern_data *pdata = &ctx_mae->pattern_data;
+ boolean_t *has_vlan_mp_by_nb_tags[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {
+ &pdata->has_ovlan_mask,
+ &pdata->has_ivlan_mask,
+ };
+ boolean_t *has_vlan_vp_by_nb_tags[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {
+ &pdata->has_ovlan_value,
+ &pdata->has_ivlan_value,
+ };
+ boolean_t *cur_tag_presence_bit_mp;
+ boolean_t *cur_tag_presence_bit_vp;
const struct sfc_mae_field_locator *flocs;
struct rte_flow_item_vlan supp_mask;
const uint8_t *spec = NULL;
@@ -1244,14 +1299,27 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
"Can't match that many VLAN tags");
}
+ cur_tag_presence_bit_mp = has_vlan_mp_by_nb_tags[pdata->nb_vlan_tags];
+ cur_tag_presence_bit_vp = has_vlan_vp_by_nb_tags[pdata->nb_vlan_tags];
+
+ if (*cur_tag_presence_bit_mp == B_TRUE &&
+ *cur_tag_presence_bit_vp == B_FALSE) {
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "The previous item enforces no (more) VLAN, "
+ "so the current item (VLAN) must not exist");
+ }
+
nb_flocs = RTE_DIM(flocs_vlan) / SFC_MAE_MATCH_VLAN_MAX_NTAGS;
flocs = flocs_vlan + pdata->nb_vlan_tags * nb_flocs;
- /* If parsing fails, this can remain incremented. */
- ++pdata->nb_vlan_tags;
-
sfc_mae_item_build_supp_mask(flocs, nb_flocs,
&supp_mask, sizeof(supp_mask));
+ /*
+ * This only means that the field is supported by the driver and libefx.
+ * Support on NIC level will be checked when all items have been parsed.
+ */
+ supp_mask.has_more_vlan = 1;
rc = sfc_flow_parse_init(item,
(const void **)&spec, (const void **)&mask,
@@ -1262,26 +1330,44 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
return rc;
if (spec != NULL) {
- struct sfc_mae_ethertype *ethertypes = pdata->ethertypes;
+ struct sfc_mae_ethertype *et = pdata->ethertypes;
const struct rte_flow_item_vlan *item_spec;
const struct rte_flow_item_vlan *item_mask;
item_spec = (const struct rte_flow_item_vlan *)spec;
item_mask = (const struct rte_flow_item_vlan *)mask;
- ethertypes[pdata->nb_vlan_tags].value = item_spec->inner_type;
- ethertypes[pdata->nb_vlan_tags].mask = item_mask->inner_type;
- } else {
/*
- * The specification is empty. This is wrong in the case
- * when there are more network patterns in line. Other
- * than that, any Ethernet can match. All of that is
- * checked at the end of parsing.
+ * Remember various match criteria in the parsing context.
+ * sfc_mae_rule_process_pattern_data() will consider them
+ * altogether when the rest of the items have been parsed.
*/
- return 0;
+ et[pdata->nb_vlan_tags + 1].value = item_spec->inner_type;
+ et[pdata->nb_vlan_tags + 1].mask = item_mask->inner_type;
+ pdata->tci_masks[pdata->nb_vlan_tags] = item_mask->tci;
+ if (item_mask->has_more_vlan) {
+ if (pdata->nb_vlan_tags ==
+ SFC_MAE_MATCH_VLAN_MAX_NTAGS) {
+ return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "Can't use 'has_more_vlan' in "
+ "the second item VLAN");
+ }
+ pdata->has_ivlan_mask = B_TRUE;
+ if (item_spec->has_more_vlan)
+ pdata->has_ivlan_value = B_TRUE;
+ }
+
+ /* Convert TCI to MAE representation right now. */
+ rc = sfc_mae_parse_item(flocs, nb_flocs, spec, mask,
+ ctx_mae, error);
+ if (rc != 0)
+ return rc;
}
- return sfc_mae_parse_item(flocs, nb_flocs, spec, mask, ctx_mae, error);
+ ++(pdata->nb_vlan_tags);
+
+ return 0;
}
static const struct sfc_mae_field_locator flocs_ipv4[] = {
@@ -1612,6 +1698,8 @@ static const efx_mae_field_id_t field_ids_no_remap[] = {
FIELD_ID_NO_REMAP(L4_SPORT_BE),
FIELD_ID_NO_REMAP(L4_DPORT_BE),
FIELD_ID_NO_REMAP(TCP_FLAGS_BE),
+ FIELD_ID_NO_REMAP(HAS_OVLAN),
+ FIELD_ID_NO_REMAP(HAS_IVLAN),
#undef FIELD_ID_NO_REMAP
};
@@ -1642,6 +1730,8 @@ static const efx_mae_field_id_t field_ids_remap_to_encap[] = {
FIELD_ID_REMAP_TO_ENCAP(DST_IP6_BE),
FIELD_ID_REMAP_TO_ENCAP(L4_SPORT_BE),
FIELD_ID_REMAP_TO_ENCAP(L4_DPORT_BE),
+ FIELD_ID_REMAP_TO_ENCAP(HAS_OVLAN),
+ FIELD_ID_REMAP_TO_ENCAP(HAS_IVLAN),
#undef FIELD_ID_REMAP_TO_ENCAP
};
diff --git a/drivers/net/sfc/sfc_mae.h b/drivers/net/sfc/sfc_mae.h
index 9740e54e4..0241fe33c 100644
--- a/drivers/net/sfc/sfc_mae.h
+++ b/drivers/net/sfc/sfc_mae.h
@@ -130,12 +130,14 @@ struct sfc_mae_pattern_data {
*
* - If an item ETH is followed by a single item VLAN,
* the former must have "type" set to one of supported
- * TPID values (0x8100, 0x88a8, 0x9100, 0x9200, 0x9300).
+ * TPID values (0x8100, 0x88a8, 0x9100, 0x9200, 0x9300),
+ * or 0x0000/0x0000.
*
* - If an item ETH is followed by two items VLAN, the
* item ETH must have "type" set to one of supported TPID
- * values (0x88a8, 0x9100, 0x9200, 0x9300), and the outermost
- * VLAN item must have "inner_type" set to TPID value 0x8100.
+ * values (0x88a8, 0x9100, 0x9200, 0x9300), or 0x0000/0x0000,
+ * and the outermost VLAN item must have "inner_type" set
+ * to TPID value 0x8100, or 0x0000/0x0000
*
* - If a L2 item is followed by a L3 one, the former must
* indicate "type" ("inner_type") which corresponds to
@@ -156,6 +158,9 @@ struct sfc_mae_pattern_data {
* VLAN (L3 EtherType) --> ETHER_TYPE_BE
*/
struct sfc_mae_ethertype ethertypes[SFC_MAE_L2_MAX_NITEMS];
+
+ rte_be16_t tci_masks[SFC_MAE_MATCH_VLAN_MAX_NTAGS];
+
unsigned int nb_vlan_tags;
/**
@@ -191,6 +196,14 @@ struct sfc_mae_pattern_data {
*/
uint8_t l3_next_proto_restriction_value;
uint8_t l3_next_proto_restriction_mask;
+
+ /* Projected state of EFX_MAE_FIELD_HAS_OVLAN match bit */
+ bool has_ovlan_value;
+ bool has_ovlan_mask;
+
+ /* Projected state of EFX_MAE_FIELD_HAS_IVLAN match bit */
+ bool has_ivlan_value;
+ bool has_ivlan_mask;
};
struct sfc_mae_parse_ctx {
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v3 0/3] Match On VLAN Presence In Transfer Flows
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (6 preceding siblings ...)
2021-05-22 19:32 ` [dpdk-dev] [PATCH v2 3/3] net/sfc: support matching on VLAN presence in transfer rules Ivan Malov
@ 2021-05-24 11:18 ` Ivan Malov
2021-05-24 11:18 ` [dpdk-dev] [PATCH v3 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (3 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-24 11:18 UTC (permalink / raw)
To: dev; +Cc: Ray Kinsella, Ferruh Yigit
Changes in v2:
* [1/3] no longer triggers spelling warnings
Changes in v3:
* Attempt to correct mailing order of the patches
Andrew Rybchenko (1):
common/sfc_efx/base: update MCDI headers
Ivan Malov (2):
common/sfc_efx/base: add MAE VLAN presence match bits
net/sfc: support matching on VLAN presence in transfer rules
drivers/common/sfc_efx/base/efx.h | 18 +
drivers/common/sfc_efx/base/efx_impl.h | 3 +-
drivers/common/sfc_efx/base/efx_mae.c | 235 +-
drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3532 +++++++++++++++--
.../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
.../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
drivers/common/sfc_efx/version.map | 1 +
drivers/net/sfc/sfc_mae.c | 124 +-
drivers/net/sfc/sfc_mae.h | 19 +-
9 files changed, 3708 insertions(+), 368 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v3 1/3] common/sfc_efx/base: update MCDI headers
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (7 preceding siblings ...)
2021-05-24 11:18 ` [dpdk-dev] [PATCH v3 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
@ 2021-05-24 11:18 ` Ivan Malov
2021-05-24 11:18 ` [dpdk-dev] [PATCH v3 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
` (2 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-24 11:18 UTC (permalink / raw)
To: dev; +Cc: Andrew Rybchenko, Ray Kinsella, Ferruh Yigit
From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
---
drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3532 +++++++++++++++--
.../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
.../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
3 files changed, 3331 insertions(+), 345 deletions(-)
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
index 976db37d6..a3c9f076e 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
@@ -6,7 +6,7 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
* rebuild this file with "make mcdi_headers_v5".
*/
@@ -410,6 +410,48 @@
#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */
+/* MC_CMD_FPGA_FLASH_INDEX enum */
+#define MC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */
+#define MC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */
+
+/* MC_CMD_EXTERNAL_MAE_LINK_MODE enum */
+/* enum: Legacy mode as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0
+/* enum: Switchdev mode as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1
+/* enum: Bootstrap mode as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2
+/* enum: Link-mode change is in-progress as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf
+
+/* PCIE_INTERFACE enum: From EF100 onwards, SFC products can have multiple PCIe
+ * interfaces. There is a need to refer to interfaces explicitly from drivers
+ * (for example, a management driver on one interface administering a function
+ * on another interface). This enumeration provides stable identifiers to all
+ * interfaces present on a product. Product documentation will specify which
+ * interfaces exist and their associated identifier. In general, drivers,
+ * should not assign special meanings to specific values. Instead, behaviour
+ * should be determined by NIC configuration, which will identify interfaces
+ * where appropriate.
+ */
+/* enum: Primary host interfaces. Typically (i.e. for all known SFC products)
+ * the interface exposed on the edge connector (or form factor equivalent).
+ */
+#define PCIE_INTERFACE_HOST_PRIMARY 0x0
+/* enum: Riverhead and keystone products have a second PCIe interface to which
+ * an on-NIC ARM module is expected to be connected.
+ */
+#define PCIE_INTERFACE_NIC_EMBEDDED 0x1
+/* enum: For MCDI commands issued over a PCIe interface, this value is
+ * translated into the interface over which the command was issued. Not
+ * meaningful for other MCDI transports.
+ */
+#define PCIE_INTERFACE_CALLER 0xffffffff
+
+/* MC_CLIENT_ID_SPECIFIER enum */
+/* enum: Equivalent to the caller's client ID */
+#define MC_CMD_CLIENT_ID_SELF 0xffffffff
+
/* MAE_FIELD_SUPPORT_STATUS enum */
/* enum: The NIC does not support this field. The driver must ensure that any
* mask associated with this field in a match rule is zeroed. The NIC may
@@ -470,6 +512,20 @@
#define MAE_FIELD_CT_PRIVATE_FLAGS 0x8
/* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
#define MAE_FIELD_IS_FROM_NETWORK 0x9
+/* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
+#define MAE_FIELD_HAS_OVLAN 0xa
+/* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
+#define MAE_FIELD_HAS_IVLAN 0xb
+/* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
+ * when encap
+ */
+#define MAE_FIELD_ENC_HAS_OVLAN 0xc
+/* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
+ * when encap
+ */
+#define MAE_FIELD_ENC_HAS_IVLAN 0xd
+/* enum: Packet is IP fragment */
+#define MAE_FIELD_ENC_IP_FRAG 0xe
#define MAE_FIELD_ETHER_TYPE 0x21 /* enum */
#define MAE_FIELD_VLAN0_TCI 0x22 /* enum */
#define MAE_FIELD_VLAN0_PROTO 0x23 /* enum */
@@ -508,6 +564,10 @@
#define MAE_FIELD_L4_DPORT 0x33
/* enum: Inner when encap */
#define MAE_FIELD_TCP_FLAGS 0x34
+/* enum: TCP packet with any of SYN, FIN or RST flag set */
+#define MAE_FIELD_TCP_SYN_FIN_RST 0x35
+/* enum: Packet is IP fragment with fragment offset 0 */
+#define MAE_FIELD_IP_FIRST_FRAG 0x36
/* enum: The type of encapsulated used for this packet. Value as per
* ENCAP_TYPE_*.
*/
@@ -550,8 +610,8 @@
#define MAE_FIELD_ENC_L4_SPORT 0x52
/* enum: Outer; only present when encap */
#define MAE_FIELD_ENC_L4_DPORT 0x53
-/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Outer; only present when
- * encap
+/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Bottom 24 bits of Key
+ * (when L2GRE) Outer; only present when encap
*/
#define MAE_FIELD_ENC_VNET_ID 0x54
@@ -566,6 +626,14 @@
#define MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */
#define MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */
+/* MAE_MPORT_END enum: Selects which end of the logical link identified by an
+ * MPORT_SELECTOR is targeted by an operation.
+ */
+/* enum: Selects the port on the MAE virtual switch */
+#define MAE_MPORT_END_MAE 0x1
+/* enum: Selects the virtual NIC plugged into the MAE switch */
+#define MAE_MPORT_END_VNIC 0x2
+
/* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF100
* platforms
*/
@@ -647,17 +715,21 @@
#define MCDI_EVENT_TX_ERR_TYPE_OFST 0
#define MCDI_EVENT_TX_ERR_TYPE_LBN 12
#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
-/* enum: Descriptor loader reported failure */
+/* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */
#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
-/* enum: Descriptor ring empty and no EOP seen for packet */
+/* enum: Descriptor ring empty and no EOP seen for packet. Specific to
+ * EF10-family NICs
+ */
#define MCDI_EVENT_TX_ERR_NO_EOP 0x2
-/* enum: Overlength packet */
+/* enum: Overlength packet. Specific to EF10-family NICs. */
#define MCDI_EVENT_TX_ERR_2BIG 0x3
-/* enum: Malformed option descriptor */
+/* enum: Malformed option descriptor. Specific to EF10-family NICs. */
#define MCDI_EVENT_TX_BAD_OPTDESC 0x5
-/* enum: Option descriptor part way through a packet */
+/* enum: Option descriptor part way through a packet. Specific to EF10-family
+ * NICs.
+ */
#define MCDI_EVENT_TX_OPT_IN_PKT 0x8
-/* enum: DMA or PIO data access error */
+/* enum: DMA or PIO data access error. Specific to EF10-family NICs */
#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
#define MCDI_EVENT_TX_ERR_INFO_OFST 0
#define MCDI_EVENT_TX_ERR_INFO_LBN 16
@@ -1270,7 +1342,13 @@
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 4
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LBN 64
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_WIDTH 32
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 4
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LBN 96
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_WIDTH 32
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126
@@ -1384,6 +1462,7 @@
* has additional checks to reject insecure calls.
*/
#define MC_CMD_READ32 0x1
+#define MC_CMD_READ32_MSGSET 0x1
#undef MC_CMD_0x1_PRIVILEGE_CTG
#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -1413,6 +1492,7 @@
* Write multiple 32byte words to MC memory.
*/
#define MC_CMD_WRITE32 0x2
+#define MC_CMD_WRITE32_MSGSET 0x2
#undef MC_CMD_0x2_PRIVILEGE_CTG
#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -1442,6 +1522,7 @@
* has additional checks to reject insecure calls.
*/
#define MC_CMD_COPYCODE 0x3
+#define MC_CMD_COPYCODE_MSGSET 0x3
#undef MC_CMD_0x3_PRIVILEGE_CTG
#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -1505,6 +1586,7 @@
* Select function for function-specific commands.
*/
#define MC_CMD_SET_FUNC 0x4
+#define MC_CMD_SET_FUNC_MSGSET 0x4
#undef MC_CMD_0x4_PRIVILEGE_CTG
#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -1524,6 +1606,7 @@
* Get the instruction address from which the MC booted.
*/
#define MC_CMD_GET_BOOT_STATUS 0x5
+#define MC_CMD_GET_BOOT_STATUS_MSGSET 0x5
#undef MC_CMD_0x5_PRIVILEGE_CTG
#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -1558,6 +1641,7 @@
* fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
*/
#define MC_CMD_GET_ASSERTS 0x6
+#define MC_CMD_GET_ASSERTS_MSGSET 0x6
#undef MC_CMD_0x6_PRIVILEGE_CTG
#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -1682,12 +1766,24 @@
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LBN 2080
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_WIDTH 32
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LBN 2112
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_WIDTH 32
/* MC firmware version number */
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LBN 2144
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_WIDTH 32
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LBN 2176
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_WIDTH 32
/* MC firmware security level */
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
@@ -1705,6 +1801,7 @@
* sensor notifications and MCDI completions
*/
#define MC_CMD_LOG_CTRL 0x7
+#define MC_CMD_LOG_CTRL_MSGSET 0x7
#undef MC_CMD_0x7_PRIVILEGE_CTG
#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -1731,6 +1828,7 @@
* Get version information about adapter components.
*/
#define MC_CMD_GET_VERSION 0x8
+#define MC_CMD_GET_VERSION_MSGSET 0x8
#undef MC_CMD_0x8_PRIVILEGE_CTG
#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -1771,7 +1869,13 @@
#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_OUT_VERSION_LO_WIDTH 32
#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_OUT_VERSION_HI_WIDTH 32
/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
@@ -1787,7 +1891,13 @@
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_WIDTH 32
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
@@ -1811,7 +1921,13 @@
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_WIDTH 32
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32
#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16
@@ -1833,6 +1949,33 @@
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
/* MC firmware unique build ID (as binary SHA-1 value) */
#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52
#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20
@@ -1850,7 +1993,13 @@
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
/* The ID of the SUC chip. This is specific to the platform but typically
* indicates family, memory sizes etc. See SF-116728-SW for further details.
*/
@@ -1864,7 +2013,13 @@
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
/* FPGA version as three numbers. On Riverhead based systems this field uses
* the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
* FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
@@ -1886,12 +2041,496 @@
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64
+/* MC_CMD_GET_VERSION_V3_OUT msgresponse: Extended response providing version
+ * information for all adapter components. For Riverhead based designs, base MC
+ * firmware version fields refer to NMC firmware, while CMC firmware data is in
+ * dedicated CMC fields. Flags indicate which data is present in the response
+ * (depending on which components exist on a particular adapter)
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_LEN 328
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_WIDTH 32
+/* extra info */
+#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_LEN 64
+/* The version of the datapath hardware design as three number - a.b.c */
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_OFST 304
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_NUM 3
+/* The version of the firmware library used to control the datapath as three
+ * number - a.b.c
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_OFST 316
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_NUM 3
+
+/* MC_CMD_GET_VERSION_V4_OUT msgresponse: Extended response providing SoC
+ * version information
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_LEN 392
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_WIDTH 32
+/* extra info */
+#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_LEN 64
+/* The version of the datapath hardware design as three number - a.b.c */
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_OFST 304
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_NUM 3
+/* The version of the firmware library used to control the datapath as three
+ * number - a.b.c
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_OFST 316
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_NUM 3
+/* The SOC boot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_OFST 328
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4
+/* The SOC uboot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_OFST 344
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4
+/* The SOC main rootfs version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
+/* The SOC recovery buildroot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
+
+/* MC_CMD_GET_VERSION_V5_OUT msgresponse: Extended response providing bundle
+ * and board version information
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_LEN 424
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_WIDTH 32
+/* extra info */
+#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_LEN 64
+/* The version of the datapath hardware design as three number - a.b.c */
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_OFST 304
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_NUM 3
+/* The version of the firmware library used to control the datapath as three
+ * number - a.b.c
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_OFST 316
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_NUM 3
+/* The SOC boot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_OFST 328
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4
+/* The SOC uboot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_OFST 344
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4
+/* The SOC main rootfs version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
+/* The SOC recovery buildroot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
+/* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
+ * BOARD_REVISION field
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_OFST 392
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4
+/* Bundle version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_OFST 408
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4
+
/***********************************/
/* MC_CMD_PTP
* Perform PTP operation
*/
#define MC_CMD_PTP 0xb
+#define MC_CMD_PTP_MSGSET 0xb
#undef MC_CMD_0xb_PRIVILEGE_CTG
#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -2066,7 +2705,13 @@
#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
+#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LBN 64
+#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_WIDTH 32
#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
+#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LBN 96
+#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_WIDTH 32
/* enum: Number of fractional bits in frequency adjustment */
#define MC_CMD_PTP_IN_ADJUST_BITS 0x28
/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
@@ -2097,7 +2742,13 @@
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LBN 64
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_WIDTH 32
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LBN 96
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_WIDTH 32
/* enum: Number of fractional bits in frequency adjustment */
/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
@@ -2136,7 +2787,13 @@
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LBN 96
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_WIDTH 32
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LBN 128
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_WIDTH 32
/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
@@ -2252,7 +2909,13 @@
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LBN 64
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_WIDTH 32
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LBN 96
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_WIDTH 32
/* Enum values, see field(s): */
/* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */
@@ -2283,7 +2946,13 @@
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LBN 96
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_WIDTH 32
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LBN 128
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_WIDTH 32
/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
@@ -2745,6 +3414,7 @@
* Read 32bit words from the indirect memory map.
*/
#define MC_CMD_CSR_READ32 0xc
+#define MC_CMD_CSR_READ32_MSGSET 0xc
#undef MC_CMD_0xc_PRIVILEGE_CTG
#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -2778,6 +3448,7 @@
* Write 32bit dwords to the indirect memory map.
*/
#define MC_CMD_CSR_WRITE32 0xd
+#define MC_CMD_CSR_WRITE32_MSGSET 0xd
#undef MC_CMD_0xd_PRIVILEGE_CTG
#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -2811,6 +3482,7 @@
* MCDI command to avoid creating too many MCDI commands.
*/
#define MC_CMD_HP 0x54
+#define MC_CMD_HP_MSGSET 0x54
#undef MC_CMD_0x54_PRIVILEGE_CTG
#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -2834,7 +3506,13 @@
#define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
#define MC_CMD_HP_IN_OCSD_ADDR_LEN 8
#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
+#define MC_CMD_HP_IN_OCSD_ADDR_LO_LEN 4
+#define MC_CMD_HP_IN_OCSD_ADDR_LO_LBN 32
+#define MC_CMD_HP_IN_OCSD_ADDR_LO_WIDTH 32
#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
+#define MC_CMD_HP_IN_OCSD_ADDR_HI_LEN 4
+#define MC_CMD_HP_IN_OCSD_ADDR_HI_LBN 64
+#define MC_CMD_HP_IN_OCSD_ADDR_HI_WIDTH 32
/* The requested update interval, in seconds. (Or the sub-command if ADDR is
* NULL.)
*/
@@ -2858,6 +3536,7 @@
* Get stack information.
*/
#define MC_CMD_STACKINFO 0xf
+#define MC_CMD_STACKINFO_MSGSET 0xf
#undef MC_CMD_0xf_PRIVILEGE_CTG
#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -2884,6 +3563,7 @@
* MDIO register read.
*/
#define MC_CMD_MDIO_READ 0x10
+#define MC_CMD_MDIO_READ_MSGSET 0x10
#undef MC_CMD_0x10_PRIVILEGE_CTG
#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -2932,6 +3612,7 @@
* MDIO register write.
*/
#define MC_CMD_MDIO_WRITE 0x11
+#define MC_CMD_MDIO_WRITE_MSGSET 0x11
#undef MC_CMD_0x11_PRIVILEGE_CTG
#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -2980,6 +3661,7 @@
* Write DBI register(s).
*/
#define MC_CMD_DBI_WRITE 0x12
+#define MC_CMD_DBI_WRITE_MSGSET 0x12
#undef MC_CMD_0x12_PRIVILEGE_CTG
#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3033,6 +3715,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_READ32 0x14
+#define MC_CMD_PORT_READ32_MSGSET 0x14
/* MC_CMD_PORT_READ32_IN msgrequest */
#define MC_CMD_PORT_READ32_IN_LEN 4
@@ -3056,6 +3739,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_WRITE32 0x15
+#define MC_CMD_PORT_WRITE32_MSGSET 0x15
/* MC_CMD_PORT_WRITE32_IN msgrequest */
#define MC_CMD_PORT_WRITE32_IN_LEN 8
@@ -3079,6 +3763,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_READ128 0x16
+#define MC_CMD_PORT_READ128_MSGSET 0x16
/* MC_CMD_PORT_READ128_IN msgrequest */
#define MC_CMD_PORT_READ128_IN_LEN 4
@@ -3102,6 +3787,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_WRITE128 0x17
+#define MC_CMD_PORT_WRITE128_MSGSET 0x17
/* MC_CMD_PORT_WRITE128_IN msgrequest */
#define MC_CMD_PORT_WRITE128_IN_LEN 20
@@ -3150,6 +3836,7 @@
* Returns the MC firmware configuration structure.
*/
#define MC_CMD_GET_BOARD_CFG 0x18
+#define MC_CMD_GET_BOARD_CFG_MSGSET 0x18
#undef MC_CMD_0x18_PRIVILEGE_CTG
#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3225,6 +3912,7 @@
* Read DBI register(s) -- extended functionality
*/
#define MC_CMD_DBI_READX 0x19
+#define MC_CMD_DBI_READX_MSGSET 0x19
#undef MC_CMD_0x19_PRIVILEGE_CTG
#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3239,7 +3927,13 @@
#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
+#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 4
+#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 0
+#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_WIDTH 32
#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
+#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 4
+#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LBN 32
+#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_WIDTH 32
#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127
@@ -3283,6 +3977,7 @@
* Set the 16byte seed for the MC pseudo-random generator.
*/
#define MC_CMD_SET_RAND_SEED 0x1a
+#define MC_CMD_SET_RAND_SEED_MSGSET 0x1a
#undef MC_CMD_0x1a_PRIVILEGE_CTG
#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3302,6 +3997,7 @@
* Retrieve the history of the LTSSM, if the build supports it.
*/
#define MC_CMD_LTSSM_HIST 0x1b
+#define MC_CMD_LTSSM_HIST_MSGSET 0x1b
/* MC_CMD_LTSSM_HIST_IN msgrequest */
#define MC_CMD_LTSSM_HIST_IN_LEN 0
@@ -3330,6 +4026,7 @@
* platforms.
*/
#define MC_CMD_DRV_ATTACH 0x1c
+#define MC_CMD_DRV_ATTACH_MSGSET 0x1c
#undef MC_CMD_0x1c_PRIVILEGE_CTG
#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3524,6 +4221,7 @@
* Route UART output to circular buffer in shared memory instead.
*/
#define MC_CMD_SHMUART 0x1f
+#define MC_CMD_SHMUART_MSGSET 0x1f
/* MC_CMD_SHMUART_IN msgrequest */
#define MC_CMD_SHMUART_IN_LEN 4
@@ -3542,6 +4240,7 @@
* use MC_CMD_ENTITY_RESET instead.
*/
#define MC_CMD_PORT_RESET 0x20
+#define MC_CMD_PORT_RESET_MSGSET 0x20
#undef MC_CMD_0x20_PRIVILEGE_CTG
#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3560,6 +4259,7 @@
* extended version of the deprecated MC_CMD_PORT_RESET with added fields.
*/
#define MC_CMD_ENTITY_RESET 0x20
+#define MC_CMD_ENTITY_RESET_MSGSET 0x20
/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
/* MC_CMD_ENTITY_RESET_IN msgrequest */
@@ -3582,6 +4282,7 @@
* Read instantaneous and minimum flow control thresholds.
*/
#define MC_CMD_PCIE_CREDITS 0x21
+#define MC_CMD_PCIE_CREDITS_MSGSET 0x21
/* MC_CMD_PCIE_CREDITS_IN msgrequest */
#define MC_CMD_PCIE_CREDITS_IN_LEN 8
@@ -3617,6 +4318,7 @@
* Get histogram of RX queue fill level.
*/
#define MC_CMD_RXD_MONITOR 0x22
+#define MC_CMD_RXD_MONITOR_MSGSET 0x22
/* MC_CMD_RXD_MONITOR_IN msgrequest */
#define MC_CMD_RXD_MONITOR_IN_LEN 12
@@ -3676,6 +4378,7 @@
* Copy the given ASCII string out onto UART and/or out of the network port.
*/
#define MC_CMD_PUTS 0x23
+#define MC_CMD_PUTS_MSGSET 0x23
#undef MC_CMD_0x23_PRIVILEGE_CTG
#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3712,6 +4415,7 @@
* 'zombie' state. Locks required: None
*/
#define MC_CMD_GET_PHY_CFG 0x24
+#define MC_CMD_GET_PHY_CFG_MSGSET 0x24
#undef MC_CMD_0x24_PRIVILEGE_CTG
#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3868,6 +4572,7 @@
* Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
*/
#define MC_CMD_START_BIST 0x25
+#define MC_CMD_START_BIST_MSGSET 0x25
#undef MC_CMD_0x25_PRIVILEGE_CTG
#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -3908,6 +4613,7 @@
* EACCES (if PHY_LOCK is not held).
*/
#define MC_CMD_POLL_BIST 0x26
+#define MC_CMD_POLL_BIST_MSGSET 0x26
#undef MC_CMD_0x26_PRIVILEGE_CTG
#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -4077,6 +4783,7 @@
* returns). The driver must still wait for flush done/failure events as usual.
*/
#define MC_CMD_FLUSH_RX_QUEUES 0x27
+#define MC_CMD_FLUSH_RX_QUEUES_MSGSET 0x27
/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
@@ -4099,6 +4806,7 @@
* Returns a bitmask of loopback modes available at each speed.
*/
#define MC_CMD_GET_LOOPBACK_MODES 0x28
+#define MC_CMD_GET_LOOPBACK_MODES_MSGSET 0x28
#undef MC_CMD_0x28_PRIVILEGE_CTG
#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4112,7 +4820,13 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LBN 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_WIDTH 32
/* enum: None. */
#define MC_CMD_LOOPBACK_NONE 0x0
/* enum: Data. */
@@ -4195,28 +4909,52 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LBN 64
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LBN 96
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LBN 128
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LBN 160
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LBN 192
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LBN 224
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LBN 256
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LBN 288
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
@@ -4228,7 +4966,13 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LBN 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_WIDTH 32
/* enum: None. */
/* MC_CMD_LOOPBACK_NONE 0x0 */
/* enum: Data. */
@@ -4311,49 +5055,91 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LBN 64
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LBN 96
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LBN 128
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LBN 160
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LBN 192
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LBN 224
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LBN 256
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LBN 288
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported 25G loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LBN 320
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LBN 352
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported 50 loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LBN 384
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LBN 416
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported 100G loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LBN 448
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LBN 480
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
@@ -4395,6 +5181,7 @@
* ETIME.
*/
#define MC_CMD_GET_LINK 0x29
+#define MC_CMD_GET_LINK_MSGSET 0x29
#undef MC_CMD_0x29_PRIVILEGE_CTG
#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4596,6 +5383,7 @@
* code: 0, EINVAL, ETIME, EAGAIN
*/
#define MC_CMD_SET_LINK 0x2a
+#define MC_CMD_SET_LINK_MSGSET 0x2a
#undef MC_CMD_0x2a_PRIVILEGE_CTG
#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -4686,6 +5474,7 @@
* Set identification LED state. Locks required: None. Return code: 0, EINVAL
*/
#define MC_CMD_SET_ID_LED 0x2b
+#define MC_CMD_SET_ID_LED_MSGSET 0x2b
#undef MC_CMD_0x2b_PRIVILEGE_CTG
#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -4708,6 +5497,7 @@
* Set MAC configuration. Locks required: None. Return code: 0, EINVAL
*/
#define MC_CMD_SET_MAC 0x2c
+#define MC_CMD_SET_MAC_MSGSET 0x2c
#undef MC_CMD_0x2c_PRIVILEGE_CTG
#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4724,7 +5514,13 @@
#define MC_CMD_SET_MAC_IN_ADDR_OFST 8
#define MC_CMD_SET_MAC_IN_ADDR_LEN 8
#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
+#define MC_CMD_SET_MAC_IN_ADDR_LO_LEN 4
+#define MC_CMD_SET_MAC_IN_ADDR_LO_LBN 64
+#define MC_CMD_SET_MAC_IN_ADDR_LO_WIDTH 32
#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
+#define MC_CMD_SET_MAC_IN_ADDR_HI_LEN 4
+#define MC_CMD_SET_MAC_IN_ADDR_HI_LBN 96
+#define MC_CMD_SET_MAC_IN_ADDR_HI_WIDTH 32
#define MC_CMD_SET_MAC_IN_REJECT_OFST 16
#define MC_CMD_SET_MAC_IN_REJECT_LEN 4
#define MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16
@@ -4765,7 +5561,13 @@
#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LBN 64
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_WIDTH 32
#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LBN 96
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_WIDTH 32
#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
#define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16
@@ -4816,6 +5618,129 @@
#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
+/* MC_CMD_SET_MAC_V3_IN msgrequest */
+#define MC_CMD_SET_MAC_V3_IN_LEN 40
+/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
+ * EtherII, VLAN, bug16011 padding).
+ */
+#define MC_CMD_SET_MAC_V3_IN_MTU_OFST 0
+#define MC_CMD_SET_MAC_V3_IN_MTU_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4
+#define MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_ADDR_OFST 8
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LEN 8
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_OFST 8
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LBN 64
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_OFST 12
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LBN 96
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_REJECT_OFST 16
+#define MC_CMD_SET_MAC_V3_IN_REJECT_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_OFST 16
+#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0
+#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_OFST 16
+#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_LBN 1
+#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_FCNTL_OFST 20
+#define MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4
+/* enum: Flow control is off. */
+/* MC_CMD_FCNTL_OFF 0x0 */
+/* enum: Respond to flow control. */
+/* MC_CMD_FCNTL_RESPOND 0x1 */
+/* enum: Respond to and Issue flow control. */
+/* MC_CMD_FCNTL_BIDIR 0x2 */
+/* enum: Auto neg flow control. */
+/* MC_CMD_FCNTL_AUTO 0x3 */
+/* enum: Priority flow control (eftest builds only). */
+/* MC_CMD_FCNTL_QBB 0x4 */
+/* enum: Issue flow control. */
+/* MC_CMD_FCNTL_GENERATE 0x5 */
+#define MC_CMD_SET_MAC_V3_IN_FLAGS_OFST 24
+#define MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_OFST 24
+#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0
+#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_WIDTH 1
+/* Select which parameters to configure. A parameter will only be modified if
+ * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
+ * capabilities then this field is ignored (and all flags are assumed to be
+ * set).
+ */
+#define MC_CMD_SET_MAC_V3_IN_CONTROL_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0
+#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_LBN 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_LBN 2
+#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_LBN 3
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 1
+/* Identifies the MAC to update by the specifying the end of a logical MAE
+ * link. Setting TARGET to MAE_LINK_ENDPOINT_COMPAT is equivalent to using the
+ * previous version of the command (MC_CMD_SET_MAC_EXT). Not all possible
+ * combinations of MPORT_END and MPORT_SELECTOR in TARGET will work in all
+ * circumstances. 1. Some will always work (e.g. a VF can always address its
+ * logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC), 2. Some are not
+ * meaningful and will always fail with EINVAL (e.g. attempting to address the
+ * VNIC end of a link to a physical port), 3. Some are meaningful but require
+ * the MCDI client to have the required permission and fail with EPERM
+ * otherwise (e.g. trying to set the MAC on a VF the caller cannot administer),
+ * and 4. Some could be implementation-specific and fail with ENOTSUP if not
+ * available (no examples exist right now). See SF-123581-TC section 4.3 for
+ * more details.
+ */
+#define MC_CMD_SET_MAC_V3_IN_TARGET_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LEN 8
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LBN 256
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_OFST 36
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LBN 288
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 35
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 256
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 276
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 272
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 34
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_OFST 36
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LEN 8
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LBN 256
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_OFST 36
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LBN 288
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_WIDTH 32
+
/* MC_CMD_SET_MAC_OUT msgresponse */
#define MC_CMD_SET_MAC_OUT_LEN 0
@@ -4839,6 +5764,7 @@
* Returns: 0, ETIME
*/
#define MC_CMD_PHY_STATS 0x2d
+#define MC_CMD_PHY_STATS_MSGSET 0x2d
#undef MC_CMD_0x2d_PRIVILEGE_CTG
#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -4849,7 +5775,13 @@
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_WIDTH 32
/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
@@ -4921,6 +5853,7 @@
* effect. Returns: 0, ETIME
*/
#define MC_CMD_MAC_STATS 0x2e
+#define MC_CMD_MAC_STATS_MSGSET 0x2e
#undef MC_CMD_0x2e_PRIVILEGE_CTG
#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4931,7 +5864,13 @@
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_MAC_STATS_IN_CMD_OFST 8
#define MC_CMD_MAC_STATS_IN_CMD_LEN 4
#define MC_CMD_MAC_STATS_IN_DMA_OFST 8
@@ -4974,7 +5913,13 @@
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
@@ -5130,7 +6075,13 @@
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
/* enum: Start of FEC stats buffer space, Medford2 and up */
#define MC_CMD_MAC_FEC_DMABUF_START 0x61
@@ -5163,7 +6114,13 @@
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
/* enum: Start of CTPIO stats buffer space, Medford2 and up */
#define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
@@ -5237,7 +6194,13 @@
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4
/* enum: Start of V4 stats buffer space */
#define MC_CMD_MAC_V4_DMABUF_START 0x79
@@ -5266,6 +6229,7 @@
* to be documented
*/
#define MC_CMD_SRIOV 0x30
+#define MC_CMD_SRIOV_MSGSET 0x30
/* MC_CMD_SRIOV_IN msgrequest */
#define MC_CMD_SRIOV_IN_LEN 12
@@ -5297,7 +6261,13 @@
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LBN 64
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LBN 96
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
@@ -5308,7 +6278,13 @@
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LBN 160
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LBN 192
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
@@ -5338,6 +6314,7 @@
* Returns: 0, EINVAL (invalid RID)
*/
#define MC_CMD_MEMCPY 0x31
+#define MC_CMD_MEMCPY_MSGSET 0x31
/* MC_CMD_MEMCPY_IN msgrequest */
#define MC_CMD_MEMCPY_IN_LENMIN 32
@@ -5361,6 +6338,7 @@
* Set a WoL filter.
*/
#define MC_CMD_WOL_FILTER_SET 0x32
+#define MC_CMD_WOL_FILTER_SET_MSGSET 0x32
#undef MC_CMD_0x32_PRIVILEGE_CTG
#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -5401,7 +6379,13 @@
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LBN 64
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_WIDTH 32
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LBN 96
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_WIDTH 32
/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
@@ -5476,6 +6460,7 @@
* Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
*/
#define MC_CMD_WOL_FILTER_REMOVE 0x33
+#define MC_CMD_WOL_FILTER_REMOVE_MSGSET 0x33
#undef MC_CMD_0x33_PRIVILEGE_CTG
#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -5495,6 +6480,7 @@
* ENOSYS
*/
#define MC_CMD_WOL_FILTER_RESET 0x34
+#define MC_CMD_WOL_FILTER_RESET_MSGSET 0x34
#undef MC_CMD_0x34_PRIVILEGE_CTG
#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -5515,6 +6501,7 @@
* Set the MCAST hash value without otherwise reconfiguring the MAC
*/
#define MC_CMD_SET_MCAST_HASH 0x35
+#define MC_CMD_SET_MCAST_HASH_MSGSET 0x35
/* MC_CMD_SET_MCAST_HASH_IN msgrequest */
#define MC_CMD_SET_MCAST_HASH_IN_LEN 32
@@ -5533,6 +6520,7 @@
* Locks required: none. Returns: 0
*/
#define MC_CMD_NVRAM_TYPES 0x36
+#define MC_CMD_NVRAM_TYPES_MSGSET 0x36
#undef MC_CMD_0x36_PRIVILEGE_CTG
#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5595,6 +6583,7 @@
* EINVAL (bad type).
*/
#define MC_CMD_NVRAM_INFO 0x37
+#define MC_CMD_NVRAM_INFO_MSGSET 0x37
#undef MC_CMD_0x37_PRIVILEGE_CTG
#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5692,6 +6681,7 @@
* EPERM.
*/
#define MC_CMD_NVRAM_UPDATE_START 0x38
+#define MC_CMD_NVRAM_UPDATE_START_MSGSET 0x38
#undef MC_CMD_0x38_PRIVILEGE_CTG
#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5732,6 +6722,7 @@
* PHY_LOCK required and not held)
*/
#define MC_CMD_NVRAM_READ 0x39
+#define MC_CMD_NVRAM_READ_MSGSET 0x39
#undef MC_CMD_0x39_PRIVILEGE_CTG
#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5803,6 +6794,7 @@
* PHY_LOCK required and not held)
*/
#define MC_CMD_NVRAM_WRITE 0x3a
+#define MC_CMD_NVRAM_WRITE_MSGSET 0x3a
#undef MC_CMD_0x3a_PRIVILEGE_CTG
#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5838,6 +6830,7 @@
* PHY_LOCK required and not held)
*/
#define MC_CMD_NVRAM_ERASE 0x3b
+#define MC_CMD_NVRAM_ERASE_MSGSET 0x3b
#undef MC_CMD_0x3b_PRIVILEGE_CTG
#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5868,6 +6861,7 @@
* the error EPERM.
*/
#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
+#define MC_CMD_NVRAM_UPDATE_FINISH_MSGSET 0x3c
#undef MC_CMD_0x3c_PRIVILEGE_CTG
#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5906,6 +6900,9 @@
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_OFST 8
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_LBN 3
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_WIDTH 1
/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
* response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
@@ -6036,6 +7033,7 @@
* DATALEN=0
*/
#define MC_CMD_REBOOT 0x3d
+#define MC_CMD_REBOOT_MSGSET 0x3d
#undef MC_CMD_0x3d_PRIVILEGE_CTG
#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -6057,6 +7055,7 @@
* thread address.
*/
#define MC_CMD_SCHEDINFO 0x3e
+#define MC_CMD_SCHEDINFO_MSGSET 0x3e
#undef MC_CMD_0x3e_PRIVILEGE_CTG
#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6083,6 +7082,7 @@
* mode to the specified value. Returns the old mode.
*/
#define MC_CMD_REBOOT_MODE 0x3f
+#define MC_CMD_REBOOT_MODE_MSGSET 0x3f
#undef MC_CMD_0x3f_PRIVILEGE_CTG
#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -6141,6 +7141,7 @@
* Locks required: None Returns: 0
*/
#define MC_CMD_SENSOR_INFO 0x41
+#define MC_CMD_SENSOR_INFO_MSGSET 0x41
#undef MC_CMD_0x41_PRIVILEGE_CTG
#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -6380,7 +7381,13 @@
#define MC_CMD_SENSOR_ENTRY_OFST 4
#define MC_CMD_SENSOR_ENTRY_LEN 8
#define MC_CMD_SENSOR_ENTRY_LO_OFST 4
+#define MC_CMD_SENSOR_ENTRY_LO_LEN 4
+#define MC_CMD_SENSOR_ENTRY_LO_LBN 32
+#define MC_CMD_SENSOR_ENTRY_LO_WIDTH 32
#define MC_CMD_SENSOR_ENTRY_HI_OFST 8
+#define MC_CMD_SENSOR_ENTRY_HI_LEN 4
+#define MC_CMD_SENSOR_ENTRY_HI_LBN 64
+#define MC_CMD_SENSOR_ENTRY_HI_WIDTH 32
#define MC_CMD_SENSOR_ENTRY_MINNUM 0
#define MC_CMD_SENSOR_ENTRY_MAXNUM 31
#define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127
@@ -6402,7 +7409,13 @@
/* MC_CMD_SENSOR_ENTRY_OFST 4 */
/* MC_CMD_SENSOR_ENTRY_LEN 8 */
/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
+/* MC_CMD_SENSOR_ENTRY_LO_LEN 4 */
+/* MC_CMD_SENSOR_ENTRY_LO_LBN 32 */
+/* MC_CMD_SENSOR_ENTRY_LO_WIDTH 32 */
/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
+/* MC_CMD_SENSOR_ENTRY_HI_LEN 4 */
+/* MC_CMD_SENSOR_ENTRY_HI_LBN 64 */
+/* MC_CMD_SENSOR_ENTRY_HI_WIDTH 32 */
/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
/* MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */
@@ -6445,6 +7458,7 @@
* STATE_WARNING. Otherwise the board should not be expected to function.
*/
#define MC_CMD_READ_SENSORS 0x42
+#define MC_CMD_READ_SENSORS_MSGSET 0x42
#undef MC_CMD_0x42_PRIVILEGE_CTG
#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -6459,7 +7473,13 @@
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_WIDTH 32
/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
@@ -6471,7 +7491,13 @@
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_WIDTH 32
/* Size in bytes of host buffer. */
#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
@@ -6486,7 +7512,13 @@
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LBN 32
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_WIDTH 32
/* Size in bytes of host buffer. */
#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8
#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
@@ -6540,6 +7572,7 @@
* code: 0
*/
#define MC_CMD_GET_PHY_STATE 0x43
+#define MC_CMD_GET_PHY_STATE_MSGSET 0x43
#undef MC_CMD_0x43_PRIVILEGE_CTG
#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -6563,6 +7596,7 @@
* disable 802.Qbb for a given priority.
*/
#define MC_CMD_SETUP_8021QBB 0x44
+#define MC_CMD_SETUP_8021QBB_MSGSET 0x44
/* MC_CMD_SETUP_8021QBB_IN msgrequest */
#define MC_CMD_SETUP_8021QBB_IN_LEN 32
@@ -6578,6 +7612,7 @@
* Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
*/
#define MC_CMD_WOL_FILTER_GET 0x45
+#define MC_CMD_WOL_FILTER_GET_MSGSET 0x45
#undef MC_CMD_0x45_PRIVILEGE_CTG
#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -6597,6 +7632,7 @@
* Returns: 0, ENOSYS
*/
#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
+#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_MSGSET 0x46
#undef MC_CMD_0x46_PRIVILEGE_CTG
#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -6649,6 +7685,7 @@
* None. Returns: 0, ENOSYS
*/
#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
+#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_MSGSET 0x47
#undef MC_CMD_0x47_PRIVILEGE_CTG
#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -6669,6 +7706,7 @@
* Restore MAC after block reset. Locks required: None. Returns: 0.
*/
#define MC_CMD_MAC_RESET_RESTORE 0x48
+#define MC_CMD_MAC_RESET_RESTORE_MSGSET 0x48
/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
@@ -6684,6 +7722,7 @@
* required: None Returns: 0
*/
#define MC_CMD_TESTASSERT 0x49
+#define MC_CMD_TESTASSERT_MSGSET 0x49
#undef MC_CMD_0x49_PRIVILEGE_CTG
#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -6727,6 +7766,7 @@
* basis. Locks required: None. Returns: 0, EINVAL .
*/
#define MC_CMD_WORKAROUND 0x4a
+#define MC_CMD_WORKAROUND_MSGSET 0x4a
#undef MC_CMD_0x4a_PRIVILEGE_CTG
#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6790,6 +7830,7 @@
* Anything else: currently undefined. Locks required: None. Return code: 0.
*/
#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
+#define MC_CMD_GET_PHY_MEDIA_INFO_MSGSET 0x4b
#undef MC_CMD_0x4b_PRIVILEGE_CTG
#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6821,6 +7862,7 @@
* on the type of partition).
*/
#define MC_CMD_NVRAM_TEST 0x4c
+#define MC_CMD_NVRAM_TEST_MSGSET 0x4c
#undef MC_CMD_0x4c_PRIVILEGE_CTG
#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -6851,6 +7893,7 @@
* they are configured first. Locks required: None. Return code: 0, EINVAL.
*/
#define MC_CMD_MRSFP_TWEAK 0x4d
+#define MC_CMD_MRSFP_TWEAK_MSGSET 0x4d
/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
@@ -6894,6 +7937,7 @@
* of range.
*/
#define MC_CMD_SENSOR_SET_LIMS 0x4e
+#define MC_CMD_SENSOR_SET_LIMS_MSGSET 0x4e
#undef MC_CMD_0x4e_PRIVILEGE_CTG
#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -6925,6 +7969,7 @@
/* MC_CMD_GET_RESOURCE_LIMITS
*/
#define MC_CMD_GET_RESOURCE_LIMITS 0x4f
+#define MC_CMD_GET_RESOURCE_LIMITS_MSGSET 0x4f
/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
@@ -6947,6 +7992,7 @@
* none. Returns: 0, EINVAL (bad type).
*/
#define MC_CMD_NVRAM_PARTITIONS 0x51
+#define MC_CMD_NVRAM_PARTITIONS_MSGSET 0x51
#undef MC_CMD_0x51_PRIVILEGE_CTG
#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6977,6 +8023,7 @@
* none. Returns: 0, EINVAL (bad type).
*/
#define MC_CMD_NVRAM_METADATA 0x52
+#define MC_CMD_NVRAM_METADATA_MSGSET 0x52
#undef MC_CMD_0x52_PRIVILEGE_CTG
#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -7035,6 +8082,7 @@
* Returns the base MAC, count and stride for the requesting function
*/
#define MC_CMD_GET_MAC_ADDRESSES 0x55
+#define MC_CMD_GET_MAC_ADDRESSES_MSGSET 0x55
#undef MC_CMD_0x55_PRIVILEGE_CTG
#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -7066,6 +8114,7 @@
* SF-120509-TC and SF-117282-PS.
*/
#define MC_CMD_CLP 0x56
+#define MC_CMD_CLP_MSGSET 0x56
#undef MC_CMD_0x56_PRIVILEGE_CTG
#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -7188,6 +8237,7 @@
* Perform a MUM operation
*/
#define MC_CMD_MUM 0x57
+#define MC_CMD_MUM_MSGSET 0x57
#undef MC_CMD_0x57_PRIVILEGE_CTG
#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -7604,7 +8654,13 @@
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 4
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LBN 32
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_WIDTH 32
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 4
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LBN 64
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_WIDTH 32
/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
#define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
@@ -7789,7 +8845,13 @@
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 4
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LBN 64
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_WIDTH 32
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 4
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LBN 96
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_WIDTH 32
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126
@@ -7986,6 +9048,7 @@
* sensor_query SPHINX service.
*/
#define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
+#define MC_CMD_DYNAMIC_SENSORS_LIST_MSGSET 0x66
#undef MC_CMD_0x66_PRIVILEGE_CTG
#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8031,6 +9094,7 @@
* `get_descriptions` in the sensor_query SPHINX service.
*/
#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_MSGSET 0x67
#undef MC_CMD_0x67_PRIVILEGE_CTG
#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8080,6 +9144,7 @@
* in the sensor_query SPHINX service.
*/
#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_MSGSET 0x68
#undef MC_CMD_0x68_PRIVILEGE_CTG
#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8117,6 +9182,7 @@
* receive (Riverhead).
*/
#define MC_CMD_EVENT_CTRL 0x69
+#define MC_CMD_EVENT_CTRL_MSGSET 0x69
#undef MC_CMD_0x69_PRIVILEGE_CTG
#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8197,7 +9263,13 @@
#define BUFTBL_ENTRY_RAWADDR_OFST 4
#define BUFTBL_ENTRY_RAWADDR_LEN 8
#define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
+#define BUFTBL_ENTRY_RAWADDR_LO_LEN 4
+#define BUFTBL_ENTRY_RAWADDR_LO_LBN 32
+#define BUFTBL_ENTRY_RAWADDR_LO_WIDTH 32
#define BUFTBL_ENTRY_RAWADDR_HI_OFST 8
+#define BUFTBL_ENTRY_RAWADDR_HI_LEN 4
+#define BUFTBL_ENTRY_RAWADDR_HI_LBN 64
+#define BUFTBL_ENTRY_RAWADDR_HI_WIDTH 32
#define BUFTBL_ENTRY_RAWADDR_LBN 32
#define BUFTBL_ENTRY_RAWADDR_WIDTH 64
@@ -8207,14 +9279,25 @@
#define NVRAM_PARTITION_TYPE_ID_LEN 2
/* enum: Primary MC firmware partition */
#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
+/* enum: NMC firmware partition (this is intentionally an alias of MC_FIRMWARE)
+ */
+#define NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100
/* enum: Secondary MC firmware partition */
#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
/* enum: Expansion ROM partition */
#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
/* enum: Static configuration TLV partition */
#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
+/* enum: Factory configuration TLV partition (this is intentionally an alias of
+ * STATIC_CONFIG)
+ */
+#define NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400
/* enum: Dynamic configuration TLV partition */
#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
+/* enum: User configuration TLV partition (this is intentionally an alias of
+ * DYNAMIC_CONFIG)
+ */
+#define NVRAM_PARTITION_TYPE_USER_CONFIG 0x500
/* enum: Expansion ROM configuration data for port 0 */
#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
@@ -8227,10 +9310,16 @@
#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
/* enum: Non-volatile log output partition */
#define NVRAM_PARTITION_TYPE_LOG 0x700
+/* enum: Non-volatile log output partition for NMC firmware (this is
+ * intentionally an alias of LOG)
+ */
+#define NVRAM_PARTITION_TYPE_NMC_LOG 0x700
/* enum: Non-volatile log output of second core on dual-core device */
#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
/* enum: Device state dump output partition */
#define NVRAM_PARTITION_TYPE_DUMP 0x800
+/* enum: Crash log partition for NMC firmware */
+#define NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801
/* enum: Application license key storage partition */
#define NVRAM_PARTITION_TYPE_LICENSE 0x900
/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
@@ -8247,6 +9336,20 @@
#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
/* enum: Non-volatile log output partition for FC */
#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
+/* enum: FPGA Stage 1 bitstream */
+#define NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05
+/* enum: FPGA Stage 2 bitstream */
+#define NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06
+/* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */
+#define NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07
+/* enum: FPGA User XCLBIN (this is intentionally an alias of FPGA_REGION0) */
+#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07
+/* enum: FPGA jump instruction (a.k.a. boot) partition to select Stage1
+ * bitstream
+ */
+#define NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08
+/* enum: FPGA Validate XCLBIN */
+#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09
/* enum: MUM firmware partition */
#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
/* enum: SUC firmware partition (this is intentionally an alias of
@@ -8255,6 +9358,10 @@
#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
/* enum: MUM Non-volatile log output partition. */
#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
+/* enum: SUC Non-volatile log output partition (this is intentionally an alias
+ * of MUM_LOG).
+ */
+#define NVRAM_PARTITION_TYPE_SUC_LOG 0xc01
/* enum: MUM Application table partition. */
#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
/* enum: MUM boot rom partition. */
@@ -8269,6 +9376,10 @@
#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
/* enum: Used by the expansion ROM for logging */
#define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
+/* enum: Non-volatile log output partition for Expansion ROM (this is
+ * intentionally an alias of PXE_LOG).
+ */
+#define NVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000
/* enum: Used for XIP code of shmbooted images */
#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
/* enum: Spare partition 2 */
@@ -8277,6 +9388,10 @@
* between XJTAG and Manftest.
*/
#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
+/* enum: Deployment configuration TLV partition (this is intentionally an alias
+ * of MANUFACTURING)
+ */
+#define NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300
/* enum: Spare partition 4 */
#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
/* enum: Spare partition 5 */
@@ -8312,14 +9427,43 @@
#define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */
#define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
+/* enum: Test partition on SmartNIC system microcontroller (SUC) */
+#define NVRAM_PARTITION_TYPE_SUC_TEST 0x1f00
+/* enum: System microcontroller access to primary FPGA flash. */
+#define NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01
+/* enum: System microcontroller access to secondary FPGA flash (if present) */
+#define NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02
+/* enum: System microcontroller access to primary System-on-Chip flash */
+#define NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03
+/* enum: System microcontroller access to secondary System-on-Chip flash (if
+ * present)
+ */
+#define NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04
+/* enum: System microcontroller critical failure logs. Contains structured
+ * details of sensors leading up to a critical failure (where the board is shut
+ * down).
+ */
+#define NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05
+/* enum: System-on-Chip configuration information (see XN-200467-PS). */
+#define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07
+/* enum: System-on-Chip update information. */
+#define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003
/* enum: Start of reserved value range (firmware may use for any purpose) */
#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
/* enum: End of reserved value range (firmware may use for any purpose) */
#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
/* enum: Recovery partition map (provided if real map is missing or corrupt) */
#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
+/* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is
+ * intentionally an alias of RECOVERY_MAP)
+ */
+#define NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe
/* enum: Partition map (real map as stored in flash) */
#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
+/* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an
+ * alias of PARTITION_MAP)
+ */
+#define NVRAM_PARTITION_TYPE_FPT 0xffff
#define NVRAM_PARTITION_TYPE_ID_LBN 0
#define NVRAM_PARTITION_TYPE_ID_WIDTH 16
@@ -8368,7 +9512,13 @@
#define LICENSED_FEATURES_MASK_OFST 0
#define LICENSED_FEATURES_MASK_LEN 8
#define LICENSED_FEATURES_MASK_LO_OFST 0
+#define LICENSED_FEATURES_MASK_LO_LEN 4
+#define LICENSED_FEATURES_MASK_LO_LBN 0
+#define LICENSED_FEATURES_MASK_LO_WIDTH 32
#define LICENSED_FEATURES_MASK_HI_OFST 4
+#define LICENSED_FEATURES_MASK_HI_LEN 4
+#define LICENSED_FEATURES_MASK_HI_LBN 32
+#define LICENSED_FEATURES_MASK_HI_WIDTH 32
#define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
@@ -8408,7 +9558,13 @@
#define LICENSED_V3_APPS_MASK_OFST 0
#define LICENSED_V3_APPS_MASK_LEN 8
#define LICENSED_V3_APPS_MASK_LO_OFST 0
+#define LICENSED_V3_APPS_MASK_LO_LEN 4
+#define LICENSED_V3_APPS_MASK_LO_LBN 0
+#define LICENSED_V3_APPS_MASK_LO_WIDTH 32
#define LICENSED_V3_APPS_MASK_HI_OFST 4
+#define LICENSED_V3_APPS_MASK_HI_LEN 4
+#define LICENSED_V3_APPS_MASK_HI_LBN 32
+#define LICENSED_V3_APPS_MASK_HI_WIDTH 32
#define LICENSED_V3_APPS_ONLOAD_OFST 0
#define LICENSED_V3_APPS_ONLOAD_LBN 0
#define LICENSED_V3_APPS_ONLOAD_WIDTH 1
@@ -8466,7 +9622,13 @@
#define LICENSED_V3_FEATURES_MASK_OFST 0
#define LICENSED_V3_FEATURES_MASK_LEN 8
#define LICENSED_V3_FEATURES_MASK_LO_OFST 0
+#define LICENSED_V3_FEATURES_MASK_LO_LEN 4
+#define LICENSED_V3_FEATURES_MASK_LO_LBN 0
+#define LICENSED_V3_FEATURES_MASK_LO_WIDTH 32
#define LICENSED_V3_FEATURES_MASK_HI_OFST 4
+#define LICENSED_V3_FEATURES_MASK_HI_LEN 4
+#define LICENSED_V3_FEATURES_MASK_HI_LBN 32
+#define LICENSED_V3_FEATURES_MASK_HI_WIDTH 32
#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
@@ -8617,6 +9779,7 @@
* Get a dump of the MCPU registers
*/
#define MC_CMD_READ_REGS 0x50
+#define MC_CMD_READ_REGS_MSGSET 0x50
#undef MC_CMD_0x50_PRIVILEGE_CTG
#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -8643,6 +9806,7 @@
* end with an address for each 4k of host memory required to back the EVQ.
*/
#define MC_CMD_INIT_EVQ 0x80
+#define MC_CMD_INIT_EVQ_MSGSET 0x80
#undef MC_CMD_0x80_PRIVILEGE_CTG
#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8657,7 +9821,8 @@
#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
#define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
@@ -8729,7 +9894,13 @@
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LBN 288
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LBN 320
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 64
@@ -8750,7 +9921,8 @@
#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
@@ -8847,7 +10019,13 @@
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LBN 288
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LBN 320
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 64
@@ -8900,6 +10078,7 @@
* the RXQ.
*/
#define MC_CMD_INIT_RXQ 0x81
+#define MC_CMD_INIT_RXQ_MSGSET 0x81
#undef MC_CMD_0x81_PRIVILEGE_CTG
#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8923,7 +10102,8 @@
#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
@@ -8964,7 +10144,13 @@
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
@@ -8988,7 +10174,8 @@
#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
@@ -9062,7 +10249,13 @@
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9085,7 +10278,8 @@
#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
@@ -9159,7 +10353,13 @@
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9211,7 +10411,8 @@
#define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
@@ -9285,7 +10486,13 @@
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9350,7 +10557,8 @@
#define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
@@ -9424,7 +10632,13 @@
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9497,6 +10711,7 @@
/* MC_CMD_INIT_TXQ
*/
#define MC_CMD_INIT_TXQ 0x82
+#define MC_CMD_INIT_TXQ_MSGSET 0x82
#undef MC_CMD_0x82_PRIVILEGE_CTG
#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9521,7 +10736,8 @@
#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
#define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
@@ -9565,7 +10781,13 @@
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
@@ -9586,7 +10808,8 @@
#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
@@ -9648,7 +10871,13 @@
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64
@@ -9674,6 +10903,7 @@
* or the operation will fail with EBUSY
*/
#define MC_CMD_FINI_EVQ 0x83
+#define MC_CMD_FINI_EVQ_MSGSET 0x83
#undef MC_CMD_0x83_PRIVILEGE_CTG
#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9695,6 +10925,7 @@
* Teardown a RXQ.
*/
#define MC_CMD_FINI_RXQ 0x84
+#define MC_CMD_FINI_RXQ_MSGSET 0x84
#undef MC_CMD_0x84_PRIVILEGE_CTG
#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9714,6 +10945,7 @@
* Teardown a TXQ.
*/
#define MC_CMD_FINI_TXQ 0x85
+#define MC_CMD_FINI_TXQ_MSGSET 0x85
#undef MC_CMD_0x85_PRIVILEGE_CTG
#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9733,6 +10965,7 @@
* Generate an event on an EVQ belonging to the function issuing the command.
*/
#define MC_CMD_DRIVER_EVENT 0x86
+#define MC_CMD_DRIVER_EVENT_MSGSET 0x86
#undef MC_CMD_0x86_PRIVILEGE_CTG
#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9746,7 +10979,13 @@
#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
+#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 4
+#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LBN 32
+#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_WIDTH 32
#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
+#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 4
+#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LBN 64
+#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_WIDTH 32
/* MC_CMD_DRIVER_EVENT_OUT msgresponse */
#define MC_CMD_DRIVER_EVENT_OUT_LEN 0
@@ -9760,6 +10999,7 @@
* MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
*/
#define MC_CMD_PROXY_CMD 0x5b
+#define MC_CMD_PROXY_CMD_MSGSET 0x5b
#undef MC_CMD_0x5b_PRIVILEGE_CTG
#define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -9828,6 +11068,7 @@
* a designated admin function
*/
#define MC_CMD_PROXY_CONFIGURE 0x58
+#define MC_CMD_PROXY_CONFIGURE_MSGSET 0x58
#undef MC_CMD_0x58_PRIVILEGE_CTG
#define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -9845,7 +11086,13 @@
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LBN 32
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LBN 64
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
@@ -9855,7 +11102,13 @@
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LBN 128
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LBN 160
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
@@ -9866,7 +11119,13 @@
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LBN 224
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LBN 256
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2, or zero if this buffer is not provided */
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
@@ -9890,7 +11149,13 @@
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LBN 32
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LBN 64
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
@@ -9900,7 +11165,13 @@
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LBN 128
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LBN 160
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
@@ -9911,7 +11182,13 @@
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LBN 224
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LBN 256
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2, or zero if this buffer is not provided */
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
@@ -9936,6 +11213,7 @@
* MC_CMD_PROXY_CONFIGURE).
*/
#define MC_CMD_PROXY_COMPLETE 0x5f
+#define MC_CMD_PROXY_COMPLETE_MSGSET 0x5f
#undef MC_CMD_0x5f_PRIVILEGE_CTG
#define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -9974,6 +11252,7 @@
* cannot do so). The buffer table entries will initially be zeroed.
*/
#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
+#define MC_CMD_ALLOC_BUFTBL_CHUNK_MSGSET 0x87
#undef MC_CMD_0x87_PRIVILEGE_CTG
#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -10005,6 +11284,7 @@
* Reprogram a set of buffer table entries in the specified chunk.
*/
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_MSGSET 0x88
#undef MC_CMD_0x88_PRIVILEGE_CTG
#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -10027,7 +11307,13 @@
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LEN 4
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LBN 96
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_WIDTH 32
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LEN 4
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LBN 128
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_WIDTH 32
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 32
@@ -10040,6 +11326,7 @@
/* MC_CMD_FREE_BUFTBL_CHUNK
*/
#define MC_CMD_FREE_BUFTBL_CHUNK 0x89
+#define MC_CMD_FREE_BUFTBL_CHUNK_MSGSET 0x89
#undef MC_CMD_0x89_PRIVILEGE_CTG
#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -10058,6 +11345,7 @@
* Multiplexed MCDI call for filter operations
*/
#define MC_CMD_FILTER_OP 0x8a
+#define MC_CMD_FILTER_OP_MSGSET 0x8a
#undef MC_CMD_0x8a_PRIVILEGE_CTG
#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -10083,7 +11371,13 @@
#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_IN_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_IN_HANDLE_HI_WIDTH 32
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
@@ -10239,7 +11533,13 @@
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_WIDTH 32
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
@@ -10518,7 +11818,13 @@
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_WIDTH 32
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12
@@ -10779,15 +12085,15 @@
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16
-/* Flags controlling mutations of the user_mark and user_flag fields of
- * matching packets, with logic as follows: if (req.MATCH_BITOR_FLAG == 1)
- * user_flag = req.MATCH_SET_FLAG bit_or user_flag; else user_flag =
- * req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark = 0; else if
- * (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK bit_or user_mark;
- * else user_mark = req.MATCH_SET_MARK; N.B. These flags overlap with the
- * MATCH_ACTION field, which is deprecated in favour of this field. For the
- * cases where these flags induce a valid encoding of the MATCH_ACTION field,
- * the semantics agree.
+/* Flags controlling mutations of the packet and/or metadata when the filter is
+ * matched. The user_mark and user_flag fields' logic is as follows: if
+ * (req.MATCH_BITOR_FLAG == 1) user_flag = req.MATCH_SET_FLAG bit_or user_flag;
+ * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark
+ * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK
+ * bit_or user_mark; else user_mark = req.MATCH_SET_MARK; N.B. These flags
+ * overlap with the MATCH_ACTION field, which is deprecated in favour of this
+ * field. For the cases where these flags induce a valid encoding of the
+ * MATCH_ACTION field, the semantics agree.
*/
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_OFST 172
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4
@@ -10803,6 +12109,9 @@
#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_OFST 172
#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_LBN 3
#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_WIDTH 1
+#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_OFST 172
+#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 4
+#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_WIDTH 1
/* Deprecated: the overlapping MATCH_ACTION_FLAGS field exposes all of the
* functionality of this field in an ABI-backwards-compatible manner, and
* should be used instead. Any future extensions should be made to the
@@ -10848,7 +12157,13 @@
#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_WIDTH 32
/* enum: guaranteed invalid filter handle (low 32 bits) */
#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
/* enum: guaranteed invalid filter handle (high 32 bits) */
@@ -10868,7 +12183,13 @@
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_WIDTH 32
/* Enum values, see field(s): */
/* MC_CMD_FILTER_OP_OUT/HANDLE */
@@ -10878,6 +12199,7 @@
* Get information related to the parser-dispatcher subsystem
*/
#define MC_CMD_GET_PARSER_DISP_INFO 0xe4
+#define MC_CMD_GET_PARSER_DISP_INFO_MSGSET 0xe4
#undef MC_CMD_0xe4_PRIVILEGE_CTG
#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11025,6 +12347,7 @@
* permitted.
*/
#define MC_CMD_PARSER_DISP_RW 0xe5
+#define MC_CMD_PARSER_DISP_RW_MSGSET 0xe5
#undef MC_CMD_0xe5_PRIVILEGE_CTG
#define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11115,6 +12438,7 @@
* Get number of PFs on the device.
*/
#define MC_CMD_GET_PF_COUNT 0xb6
+#define MC_CMD_GET_PF_COUNT_MSGSET 0xb6
#undef MC_CMD_0xb6_PRIVILEGE_CTG
#define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11134,6 +12458,7 @@
* Set number of PFs on the device.
*/
#define MC_CMD_SET_PF_COUNT 0xb7
+#define MC_CMD_SET_PF_COUNT_MSGSET 0xb7
/* MC_CMD_SET_PF_COUNT_IN msgrequest */
#define MC_CMD_SET_PF_COUNT_IN_LEN 4
@@ -11150,6 +12475,7 @@
* Get port assignment for current PCI function.
*/
#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
+#define MC_CMD_GET_PORT_ASSIGNMENT_MSGSET 0xb8
#undef MC_CMD_0xb8_PRIVILEGE_CTG
#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11175,6 +12501,7 @@
* Set port assignment for current PCI function.
*/
#define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
+#define MC_CMD_SET_PORT_ASSIGNMENT_MSGSET 0xb9
#undef MC_CMD_0xb9_PRIVILEGE_CTG
#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11194,6 +12521,7 @@
* Allocate VIs for current PCI function.
*/
#define MC_CMD_ALLOC_VIS 0x8b
+#define MC_CMD_ALLOC_VIS_MSGSET 0x8b
#undef MC_CMD_0x8b_PRIVILEGE_CTG
#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11241,6 +12569,7 @@
* but not freed.
*/
#define MC_CMD_FREE_VIS 0x8c
+#define MC_CMD_FREE_VIS_MSGSET 0x8c
#undef MC_CMD_0x8c_PRIVILEGE_CTG
#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11257,6 +12586,7 @@
* Get SRIOV config for this PF.
*/
#define MC_CMD_GET_SRIOV_CFG 0xba
+#define MC_CMD_GET_SRIOV_CFG_MSGSET 0xba
#undef MC_CMD_0xba_PRIVILEGE_CTG
#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11290,6 +12620,7 @@
* Set SRIOV config for this PF.
*/
#define MC_CMD_SET_SRIOV_CFG 0xbb
+#define MC_CMD_SET_SRIOV_CFG_MSGSET 0xbb
#undef MC_CMD_0xbb_PRIVILEGE_CTG
#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11325,9 +12656,11 @@
/***********************************/
/* MC_CMD_GET_VI_ALLOC_INFO
* Get information about number of VI's and base VI number allocated to this
- * function.
+ * function. This message is not available to dynamic clients created by
+ * MC_CMD_CLIENT_ALLOC.
*/
#define MC_CMD_GET_VI_ALLOC_INFO 0x8d
+#define MC_CMD_GET_VI_ALLOC_INFO_MSGSET 0x8d
#undef MC_CMD_0x8d_PRIVILEGE_CTG
#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11352,9 +12685,12 @@
/***********************************/
/* MC_CMD_DUMP_VI_STATE
- * For CmdClient use. Dump pertinent information on a specific absolute VI.
+ * For CmdClient use. Dump pertinent information on a specific absolute VI. The
+ * VI must be owned by the calling client or one of its ancestors; usership of
+ * the VI (as set by MC_CMD_SET_VI_USER) is not sufficient.
*/
#define MC_CMD_DUMP_VI_STATE 0x8e
+#define MC_CMD_DUMP_VI_STATE_MSGSET 0x8e
#undef MC_CMD_0x8e_PRIVILEGE_CTG
#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11366,7 +12702,7 @@
#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
-#define MC_CMD_DUMP_VI_STATE_OUT_LEN 96
+#define MC_CMD_DUMP_VI_STATE_OUT_LEN 100
/* The PF part of the function owning this VI. */
#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
@@ -11389,12 +12725,24 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LBN 96
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LBN 128
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_WIDTH 32
/* Raw evq timer table data. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LBN 160
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LBN 192
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_WIDTH 32
/* Combined metadata field. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
@@ -11411,22 +12759,46 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LBN 256
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LBN 288
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_WIDTH 32
/* TXDPCPU raw table data for queue. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LBN 320
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LBN 352
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_WIDTH 32
/* TXDPCPU raw table data for queue. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LBN 384
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LBN 416
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_WIDTH 32
/* Combined metadata field. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LBN 448
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LBN 480
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
@@ -11446,22 +12818,46 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LBN 512
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LBN 544
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_WIDTH 32
/* RXDPCPU raw table data for queue. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LBN 576
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LBN 608
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_WIDTH 32
/* Reserved, currently 0. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LBN 640
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LBN 672
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_WIDTH 32
/* Combined metadata field. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LBN 704
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LBN 736
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
@@ -11474,6 +12870,9 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
+/* Current user, as assigned by MC_CMD_SET_VI_USER. */
+#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_OFST 96
+#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_LEN 4
/***********************************/
@@ -11481,6 +12880,7 @@
* Allocate a push I/O buffer for later use with a tx queue.
*/
#define MC_CMD_ALLOC_PIOBUF 0x8f
+#define MC_CMD_ALLOC_PIOBUF_MSGSET 0x8f
#undef MC_CMD_0x8f_PRIVILEGE_CTG
#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -11500,6 +12900,7 @@
* Free a push I/O buffer.
*/
#define MC_CMD_FREE_PIOBUF 0x90
+#define MC_CMD_FREE_PIOBUF_MSGSET 0x90
#undef MC_CMD_0x90_PRIVILEGE_CTG
#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -11516,9 +12917,12 @@
/***********************************/
/* MC_CMD_GET_VI_TLP_PROCESSING
- * Get TLP steering and ordering information for a VI.
+ * Get TLP steering and ordering information for a VI. The caller must have the
+ * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
+ * an ancestor of the current user (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
+#define MC_CMD_GET_VI_TLP_PROCESSING_MSGSET 0xb0
#undef MC_CMD_0xb0_PRIVILEGE_CTG
#define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11555,9 +12959,12 @@
/***********************************/
/* MC_CMD_SET_VI_TLP_PROCESSING
- * Set TLP steering and ordering information for a VI.
+ * Set TLP steering and ordering information for a VI. The caller must have the
+ * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
+ * an ancestor of the current user (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
+#define MC_CMD_SET_VI_TLP_PROCESSING_MSGSET 0xb1
#undef MC_CMD_0xb1_PRIVILEGE_CTG
#define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11597,6 +13004,7 @@
* Get global PCIe steering and transaction processing configuration.
*/
#define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
+#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_MSGSET 0xbc
#undef MC_CMD_0xbc_PRIVILEGE_CTG
#define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11681,6 +13089,7 @@
* Set global PCIe steering and transaction processing configuration.
*/
#define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
+#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_MSGSET 0xbd
#undef MC_CMD_0xbd_PRIVILEGE_CTG
#define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11746,6 +13155,7 @@
* Download a new set of images to the satellite CPUs from the host.
*/
#define MC_CMD_SATELLITE_DOWNLOAD 0x91
+#define MC_CMD_SATELLITE_DOWNLOAD_MSGSET 0x91
#undef MC_CMD_0x91_PRIVILEGE_CTG
#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -11873,6 +13283,7 @@
* reference inherent device capabilities as opposed to current NVRAM config.
*/
#define MC_CMD_GET_CAPABILITIES 0xbe
+#define MC_CMD_GET_CAPABILITIES_MSGSET 0xbe
#undef MC_CMD_0xbe_PRIVILEGE_CTG
#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -14813,6 +16224,18 @@
#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */
#define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160
@@ -15299,6 +16722,18 @@
#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
@@ -15306,7 +16741,13 @@
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LBN 1216
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_WIDTH 32
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LBN 1248
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_WIDTH 32
/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */
#define MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184
@@ -15793,6 +17234,18 @@
#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
@@ -15800,7 +17253,13 @@
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LBN 1216
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_WIDTH 32
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LBN 1248
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_WIDTH 32
/* The minimum size (in table entries) of indirection table to be allocated
* from the pool for an RSS context. Note that the table size used must be a
* power of 2.
@@ -16322,6 +17781,18 @@
#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
@@ -16329,7 +17800,13 @@
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_OFST 152
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LEN 8
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_OFST 152
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LBN 1216
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_WIDTH 32
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_OFST 156
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LBN 1248
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_WIDTH 32
/* The minimum size (in table entries) of indirection table to be allocated
* from the pool for an RSS context. Note that the table size used must be a
* power of 2.
@@ -16386,6 +17863,7 @@
* Encapsulation for a v2 extended command
*/
#define MC_CMD_V2_EXTN 0x7f
+#define MC_CMD_V2_EXTN_MSGSET 0x7f
/* MC_CMD_V2_EXTN_IN msgrequest */
#define MC_CMD_V2_EXTN_IN_LEN 4
@@ -16417,6 +17895,7 @@
* Allocate a pacer bucket (for qau rp or a snapper test)
*/
#define MC_CMD_TCM_BUCKET_ALLOC 0xb2
+#define MC_CMD_TCM_BUCKET_ALLOC_MSGSET 0xb2
#undef MC_CMD_0xb2_PRIVILEGE_CTG
#define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16436,6 +17915,7 @@
* Free a pacer bucket
*/
#define MC_CMD_TCM_BUCKET_FREE 0xb3
+#define MC_CMD_TCM_BUCKET_FREE_MSGSET 0xb3
#undef MC_CMD_0xb3_PRIVILEGE_CTG
#define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16455,6 +17935,7 @@
* Initialise pacer bucket with a given rate
*/
#define MC_CMD_TCM_BUCKET_INIT 0xb4
+#define MC_CMD_TCM_BUCKET_INIT_MSGSET 0xb4
#undef MC_CMD_0xb4_PRIVILEGE_CTG
#define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16489,6 +17970,7 @@
* Initialise txq in pacer with given options or set options
*/
#define MC_CMD_TCM_TXQ_INIT 0xb5
+#define MC_CMD_TCM_TXQ_INIT_MSGSET 0xb5
#undef MC_CMD_0xb5_PRIVILEGE_CTG
#define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16579,6 +18061,7 @@
* Link a push I/O buffer to a TxQ
*/
#define MC_CMD_LINK_PIOBUF 0x92
+#define MC_CMD_LINK_PIOBUF_MSGSET 0x92
#undef MC_CMD_0x92_PRIVILEGE_CTG
#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -16588,7 +18071,7 @@
/* Handle for allocated push I/O buffer. */
#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
-/* Function Local Instance (VI) number. */
+/* Function Local Instance (VI) number which has a TxQ allocated to it. */
#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
@@ -16601,6 +18084,7 @@
* Unlink a push I/O buffer from a TxQ
*/
#define MC_CMD_UNLINK_PIOBUF 0x93
+#define MC_CMD_UNLINK_PIOBUF_MSGSET 0x93
#undef MC_CMD_0x93_PRIVILEGE_CTG
#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -16620,6 +18104,7 @@
* allocate and initialise a v-switch.
*/
#define MC_CMD_VSWITCH_ALLOC 0x94
+#define MC_CMD_VSWITCH_ALLOC_MSGSET 0x94
#undef MC_CMD_0x94_PRIVILEGE_CTG
#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16667,6 +18152,7 @@
* de-allocate a v-switch.
*/
#define MC_CMD_VSWITCH_FREE 0x95
+#define MC_CMD_VSWITCH_FREE_MSGSET 0x95
#undef MC_CMD_0x95_PRIVILEGE_CTG
#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16688,6 +18174,7 @@
* not, then the command returns ENOENT).
*/
#define MC_CMD_VSWITCH_QUERY 0x63
+#define MC_CMD_VSWITCH_QUERY_MSGSET 0x63
#undef MC_CMD_0x63_PRIVILEGE_CTG
#define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16707,6 +18194,7 @@
* allocate a v-port.
*/
#define MC_CMD_VPORT_ALLOC 0x96
+#define MC_CMD_VPORT_ALLOC_MSGSET 0x96
#undef MC_CMD_0x96_PRIVILEGE_CTG
#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16774,6 +18262,7 @@
* de-allocate a v-port.
*/
#define MC_CMD_VPORT_FREE 0x97
+#define MC_CMD_VPORT_FREE_MSGSET 0x97
#undef MC_CMD_0x97_PRIVILEGE_CTG
#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16793,6 +18282,7 @@
* allocate a v-adaptor.
*/
#define MC_CMD_VADAPTOR_ALLOC 0x98
+#define MC_CMD_VADAPTOR_ALLOC_MSGSET 0x98
#undef MC_CMD_0x98_PRIVILEGE_CTG
#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16841,6 +18331,7 @@
* de-allocate a v-adaptor.
*/
#define MC_CMD_VADAPTOR_FREE 0x99
+#define MC_CMD_VADAPTOR_FREE_MSGSET 0x99
#undef MC_CMD_0x99_PRIVILEGE_CTG
#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16860,6 +18351,7 @@
* assign a new MAC address to a v-adaptor.
*/
#define MC_CMD_VADAPTOR_SET_MAC 0x5d
+#define MC_CMD_VADAPTOR_SET_MAC_MSGSET 0x5d
#undef MC_CMD_0x5d_PRIVILEGE_CTG
#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16882,6 +18374,7 @@
* read the MAC address assigned to a v-adaptor.
*/
#define MC_CMD_VADAPTOR_GET_MAC 0x5e
+#define MC_CMD_VADAPTOR_GET_MAC_MSGSET 0x5e
#undef MC_CMD_0x5e_PRIVILEGE_CTG
#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16904,6 +18397,7 @@
* read some config of v-adaptor.
*/
#define MC_CMD_VADAPTOR_QUERY 0x61
+#define MC_CMD_VADAPTOR_QUERY_MSGSET 0x61
#undef MC_CMD_0x61_PRIVILEGE_CTG
#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16932,6 +18426,7 @@
* assign a port to a PCI function.
*/
#define MC_CMD_EVB_PORT_ASSIGN 0x9a
+#define MC_CMD_EVB_PORT_ASSIGN_MSGSET 0x9a
#undef MC_CMD_0x9a_PRIVILEGE_CTG
#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16960,6 +18455,7 @@
* Assign the 64 bit region addresses.
*/
#define MC_CMD_RDWR_A64_REGIONS 0x9b
+#define MC_CMD_RDWR_A64_REGIONS_MSGSET 0x9b
#undef MC_CMD_0x9b_PRIVILEGE_CTG
#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -16999,6 +18495,7 @@
* Allocate an Onload stack ID.
*/
#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
+#define MC_CMD_ONLOAD_STACK_ALLOC_MSGSET 0x9c
#undef MC_CMD_0x9c_PRIVILEGE_CTG
#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -17021,6 +18518,7 @@
* Free an Onload stack ID.
*/
#define MC_CMD_ONLOAD_STACK_FREE 0x9d
+#define MC_CMD_ONLOAD_STACK_FREE_MSGSET 0x9d
#undef MC_CMD_0x9d_PRIVILEGE_CTG
#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -17040,6 +18538,7 @@
* Allocate an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
+#define MC_CMD_RSS_CONTEXT_ALLOC_MSGSET 0x9e
#undef MC_CMD_0x9e_PRIVILEGE_CTG
#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17140,6 +18639,7 @@
* Free an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_FREE 0x9f
+#define MC_CMD_RSS_CONTEXT_FREE_MSGSET 0x9f
#undef MC_CMD_0x9f_PRIVILEGE_CTG
#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17159,6 +18659,7 @@
* Set the Toeplitz hash key for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
+#define MC_CMD_RSS_CONTEXT_SET_KEY_MSGSET 0xa0
#undef MC_CMD_0xa0_PRIVILEGE_CTG
#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17181,6 +18682,7 @@
* Get the Toeplitz hash key for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
+#define MC_CMD_RSS_CONTEXT_GET_KEY_MSGSET 0xa1
#undef MC_CMD_0xa1_PRIVILEGE_CTG
#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17205,6 +18707,7 @@
* when the RSS context is allocated without specifying a table size.
*/
#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
+#define MC_CMD_RSS_CONTEXT_SET_TABLE_MSGSET 0xa2
#undef MC_CMD_0xa2_PRIVILEGE_CTG
#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17229,6 +18732,7 @@
* when the RSS context is allocated without specifying a table size.
*/
#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
+#define MC_CMD_RSS_CONTEXT_GET_TABLE_MSGSET 0xa3
#undef MC_CMD_0xa3_PRIVILEGE_CTG
#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17253,6 +18757,7 @@
* RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
*/
#define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e
+#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_MSGSET 0x13e
#undef MC_CMD_0x13e_PRIVILEGE_CTG
#define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17299,6 +18804,7 @@
* RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
*/
#define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f
+#define MC_CMD_RSS_CONTEXT_READ_TABLE_MSGSET 0x13f
#undef MC_CMD_0x13f_PRIVILEGE_CTG
#define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17338,6 +18844,7 @@
* Set various control flags for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
+#define MC_CMD_RSS_CONTEXT_SET_FLAGS_MSGSET 0xe1
#undef MC_CMD_0xe1_PRIVILEGE_CTG
#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17404,6 +18911,7 @@
* Get various control flags for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
+#define MC_CMD_RSS_CONTEXT_GET_FLAGS_MSGSET 0xe2
#undef MC_CMD_0xe2_PRIVILEGE_CTG
#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17471,6 +18979,7 @@
* Allocate a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
+#define MC_CMD_DOT1P_MAPPING_ALLOC_MSGSET 0xa4
#undef MC_CMD_0xa4_PRIVILEGE_CTG
#define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17504,6 +19013,7 @@
* Free a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_FREE 0xa5
+#define MC_CMD_DOT1P_MAPPING_FREE_MSGSET 0xa5
#undef MC_CMD_0xa5_PRIVILEGE_CTG
#define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17523,6 +19033,7 @@
* Set the mapping table for a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
+#define MC_CMD_DOT1P_MAPPING_SET_TABLE_MSGSET 0xa6
#undef MC_CMD_0xa6_PRIVILEGE_CTG
#define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17547,6 +19058,7 @@
* Get the mapping table for a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
+#define MC_CMD_DOT1P_MAPPING_GET_TABLE_MSGSET 0xa7
#undef MC_CMD_0xa7_PRIVILEGE_CTG
#define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17571,6 +19083,7 @@
* Get Interrupt Vector config for this PF.
*/
#define MC_CMD_GET_VECTOR_CFG 0xbf
+#define MC_CMD_GET_VECTOR_CFG_MSGSET 0xbf
#undef MC_CMD_0xbf_PRIVILEGE_CTG
#define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17596,6 +19109,7 @@
* Set Interrupt Vector config for this PF.
*/
#define MC_CMD_SET_VECTOR_CFG 0xc0
+#define MC_CMD_SET_VECTOR_CFG_MSGSET 0xc0
#undef MC_CMD_0xc0_PRIVILEGE_CTG
#define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17623,6 +19137,7 @@
* Add a MAC address to a v-port
*/
#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
+#define MC_CMD_VPORT_ADD_MAC_ADDRESS_MSGSET 0xa8
#undef MC_CMD_0xa8_PRIVILEGE_CTG
#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17645,6 +19160,7 @@
* Delete a MAC address from a v-port
*/
#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
+#define MC_CMD_VPORT_DEL_MAC_ADDRESS_MSGSET 0xa9
#undef MC_CMD_0xa9_PRIVILEGE_CTG
#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17667,6 +19183,7 @@
* Delete a MAC address from a v-port
*/
#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
+#define MC_CMD_VPORT_GET_MAC_ADDRESSES_MSGSET 0xaa
#undef MC_CMD_0xaa_PRIVILEGE_CTG
#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17701,6 +19218,7 @@
* function will be reset before applying the changes.
*/
#define MC_CMD_VPORT_RECONFIGURE 0xeb
+#define MC_CMD_VPORT_RECONFIGURE_MSGSET 0xeb
#undef MC_CMD_0xeb_PRIVILEGE_CTG
#define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17756,6 +19274,7 @@
* read some config of v-port.
*/
#define MC_CMD_EVB_PORT_QUERY 0x62
+#define MC_CMD_EVB_PORT_QUERY_MSGSET 0x62
#undef MC_CMD_0x62_PRIVILEGE_CTG
#define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17786,6 +19305,7 @@
* lifted in future.
*/
#define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
+#define MC_CMD_DUMP_BUFTBL_ENTRIES_MSGSET 0xab
#undef MC_CMD_0xab_PRIVILEGE_CTG
#define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -17818,6 +19338,7 @@
* Set global RXDP configuration settings
*/
#define MC_CMD_SET_RXDP_CONFIG 0xc1
+#define MC_CMD_SET_RXDP_CONFIG_MSGSET 0xc1
#undef MC_CMD_0xc1_PRIVILEGE_CTG
#define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17848,6 +19369,7 @@
* Get global RXDP configuration settings
*/
#define MC_CMD_GET_RXDP_CONFIG 0xc2
+#define MC_CMD_GET_RXDP_CONFIG_MSGSET 0xc2
#undef MC_CMD_0xc2_PRIVILEGE_CTG
#define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17874,6 +19396,7 @@
* Return the system and PDCPU clock frequencies.
*/
#define MC_CMD_GET_CLOCK 0xac
+#define MC_CMD_GET_CLOCK_MSGSET 0xac
#undef MC_CMD_0xac_PRIVILEGE_CTG
#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17896,6 +19419,7 @@
* Control the system and DPCPU clock frequencies. Changes are lost reboot.
*/
#define MC_CMD_SET_CLOCK 0xad
+#define MC_CMD_SET_CLOCK_MSGSET 0xad
#undef MC_CMD_0xad_PRIVILEGE_CTG
#define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -17982,6 +19506,7 @@
* Send an arbitrary DPCPU message.
*/
#define MC_CMD_DPCPU_RPC 0xae
+#define MC_CMD_DPCPU_RPC_MSGSET 0xae
#undef MC_CMD_0xae_PRIVILEGE_CTG
#define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18100,6 +19625,7 @@
* Trigger an interrupt by prodding the BIU.
*/
#define MC_CMD_TRIGGER_INTERRUPT 0xe3
+#define MC_CMD_TRIGGER_INTERRUPT_MSGSET 0xe3
#undef MC_CMD_0xe3_PRIVILEGE_CTG
#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18119,6 +19645,7 @@
* Special operations to support (for now) shmboot.
*/
#define MC_CMD_SHMBOOT_OP 0xe6
+#define MC_CMD_SHMBOOT_OP_MSGSET 0xe6
#undef MC_CMD_0xe6_PRIVILEGE_CTG
#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -18140,6 +19667,7 @@
* Read multiple 64bit words from capture block memory
*/
#define MC_CMD_CAP_BLK_READ 0xe7
+#define MC_CMD_CAP_BLK_READ_MSGSET 0xe7
#undef MC_CMD_0xe7_PRIVILEGE_CTG
#define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18162,7 +19690,13 @@
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LEN 4
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LBN 0
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_WIDTH 32
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LEN 4
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LBN 32
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_WIDTH 32
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM_MCDI2 127
@@ -18173,6 +19707,7 @@
* Take a dump of the DUT state
*/
#define MC_CMD_DUMP_DO 0xe8
+#define MC_CMD_DUMP_DO_MSGSET 0xe8
#undef MC_CMD_0xe8_PRIVILEGE_CTG
#define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18253,6 +19788,7 @@
* Configure unsolicited dumps
*/
#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
+#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_MSGSET 0xe9
#undef MC_CMD_0xe9_PRIVILEGE_CTG
#define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18322,6 +19858,7 @@
* the parameter is out of range.
*/
#define MC_CMD_SET_PSU 0xea
+#define MC_CMD_SET_PSU_MSGSET 0xea
#undef MC_CMD_0xea_PRIVILEGE_CTG
#define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18348,6 +19885,7 @@
* Get function information. PF and VF number.
*/
#define MC_CMD_GET_FUNCTION_INFO 0xec
+#define MC_CMD_GET_FUNCTION_INFO_MSGSET 0xec
#undef MC_CMD_0xec_PRIVILEGE_CTG
#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18370,6 +19908,7 @@
* reboot.
*/
#define MC_CMD_ENABLE_OFFLINE_BIST 0xed
+#define MC_CMD_ENABLE_OFFLINE_BIST_MSGSET 0xed
#undef MC_CMD_0xed_PRIVILEGE_CTG
#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -18388,6 +19927,7 @@
* forget.
*/
#define MC_CMD_UART_SEND_DATA 0xee
+#define MC_CMD_UART_SEND_DATA_MSGSET 0xee
#undef MC_CMD_0xee_PRIVILEGE_CTG
#define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18426,6 +19966,7 @@
* subject to change and not currently implemented.
*/
#define MC_CMD_UART_RECV_DATA 0xef
+#define MC_CMD_UART_RECV_DATA_MSGSET 0xef
#undef MC_CMD_0xef_PRIVILEGE_CTG
#define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18475,6 +20016,7 @@
* Read data programmed into the device One-Time-Programmable (OTP) Fuses
*/
#define MC_CMD_READ_FUSES 0xf0
+#define MC_CMD_READ_FUSES_MSGSET 0xf0
#undef MC_CMD_0xf0_PRIVILEGE_CTG
#define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18510,6 +20052,7 @@
* Get or set KR Serdes RXEQ and TX Driver settings
*/
#define MC_CMD_KR_TUNE 0xf1
+#define MC_CMD_KR_TUNE_MSGSET 0xf1
#undef MC_CMD_0xf1_PRIVILEGE_CTG
#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -19066,6 +20609,7 @@
* Get or set PCIE Serdes RXEQ and TX Driver settings
*/
#define MC_CMD_PCIE_TUNE 0xf2
+#define MC_CMD_PCIE_TUNE_MSGSET 0xf2
#undef MC_CMD_0xf2_PRIVILEGE_CTG
#define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -19323,6 +20867,7 @@
* - not used for V3 licensing
*/
#define MC_CMD_LICENSING 0xf3
+#define MC_CMD_LICENSING_MSGSET 0xf3
#undef MC_CMD_0xf3_PRIVILEGE_CTG
#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19379,6 +20924,7 @@
* - V3 licensing (Medford)
*/
#define MC_CMD_LICENSING_V3 0xd0
+#define MC_CMD_LICENSING_V3_MSGSET 0xd0
#undef MC_CMD_0xd0_PRIVILEGE_CTG
#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19429,7 +20975,13 @@
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LBN 192
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_WIDTH 32
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LBN 224
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_WIDTH 32
/* reserved for future use */
#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
@@ -19437,7 +20989,13 @@
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LBN 448
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_WIDTH 32
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LBN 480
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_WIDTH 32
/* reserved for future use */
#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
@@ -19449,6 +21007,7 @@
* partition - V3 licensing (Medford)
*/
#define MC_CMD_LICENSING_GET_ID_V3 0xd1
+#define MC_CMD_LICENSING_GET_ID_V3_MSGSET 0xd1
#undef MC_CMD_0xd1_PRIVILEGE_CTG
#define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19482,6 +21041,7 @@
* This will fail on a single-core system.
*/
#define MC_CMD_MC2MC_PROXY 0xf4
+#define MC_CMD_MC2MC_PROXY_MSGSET 0xf4
#undef MC_CMD_0xf4_PRIVILEGE_CTG
#define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19500,6 +21060,7 @@
* or a reboot of the MC.) Not used for V3 licensing
*/
#define MC_CMD_GET_LICENSED_APP_STATE 0xf5
+#define MC_CMD_GET_LICENSED_APP_STATE_MSGSET 0xf5
#undef MC_CMD_0xf5_PRIVILEGE_CTG
#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19528,6 +21089,7 @@
* operation or a reboot of the MC.) Used for V3 licensing (Medford)
*/
#define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_MSGSET 0xd2
#undef MC_CMD_0xd2_PRIVILEGE_CTG
#define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19540,7 +21102,13 @@
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LEN 4
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LBN 0
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_WIDTH 32
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LEN 4
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LBN 32
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_WIDTH 32
/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */
#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
@@ -19560,6 +21128,7 @@
* operation or a reboot of the MC.) Used for V3 licensing (Medford)
*/
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_MSGSET 0xd3
#undef MC_CMD_0xd3_PRIVILEGE_CTG
#define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19572,7 +21141,13 @@
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LBN 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_WIDTH 32
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LBN 32
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_WIDTH 32
/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8
@@ -19580,7 +21155,13 @@
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LBN 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_WIDTH 32
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LBN 32
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_WIDTH 32
/***********************************/
@@ -19589,6 +21170,7 @@
* licensing.
*/
#define MC_CMD_LICENSED_APP_OP 0xf6
+#define MC_CMD_LICENSED_APP_OP_MSGSET 0xf6
#undef MC_CMD_0xf6_PRIVILEGE_CTG
#define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19672,6 +21254,7 @@
* (Medford)
*/
#define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_MSGSET 0xd4
#undef MC_CMD_0xd4_PRIVILEGE_CTG
#define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19685,7 +21268,13 @@
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LEN 4
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LBN 384
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_WIDTH 32
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LEN 4
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LBN 416
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_WIDTH 32
/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */
#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116
@@ -19725,6 +21314,7 @@
* Mask features - V3 licensing (Medford)
*/
#define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_MSGSET 0xd5
#undef MC_CMD_0xd5_PRIVILEGE_CTG
#define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -19735,7 +21325,13 @@
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LEN 4
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LBN 0
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_WIDTH 32
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LEN 4
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LBN 32
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_WIDTH 32
/* whether to turn on or turn off the masked features */
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
@@ -19757,6 +21353,7 @@
* erased when the adapter is power cycled
*/
#define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
+#define MC_CMD_LICENSING_V3_TEMPORARY_MSGSET 0xd6
#undef MC_CMD_0xd6_PRIVILEGE_CTG
#define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -19815,7 +21412,13 @@
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LEN 4
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LBN 32
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_WIDTH 32
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LEN 4
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LBN 64
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_WIDTH 32
/***********************************/
@@ -19827,6 +21430,7 @@
* delivered to a specific queue, or a set of queues with RSS.
*/
#define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
+#define MC_CMD_SET_PORT_SNIFF_CONFIG_MSGSET 0xf7
#undef MC_CMD_0xf7_PRIVILEGE_CTG
#define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -19870,6 +21474,7 @@
* the configuration.
*/
#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
+#define MC_CMD_GET_PORT_SNIFF_CONFIG_MSGSET 0xf8
#undef MC_CMD_0xf8_PRIVILEGE_CTG
#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19908,6 +21513,7 @@
* Change configuration related to the parser-dispatcher subsystem.
*/
#define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
+#define MC_CMD_SET_PARSER_DISP_CONFIG_MSGSET 0xf9
#undef MC_CMD_0xf9_PRIVILEGE_CTG
#define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19953,6 +21559,7 @@
* Read configuration related to the parser-dispatcher subsystem.
*/
#define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
+#define MC_CMD_GET_PARSER_DISP_CONFIG_MSGSET 0xfa
#undef MC_CMD_0xfa_PRIVILEGE_CTG
#define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19997,6 +21604,7 @@
* dedicated as TX sniff receivers.
*/
#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
+#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_MSGSET 0xfb
#undef MC_CMD_0xfb_PRIVILEGE_CTG
#define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20037,6 +21645,7 @@
* the configuration.
*/
#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
+#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_MSGSET 0xfc
#undef MC_CMD_0xfc_PRIVILEGE_CTG
#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20072,6 +21681,7 @@
* Per queue rx error stats.
*/
#define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
+#define MC_CMD_RMON_STATS_RX_ERRORS_MSGSET 0xfe
#undef MC_CMD_0xfe_PRIVILEGE_CTG
#define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20104,6 +21714,7 @@
* Find out about available PCIE resources
*/
#define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
+#define MC_CMD_GET_PCIE_RESOURCE_INFO_MSGSET 0xfd
#undef MC_CMD_0xfd_PRIVILEGE_CTG
#define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20143,6 +21754,7 @@
* Find out about available port modes
*/
#define MC_CMD_GET_PORT_MODES 0xff
+#define MC_CMD_GET_PORT_MODES_MSGSET 0xff
#undef MC_CMD_0xff_PRIVILEGE_CTG
#define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20199,6 +21811,7 @@
* the new port mode, as the override does not affect PF configuration.
*/
#define MC_CMD_OVERRIDE_PORT_MODE 0x137
+#define MC_CMD_OVERRIDE_PORT_MODE_MSGSET 0x137
#undef MC_CMD_0x137_PRIVILEGE_CTG
#define MC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20223,6 +21836,7 @@
* Sample voltages on the ATB
*/
#define MC_CMD_READ_ATB 0x100
+#define MC_CMD_READ_ATB_MSGSET 0x100
#undef MC_CMD_0x100_PRIVILEGE_CTG
#define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20253,6 +21867,7 @@
* enums here must correspond with those in MC_CMD_WORKAROUND.
*/
#define MC_CMD_GET_WORKAROUNDS 0x59
+#define MC_CMD_GET_WORKAROUNDS_MSGSET 0x59
#undef MC_CMD_0x59_PRIVILEGE_CTG
#define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20290,6 +21905,7 @@
* Read/set privileges of an arbitrary PCIe function
*/
#define MC_CMD_PRIVILEGE_MASK 0x5a
+#define MC_CMD_PRIVILEGE_MASK_MSGSET 0x5a
#undef MC_CMD_0x5a_PRIVILEGE_CTG
#define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20351,6 +21967,20 @@
#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
/* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */
#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000
+/* enum: This Function/client may call MC_CMD_CLIENT_ALLOC to create new
+ * dynamic client children of itself.
+ */
+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALLOC_CLIENT 0x20000
+/* enum: A dynamic client with this privilege may perform all the same DMA
+ * operations as the function client from which it is descended.
+ */
+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_FUNC_DMA 0x40000
+/* enum: A client with this privilege may perform DMA as any PCIe function on
+ * the device and to on-device DDR. It allows clients to use TX-DESC2CMPT-DESC
+ * descriptors, and to use TX-SEG-DESC and TX-MEM2MEM-DESC with an address
+ * space override (i.e. with the ADDR_SPC_EN bit set).
+ */
+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ARBITRARY_DMA 0x80000
/* enum: Set this bit to indicate that a new privilege mask is to be set,
* otherwise the command will only read the existing mask.
*/
@@ -20368,6 +21998,7 @@
* Read/set link state mode of a VF
*/
#define MC_CMD_LINK_STATE_MODE 0x5c
+#define MC_CMD_LINK_STATE_MODE_MSGSET 0x5c
#undef MC_CMD_0x5c_PRIVILEGE_CTG
#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20407,6 +22038,7 @@
* parameter to MC_CMD_INIT_RXQ.
*/
#define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
+#define MC_CMD_GET_SNAPSHOT_LENGTH_MSGSET 0x101
#undef MC_CMD_0x101_PRIVILEGE_CTG
#define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20429,6 +22061,7 @@
* Additional fuse diagnostics
*/
#define MC_CMD_FUSE_DIAGS 0x102
+#define MC_CMD_FUSE_DIAGS_MSGSET 0x102
#undef MC_CMD_0x102_PRIVILEGE_CTG
#define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20483,6 +22116,7 @@
* included in one of the masks provided.
*/
#define MC_CMD_PRIVILEGE_MODIFY 0x60
+#define MC_CMD_PRIVILEGE_MODIFY_MSGSET 0x60
#undef MC_CMD_0x60_PRIVILEGE_CTG
#define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20527,6 +22161,7 @@
* Read XPM memory
*/
#define MC_CMD_XPM_READ_BYTES 0x103
+#define MC_CMD_XPM_READ_BYTES_MSGSET 0x103
#undef MC_CMD_0x103_PRIVILEGE_CTG
#define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20559,6 +22194,7 @@
* Write XPM memory
*/
#define MC_CMD_XPM_WRITE_BYTES 0x104
+#define MC_CMD_XPM_WRITE_BYTES_MSGSET 0x104
#undef MC_CMD_0x104_PRIVILEGE_CTG
#define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20591,6 +22227,7 @@
* Read XPM sector
*/
#define MC_CMD_XPM_READ_SECTOR 0x105
+#define MC_CMD_XPM_READ_SECTOR_MSGSET 0x105
#undef MC_CMD_0x105_PRIVILEGE_CTG
#define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20631,6 +22268,7 @@
* Write XPM sector
*/
#define MC_CMD_XPM_WRITE_SECTOR 0x106
+#define MC_CMD_XPM_WRITE_SECTOR_MSGSET 0x106
#undef MC_CMD_0x106_PRIVILEGE_CTG
#define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20677,6 +22315,7 @@
* Invalidate XPM sector
*/
#define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
+#define MC_CMD_XPM_INVALIDATE_SECTOR_MSGSET 0x107
#undef MC_CMD_0x107_PRIVILEGE_CTG
#define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20696,6 +22335,7 @@
* Blank-check XPM memory and report bad locations
*/
#define MC_CMD_XPM_BLANK_CHECK 0x108
+#define MC_CMD_XPM_BLANK_CHECK_MSGSET 0x108
#undef MC_CMD_0x108_PRIVILEGE_CTG
#define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20733,6 +22373,7 @@
* Blank-check and repair XPM memory
*/
#define MC_CMD_XPM_REPAIR 0x109
+#define MC_CMD_XPM_REPAIR_MSGSET 0x109
#undef MC_CMD_0x109_PRIVILEGE_CTG
#define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20756,6 +22397,7 @@
* be performed on an unprogrammed part.
*/
#define MC_CMD_XPM_DECODER_TEST 0x10a
+#define MC_CMD_XPM_DECODER_TEST_MSGSET 0x10a
#undef MC_CMD_0x10a_PRIVILEGE_CTG
#define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20776,6 +22418,7 @@
* first available location to use, or fail with ENOSPC if none left.
*/
#define MC_CMD_XPM_WRITE_TEST 0x10b
+#define MC_CMD_XPM_WRITE_TEST_MSGSET 0x10b
#undef MC_CMD_0x10b_PRIVILEGE_CTG
#define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20797,6 +22440,7 @@
* does match, otherwise it will respond with success before it jumps to IMEM.
*/
#define MC_CMD_EXEC_SIGNED 0x10c
+#define MC_CMD_EXEC_SIGNED_MSGSET 0x10c
#undef MC_CMD_0x10c_PRIVILEGE_CTG
#define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -20827,6 +22471,7 @@
* MC_CMD_EXEC_SIGNED.
*/
#define MC_CMD_PREPARE_SIGNED 0x10d
+#define MC_CMD_PREPARE_SIGNED_MSGSET 0x10d
#undef MC_CMD_0x10d_PRIVILEGE_CTG
#define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -20850,6 +22495,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_SET_SECURITY_RULE 0x10f
+#define MC_CMD_SET_SECURITY_RULE_MSGSET 0x10f
#undef MC_CMD_0x10f_PRIVILEGE_CTG
#define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21040,6 +22686,7 @@
* development. This note will be removed once it is regarded as stable.
*/
#define MC_CMD_RESET_SECURITY_RULES 0x110
+#define MC_CMD_RESET_SECURITY_RULES_MSGSET 0x110
#undef MC_CMD_0x110_PRIVILEGE_CTG
#define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21066,6 +22713,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111
+#define MC_CMD_GET_SECURITY_RULESET_VERSION_MSGSET 0x111
#undef MC_CMD_0x111_PRIVILEGE_CTG
#define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -21096,6 +22744,7 @@
* removed once it is regarded as stable.
*/
#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112
+#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_MSGSET 0x112
#undef MC_CMD_0x112_PRIVILEGE_CTG
#define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21134,6 +22783,7 @@
* removed once it is regarded as stable.
*/
#define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113
+#define MC_CMD_SECURITY_RULE_COUNTER_FREE_MSGSET 0x113
#undef MC_CMD_0x113_PRIVILEGE_CTG
#define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21169,6 +22819,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_SUBNET_MAP_SET_NODE 0x114
+#define MC_CMD_SUBNET_MAP_SET_NODE_MSGSET 0x114
#undef MC_CMD_0x114_PRIVILEGE_CTG
#define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21224,6 +22875,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115
+#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_MSGSET 0x115
#undef MC_CMD_0x115_PRIVILEGE_CTG
#define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21258,6 +22910,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116
+#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_MSGSET 0x116
#undef MC_CMD_0x116_PRIVILEGE_CTG
#define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21311,6 +22964,7 @@
* cause all functions to see a reset. (Available on Medford only.)
*/
#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
+#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_MSGSET 0x117
#undef MC_CMD_0x117_PRIVILEGE_CTG
#define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -21357,6 +23011,7 @@
* priority.
*/
#define MC_CMD_RX_BALANCING 0x118
+#define MC_CMD_RX_BALANCING_MSGSET 0x118
#undef MC_CMD_0x118_PRIVILEGE_CTG
#define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21386,6 +23041,7 @@
* info in respect to the binding protocol.
*/
#define MC_CMD_TSA_BIND 0x119
+#define MC_CMD_TSA_BIND_MSGSET 0x119
#undef MC_CMD_0x119_PRIVILEGE_CTG
#define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -21951,6 +23607,7 @@
* OP_GET_CACHED_VERSION. All other sub-operations are prohibited.
*/
#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a
+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_MSGSET 0x11a
#undef MC_CMD_0x11a_PRIVILEGE_CTG
#define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22007,6 +23664,7 @@
* if the tag is already present.
*/
#define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
+#define MC_CMD_NVRAM_PRIVATE_APPEND_MSGSET 0x11c
#undef MC_CMD_0x11c_PRIVILEGE_CTG
#define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22041,6 +23699,7 @@
* correctly at ATE.
*/
#define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
+#define MC_CMD_XPM_VERIFY_CONTENTS_MSGSET 0x11b
#undef MC_CMD_0x11b_PRIVILEGE_CTG
#define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22084,6 +23743,7 @@
* and TMR_RELOAD_ACT_NS).
*/
#define MC_CMD_SET_EVQ_TMR 0x120
+#define MC_CMD_SET_EVQ_TMR_MSGSET 0x120
#undef MC_CMD_0x120_PRIVILEGE_CTG
#define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22122,6 +23782,7 @@
* Query properties about the event queue timers.
*/
#define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
+#define MC_CMD_GET_EVQ_TMR_PROPERTIES_MSGSET 0x122
#undef MC_CMD_0x122_PRIVILEGE_CTG
#define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22191,6 +23852,7 @@
* non used switch buffers.
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_MSGSET 0x11d
#undef MC_CMD_0x11d_PRIVILEGE_CTG
#define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22198,7 +23860,8 @@
/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
@@ -22243,6 +23906,7 @@
* previously allocated common pools.
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_MSGSET 0x11e
#undef MC_CMD_0x11e_PRIVILEGE_CTG
#define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22296,6 +23960,7 @@
* ready to be re-used.
*/
#define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
+#define MC_CMD_TEARDOWN_TX_VFIFO_VF_MSGSET 0x11f
#undef MC_CMD_0x11f_PRIVILEGE_CTG
#define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22316,6 +23981,7 @@
* it ready to be re-used.
*/
#define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
+#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_MSGSET 0x121
#undef MC_CMD_0x121_PRIVILEGE_CTG
#define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22344,6 +24010,7 @@
* or 0 if there has not been a previous rekey.
*/
#define MC_CMD_REKEY 0x123
+#define MC_CMD_REKEY_MSGSET 0x123
#undef MC_CMD_0x123_PRIVILEGE_CTG
#define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22368,6 +24035,7 @@
* not yet assigned.
*/
#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
+#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_MSGSET 0x124
#undef MC_CMD_0x124_PRIVILEGE_CTG
#define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22396,6 +24064,7 @@
* the required bits were not set.
*/
#define MC_CMD_SET_SECURITY_FUSES 0x126
+#define MC_CMD_SET_SECURITY_FUSES_MSGSET 0x126
#undef MC_CMD_0x126_PRIVILEGE_CTG
#define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22438,6 +24107,7 @@
* SF-117371-SW
*/
#define MC_CMD_TSA_INFO 0x127
+#define MC_CMD_TSA_INFO_MSGSET 0x127
#undef MC_CMD_0x127_PRIVILEGE_CTG
#define MC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22614,6 +24284,7 @@
* Doxbox reference SF-117371-SW
*/
#define MC_CMD_HOST_INFO 0x128
+#define MC_CMD_HOST_INFO_MSGSET 0x128
#undef MC_CMD_0x128_PRIVILEGE_CTG
#define MC_CMD_0x128_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22681,6 +24352,7 @@
* section 'Adapter Information'
*/
#define MC_CMD_TSAN_INFO 0x129
+#define MC_CMD_TSAN_INFO_MSGSET 0x129
#undef MC_CMD_0x129_PRIVILEGE_CTG
#define MC_CMD_0x129_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22780,6 +24452,7 @@
* TSA adapter statistics operations.
*/
#define MC_CMD_TSA_STATISTICS 0x130
+#define MC_CMD_TSA_STATISTICS_MSGSET 0x130
#undef MC_CMD_0x130_PRIVILEGE_CTG
#define MC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22884,14 +24557,26 @@
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LEN 8
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_LBN 0
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_OFST 4
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_LBN 32
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_WIDTH 64
/* Rx statistics counter */
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_OFST 8
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LEN 8
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_OFST 8
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_LBN 64
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_OFST 12
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_LBN 96
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64
@@ -22904,6 +24589,7 @@
* installing TSA binding certificates. See SF-117631-TC.
*/
#define MC_CMD_ERASE_INITIAL_NIC_SECRET 0x131
+#define MC_CMD_ERASE_INITIAL_NIC_SECRET_MSGSET 0x131
#undef MC_CMD_0x131_PRIVILEGE_CTG
#define MC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22921,6 +24607,7 @@
* NIC for TSA binding.
*/
#define MC_CMD_TSA_CONFIG 0x64
+#define MC_CMD_TSA_CONFIG_MSGSET 0x64
#undef MC_CMD_0x64_PRIVILEGE_CTG
#define MC_CMD_0x64_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23038,6 +24725,7 @@
* to a TSA adapter.
*/
#define MC_CMD_TSA_IPADDR 0x65
+#define MC_CMD_TSA_IPADDR_MSGSET 0x65
#undef MC_CMD_0x65_PRIVILEGE_CTG
#define MC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23089,7 +24777,13 @@
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_OFST 8
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LEN 8
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_OFST 8
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_LBN 64
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_OFST 12
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_LBN 96
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MINNUM 1
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM 30
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM_MCDI2 126
@@ -23119,7 +24813,13 @@
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_OFST 8
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LEN 8
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_OFST 8
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_LBN 64
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_OFST 12
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_LBN 96
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MINNUM 1
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM 30
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM_MCDI2 126
@@ -23135,6 +24835,7 @@
* disabled.
*/
#define MC_CMD_SECURE_NIC_INFO 0x132
+#define MC_CMD_SECURE_NIC_INFO_MSGSET 0x132
#undef MC_CMD_0x132_PRIVILEGE_CTG
#define MC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23228,6 +24929,7 @@
* parameters in request or response.
*/
#define MC_CMD_TSA_TEST 0x125
+#define MC_CMD_TSA_TEST_MSGSET 0x125
#undef MC_CMD_0x125_PRIVILEGE_CTG
#define MC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23249,6 +24951,7 @@
* rule-set transitions.
*/
#define MC_CMD_TSA_RULESET_OVERRIDE 0x12a
+#define MC_CMD_TSA_RULESET_OVERRIDE_MSGSET 0x12a
#undef MC_CMD_0x12a_PRIVILEGE_CTG
#define MC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23281,6 +24984,7 @@
* Specific usage is determined by the TYPE field.
*/
#define MC_CMD_TSAC_REQUEST 0x12b
+#define MC_CMD_TSAC_REQUEST_MSGSET 0x12b
#undef MC_CMD_0x12b_PRIVILEGE_CTG
#define MC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23305,6 +25009,7 @@
* Get the version of the SUC
*/
#define MC_CMD_SUC_VERSION 0x134
+#define MC_CMD_SUC_VERSION_MSGSET 0x134
#undef MC_CMD_0x134_PRIVILEGE_CTG
#define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23350,6 +25055,7 @@
* Operations to support manftest on SUC based systems.
*/
#define MC_CMD_SUC_MANFTEST 0x135
+#define MC_CMD_SUC_MANFTEST_MSGSET 0x135
#undef MC_CMD_0x135_PRIVILEGE_CTG
#define MC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23546,6 +25252,7 @@
* Request a certificate.
*/
#define MC_CMD_GET_CERTIFICATE 0x12c
+#define MC_CMD_GET_CERTIFICATE_MSGSET 0x12c
#undef MC_CMD_0x12c_PRIVILEGE_CTG
#define MC_CMD_0x12c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23620,6 +25327,7 @@
* Get a global value which applies to all PCI functions
*/
#define MC_CMD_GET_NIC_GLOBAL 0x12d
+#define MC_CMD_GET_NIC_GLOBAL_MSGSET 0x12d
#undef MC_CMD_0x12d_PRIVILEGE_CTG
#define MC_CMD_0x12d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23647,6 +25355,7 @@
* appropriate error otherwise (see key descriptions).
*/
#define MC_CMD_SET_NIC_GLOBAL 0x12e
+#define MC_CMD_SET_NIC_GLOBAL_MSGSET 0x12e
#undef MC_CMD_0x12e_PRIVILEGE_CTG
#define MC_CMD_0x12e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23694,6 +25403,7 @@
* firmware buffer for later extraction.
*/
#define MC_CMD_LTSSM_TRACE_POLL 0x12f
+#define MC_CMD_LTSSM_TRACE_POLL_MSGSET 0x12f
#undef MC_CMD_0x12f_PRIVILEGE_CTG
#define MC_CMD_0x12f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23731,7 +25441,13 @@
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_OFST 8
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LEN 8
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_OFST 8
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_LEN 4
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_LBN 64
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_WIDTH 32
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_OFST 12
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_LEN 4
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_LBN 96
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_WIDTH 32
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MINNUM 0
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM 30
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM_MCDI2 126
@@ -23765,6 +25481,7 @@
* firmware variant.
*/
#define MC_CMD_TELEMETRY_ENABLE 0x138
+#define MC_CMD_TELEMETRY_ENABLE_MSGSET 0x138
#undef MC_CMD_0x138_PRIVILEGE_CTG
#define MC_CMD_0x138_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23856,6 +25573,7 @@
* Reference - SF-120569-SW Telemetry Firmware Design.
*/
#define MC_CMD_TELEMETRY_CONFIG 0x139
+#define MC_CMD_TELEMETRY_CONFIG_MSGSET 0x139
#undef MC_CMD_0x139_PRIVILEGE_CTG
#define MC_CMD_0x139_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23925,6 +25643,7 @@
* due to resource constraints, returns ENOSPC.
*/
#define MC_CMD_GET_RX_PREFIX_ID 0x13b
+#define MC_CMD_GET_RX_PREFIX_ID_MSGSET 0x13b
#undef MC_CMD_0x13b_PRIVILEGE_CTG
#define MC_CMD_0x13b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23935,7 +25654,13 @@
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LEN 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LBN 0
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_WIDTH 32
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LEN 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LBN 32
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_WIDTH 32
#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0
#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0
#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1
@@ -24056,6 +25781,7 @@
* created with that prefix id
*/
#define MC_CMD_QUERY_RX_PREFIX_ID 0x13c
+#define MC_CMD_QUERY_RX_PREFIX_ID_MSGSET 0x13c
#undef MC_CMD_0x13c_PRIVILEGE_CTG
#define MC_CMD_0x13c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24092,6 +25818,7 @@
* A command to perform various bundle-related operations on insecure cards.
*/
#define MC_CMD_BUNDLE 0x13d
+#define MC_CMD_BUNDLE_MSGSET 0x13d
#undef MC_CMD_0x13d_PRIVILEGE_CTG
#define MC_CMD_0x13d_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -24154,6 +25881,7 @@
* Read all VPD starting from a given address
*/
#define MC_CMD_GET_VPD 0x165
+#define MC_CMD_GET_VPD_MSGSET 0x165
#undef MC_CMD_0x165_PRIVILEGE_CTG
#define MC_CMD_0x165_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24185,6 +25913,7 @@
* Provide information about the NC-SI stack
*/
#define MC_CMD_GET_NCSI_INFO 0x167
+#define MC_CMD_GET_NCSI_INFO_MSGSET 0x167
#undef MC_CMD_0x167_PRIVILEGE_CTG
#define MC_CMD_0x167_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24256,6 +25985,7 @@
* System lockdown, when enabled firmware updates are blocked.
*/
#define MC_CMD_FIRMWARE_SET_LOCKDOWN 0x16f
+#define MC_CMD_FIRMWARE_SET_LOCKDOWN_MSGSET 0x16f
#undef MC_CMD_0x16f_PRIVILEGE_CTG
#define MC_CMD_0x16f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -24278,6 +26008,7 @@
* documentation.
*/
#define MC_CMD_GET_TEST_FEATURES 0x1ac
+#define MC_CMD_GET_TEST_FEATURES_MSGSET 0x1ac
#undef MC_CMD_0x1ac_PRIVILEGE_CTG
#define MC_CMD_0x1ac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24300,6 +26031,253 @@
#define MC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM 63
#define MC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM_MCDI2 255
+
+/***********************************/
+/* MC_CMD_FPGA
+ * A command to perform various fpga-related operations on platforms that
+ * include FPGAs. Note that some platforms may only support a subset of these
+ * operations.
+ */
+#define MC_CMD_FPGA 0x1bf
+#define MC_CMD_FPGA_MSGSET 0x1bf
+#undef MC_CMD_0x1bf_PRIVILEGE_CTG
+
+#define MC_CMD_0x1bf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FPGA_IN msgrequest */
+#define MC_CMD_FPGA_IN_LEN 4
+/* Sub-command code */
+#define MC_CMD_FPGA_IN_OP_OFST 0
+#define MC_CMD_FPGA_IN_OP_LEN 4
+/* enum: Get the FPGA version string. */
+#define MC_CMD_FPGA_IN_OP_GET_VERSION 0x0
+/* enum: Read bitmask of features supported in the FPGA image. */
+#define MC_CMD_FPGA_IN_OP_GET_CAPABILITIES 0x1
+/* enum: Perform a FPGA reset. */
+#define MC_CMD_FPGA_IN_OP_RESET 0x2
+/* enum: Set active flash device. */
+#define MC_CMD_FPGA_IN_OP_SELECT_FLASH 0x3
+/* enum: Get active flash device. */
+#define MC_CMD_FPGA_IN_OP_GET_ACTIVE_FLASH 0x4
+/* enum: Configure internal link i.e. the FPGA port facing the ASIC. */
+#define MC_CMD_FPGA_IN_OP_SET_INTERNAL_LINK 0x5
+/* enum: Read internal link configuration. */
+#define MC_CMD_FPGA_IN_OP_GET_INTERNAL_LINK 0x6
+
+/* MC_CMD_FPGA_OP_GET_VERSION_IN msgrequest: Get the FPGA version string. A
+ * free-format string is returned in response to this command. Any checks on
+ * supported FPGA operations are based on the response to
+ * MC_CMD_FPGA_OP_GET_CAPABILITIES.
+ */
+#define MC_CMD_FPGA_OP_GET_VERSION_IN_LEN 4
+/* Sub-command code. Must be OP_GET_VERSION */
+#define MC_CMD_FPGA_OP_GET_VERSION_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_VERSION_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_VERSION_OUT msgresponse: Returns the version string. */
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LENMIN 0
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LENMAX 252
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LEN(num) (0+1*(num))
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_NUM(len) (((len)-0)/1)
+/* Null-terminated string containing version information. */
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_OFST 0
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_LEN 1
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MINNUM 0
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MAXNUM 252
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MAXNUM_MCDI2 1020
+
+/* MC_CMD_FPGA_OP_GET_CAPABILITIES_IN msgrequest: Read bitmask of features
+ * supported in the FPGA image.
+ */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_IN_LEN 4
+/* Sub-command code. Must be OP_GET_CAPABILITIES */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT msgresponse: Returns the version string.
+ */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_LEN 4
+/* Bit-mask of supported features. */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_CAPABILITIES_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_CAPABILITIES_LEN 4
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_LBN 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_WIDTH 1
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_LBN 1
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_WIDTH 1
+
+/* MC_CMD_FPGA_OP_RESET_IN msgrequest: Perform a FPGA reset operation where
+ * supported.
+ */
+#define MC_CMD_FPGA_OP_RESET_IN_LEN 4
+/* Sub-command code. Must be OP_RESET */
+#define MC_CMD_FPGA_OP_RESET_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_RESET_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_RESET_OUT msgresponse */
+#define MC_CMD_FPGA_OP_RESET_OUT_LEN 0
+
+/* MC_CMD_FPGA_OP_SELECT_FLASH_IN msgrequest: Set active FPGA flash device.
+ * Returns EINVAL if selected flash index does not exist on the platform under
+ * test.
+ */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_LEN 8
+/* Sub-command code. Must be OP_SELECT_FLASH */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_OP_LEN 4
+/* Flash device identifier. */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_FLASH_ID_OFST 4
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_FLASH_ID_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_FPGA_FLASH_INDEX */
+
+/* MC_CMD_FPGA_OP_SELECT_FLASH_OUT msgresponse */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_OUT_LEN 0
+
+/* MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN msgrequest: Get active FPGA flash device.
+ */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_LEN 4
+/* Sub-command code. Must be OP_GET_ACTIVE_FLASH */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT msgresponse: Returns flash identifier
+ * for current active flash.
+ */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_LEN 4
+/* Flash device identifier. */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_FLASH_ID_OFST 0
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_FLASH_ID_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_FPGA_FLASH_INDEX */
+
+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN msgrequest: Configure FPGA internal
+ * port, facing the ASIC
+ */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LEN 12
+/* Sub-command code. Must be OP_SET_INTERNAL_LINK */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_OP_LEN 4
+/* Flags */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLAGS_OFST 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLAGS_LEN 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_OFST 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_LBN 0
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_WIDTH 2
+/* enum: Unmodified, same as last state set by firmware */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_AUTO 0x0
+/* enum: Configure link-up */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_UP 0x1
+/* enum: Configure link-down */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_DOWN 0x2
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_OFST 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_LBN 2
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_WIDTH 1
+/* Link speed to be applied on FPGA internal port MAC. */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_SPEED_OFST 8
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_SPEED_LEN 4
+
+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_OUT msgresponse */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_OUT_LEN 0
+
+/* MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN msgrequest: Read FPGA internal port
+ * configuration and status
+ */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_LEN 4
+/* Sub-command code. Must be OP_GET_INTERNAL_LINK */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT msgresponse: Response format for read
+ * FPGA internal port configuration and status
+ */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LEN 8
+/* Flags */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_FLAGS_OFST 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_FLAGS_LEN 4
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_OFST 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_LBN 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_WIDTH 2
+/* Enum values, see field(s): */
+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN/FLAGS */
+/* Link speed set on FPGA internal port MAC. */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_SPEED_OFST 4
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_SPEED_LEN 4
+
+
+/***********************************/
+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE
+ * This command is expected to be used on a U25 board with an MAE in the FPGA.
+ * It does not modify the operational state of the NIC. The modes are described
+ * in XN-200039-TC - U25 OVS packet formats.
+ */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE 0x1c0
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_MSGSET 0x1c0
+#undef MC_CMD_0x1c0_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_IN msgrequest */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_IN_LEN 0
+
+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT msgresponse */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_LEN 4
+/* The current link mode */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_MODE_OFST 0
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_MODE_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_EXTERNAL_MAE_LINK_MODE */
+
+
+/***********************************/
+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE
+ * This command is expected to be used on a U25 board with an MAE in the FPGA.
+ * The modes are described in XN-200039-TC - U25 OVS packet formats. This
+ * command will set the link between the FPGA and the X2 to the specified new
+ * mode. It will first enter bootstrap mode, make sure there are no packets in
+ * flight and then enter the requested mode. In order to make sure there are no
+ * packets in flight, it will flush the X2 TX path, the FPGA RX path from the
+ * X2, the FPGA TX path to the X2 and the X2 RX path. The driver is responsible
+ * for making sure there are no TX or RX descriptors posted on any TXQ or RXQ
+ * associated with the affected port before invoking this command. This command
+ * is run implicitly with MODE set to LEGACY when MC_CMD_DRV_ATTACH is
+ * executed.
+ */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE 0x1c1
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_MSGSET 0x1c1
+#undef MC_CMD_0x1c1_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN msgrequest */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_LEN 4
+/* The new link mode. */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_MODE_OFST 0
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_MODE_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_EXTERNAL_MAE_LINK_MODE */
+
+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_OUT msgresponse */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_OUT_LEN 0
+
+/* CLIENT_HANDLE structuredef: A client is an abstract entity that can make
+ * requests of the device and that can own resources managed by the device.
+ * Examples of clients include PCIe functions and dynamic clients. A client
+ * handle is a 32b opaque value used to refer to a client. Further details can
+ * be found within XN-200418-TC.
+ */
+#define CLIENT_HANDLE_LEN 4
+#define CLIENT_HANDLE_OPAQUE_OFST 0
+#define CLIENT_HANDLE_OPAQUE_LEN 4
+/* enum: A client handle guaranteed never to refer to a real client. */
+#define CLIENT_HANDLE_NULL 0xffffffff
+/* enum: Used to refer to the calling client. */
+#define CLIENT_HANDLE_SELF 0xfffffffe
+#define CLIENT_HANDLE_OPAQUE_LBN 0
+#define CLIENT_HANDLE_OPAQUE_WIDTH 32
+
/* CLOCK_INFO structuredef: Information about a single hardware clock */
#define CLOCK_INFO_LEN 28
/* Enumeration that uniquely identifies the clock */
@@ -24333,7 +26311,13 @@
#define CLOCK_INFO_FREQUENCY_OFST 4
#define CLOCK_INFO_FREQUENCY_LEN 8
#define CLOCK_INFO_FREQUENCY_LO_OFST 4
+#define CLOCK_INFO_FREQUENCY_LO_LEN 4
+#define CLOCK_INFO_FREQUENCY_LO_LBN 32
+#define CLOCK_INFO_FREQUENCY_LO_WIDTH 32
#define CLOCK_INFO_FREQUENCY_HI_OFST 8
+#define CLOCK_INFO_FREQUENCY_HI_LEN 4
+#define CLOCK_INFO_FREQUENCY_HI_LBN 64
+#define CLOCK_INFO_FREQUENCY_HI_WIDTH 32
#define CLOCK_INFO_FREQUENCY_LBN 32
#define CLOCK_INFO_FREQUENCY_WIDTH 64
/* Human-readable ASCII name for clock, with NUL termination */
@@ -24343,12 +26327,62 @@
#define CLOCK_INFO_NAME_LBN 96
#define CLOCK_INFO_NAME_WIDTH 8
+/* SCHED_CREDIT_CHECK_RESULT structuredef */
+#define SCHED_CREDIT_CHECK_RESULT_LEN 16
+/* The instance of the scheduler. Refer to XN-200389-AW for the location of
+ * these schedulers in the hardware.
+ */
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LEN 1
+#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_A 0x0 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_A 0x1 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_B 0x2 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_C 0x3 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_TX 0x4 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_D 0x5 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_REPLAY 0x6 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_WIDTH 8
+/* The type of node that this result refers to. */
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_OFST 1
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LEN 1
+/* enum: Destination node */
+#define SCHED_CREDIT_CHECK_RESULT_DEST 0x0
+/* enum: Source node */
+#define SCHED_CREDIT_CHECK_RESULT_SOURCE 0x1
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LBN 8
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_WIDTH 8
+/* Level of node in scheduler hierarchy (level 0 is the bottom of the
+ * hierarchy, increasing towards the root node).
+ */
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_OFST 2
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LEN 2
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LBN 16
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_WIDTH 16
+/* Node index */
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_OFST 4
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LEN 4
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LBN 32
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_WIDTH 32
+/* The number of credits the node is expected to have. */
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_OFST 8
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LEN 4
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LBN 64
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_WIDTH 32
+/* The number of credits the node actually had. */
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_OFST 12
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LBN 96
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_WIDTH 32
+
/***********************************/
/* MC_CMD_GET_CLOCKS_INFO
* Get information about the device clocks
*/
#define MC_CMD_GET_CLOCKS_INFO 0x166
+#define MC_CMD_GET_CLOCKS_INFO_MSGSET 0x166
#undef MC_CMD_0x166_PRIVILEGE_CTG
#define MC_CMD_0x166_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24387,6 +26421,7 @@
* returns ENOSPC if the caller's table is full.
*/
#define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d
+#define MC_CMD_VNIC_ENCAP_RULE_ADD_MSGSET 0x16d
#undef MC_CMD_0x16d_PRIVILEGE_CTG
#define MC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24469,6 +26504,7 @@
* if the input HANDLE doesn't correspond to an existing rule.
*/
#define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e
+#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_MSGSET 0x16e
#undef MC_CMD_0x16e_PRIVILEGE_CTG
#define MC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24508,303 +26544,568 @@
#define UUID_NODE_LBN 80
#define UUID_NODE_WIDTH 48
-/* MC_CMD_DEVEL_DUMP_VI_ENTRY structuredef */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_LEN 28
-/* Type of entry */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_C2H 0x0 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_H2C 0x1 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_C2H 0x2 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_H2C 0x3 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_C2H 0x4 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_H2C 0x5 /* enum */
-/* enum: First QDMA writeback/completion queue. Used for ef100, C2H VDPA and
- * plain virtio.
- */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_WRB 0x6
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_PFTCH 0x7 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_QTBL 0x100 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_C2H_QTBL 0x101 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_VIO 0x10a /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LBN 0
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_WIDTH 32
-/* Internal QDMA/dmac queue number for this entry */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_OFST 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LBN 32
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_WIDTH 32
-/* Size of entry data */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_OFST 8
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LBN 64
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_WIDTH 32
-/* Offset of entry data from start of MCDI message response payload */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_OFST 12
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LBN 96
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_WIDTH 32
-/* Absolute VI of the entry, or 0xffffffff if not available/applicable */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_OFST 16
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_NO_ABS_VI 0xffffffff /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LBN 128
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_WIDTH 32
-/* Reserved */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_OFST 20
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LEN 8
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LO_OFST 20
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_HI_OFST 24
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LBN 160
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_WIDTH 64
-
-
-/***********************************/
-/* MC_CMD_DEVEL_DUMP_VI
- * Dump various parts of the hardware's state for a VI.
- */
-#define MC_CMD_DEVEL_DUMP_VI 0x1b5
-#undef MC_CMD_0x1b5_PRIVILEGE_CTG
-
-#define MC_CMD_0x1b5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
-
-/* MC_CMD_DEVEL_DUMP_VI_IN msgrequest */
-#define MC_CMD_DEVEL_DUMP_VI_IN_LEN 4
-/* Absolute queue id of queue to dump state for */
-#define MC_CMD_DEVEL_DUMP_VI_IN_QID_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_IN_QID_LEN 4
-
-/* MC_CMD_DEVEL_DUMP_VI_IN_V2 msgrequest */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_LEN 20
-/* Which queue to dump. The meaning of this field dependes on ADDRESS_MODE. */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ID_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ID_LEN 4
-/* Method of referring to the queue to dump */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_OFST 4
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_LEN 4
-/* enum: First field refers to queue number as understood by QDMA/DMAC hardware
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_QUEUE_NUMBER 0x0
-/* enum: First field refers to absolute VI number */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ABS_VI 0x1
-/* enum: First field refers to function-relative VI number on the command's
- * function
+/* PLUGIN_EXTENSION structuredef: Used within MC_CMD_PLUGIN_GET_ALL to describe
+ * an individual extension.
+ */
+#define PLUGIN_EXTENSION_LEN 20
+#define PLUGIN_EXTENSION_UUID_OFST 0
+#define PLUGIN_EXTENSION_UUID_LEN 16
+#define PLUGIN_EXTENSION_UUID_LBN 0
+#define PLUGIN_EXTENSION_UUID_WIDTH 128
+#define PLUGIN_EXTENSION_ADMIN_GROUP_OFST 16
+#define PLUGIN_EXTENSION_ADMIN_GROUP_LEN 1
+#define PLUGIN_EXTENSION_ADMIN_GROUP_LBN 128
+#define PLUGIN_EXTENSION_ADMIN_GROUP_WIDTH 8
+#define PLUGIN_EXTENSION_FLAG_ENABLED_LBN 136
+#define PLUGIN_EXTENSION_FLAG_ENABLED_WIDTH 1
+#define PLUGIN_EXTENSION_RESERVED_LBN 137
+#define PLUGIN_EXTENSION_RESERVED_WIDTH 23
+
+/* DESC_ADDR_REGION structuredef: Describes a contiguous region of DESC_ADDR
+ * space that maps to a contiguous region of TRGT_ADDR space. Addresses
+ * DESC_ADDR in the range [DESC_ADDR_BASE:DESC_ADDR_BASE + 1 <<
+ * WINDOW_SIZE_LOG2) map to TRGT_ADDR = DESC_ADDR - DESC_ADDR_BASE +
+ * TRGT_ADDR_BASE.
+ */
+#define DESC_ADDR_REGION_LEN 32
+/* The start of the region in DESC_ADDR space. */
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_OFST 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LEN 8
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_OFST 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LEN 4
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LBN 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_WIDTH 32
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_OFST 4
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LEN 4
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LBN 32
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_WIDTH 32
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LBN 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_WIDTH 64
+/* The start of the region in TRGT_ADDR space. Drivers can set this via
+ * MC_CMD_SET_DESC_ADDR_REGIONS.
+ */
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_OFST 8
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LEN 8
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_OFST 8
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LEN 4
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LBN 64
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_WIDTH 32
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_OFST 12
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LEN 4
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LBN 96
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_WIDTH 32
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LBN 64
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_WIDTH 64
+/* The size of the region. */
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_OFST 16
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LEN 4
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LBN 128
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_WIDTH 32
+/* The alignment restriction on TRGT_ADDR. TRGT_ADDR values set by the driver
+ * must be a multiple of 1 << TRGT_ADDR_ALIGN_LOG2.
+ */
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_OFST 20
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LEN 4
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LBN 160
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_WIDTH 32
+#define DESC_ADDR_REGION_RSVD_OFST 24
+#define DESC_ADDR_REGION_RSVD_LEN 8
+#define DESC_ADDR_REGION_RSVD_LO_OFST 24
+#define DESC_ADDR_REGION_RSVD_LO_LEN 4
+#define DESC_ADDR_REGION_RSVD_LO_LBN 192
+#define DESC_ADDR_REGION_RSVD_LO_WIDTH 32
+#define DESC_ADDR_REGION_RSVD_HI_OFST 28
+#define DESC_ADDR_REGION_RSVD_HI_LEN 4
+#define DESC_ADDR_REGION_RSVD_HI_LBN 224
+#define DESC_ADDR_REGION_RSVD_HI_WIDTH 32
+#define DESC_ADDR_REGION_RSVD_LBN 192
+#define DESC_ADDR_REGION_RSVD_WIDTH 64
+
+
+/***********************************/
+/* MC_CMD_GET_DESC_ADDR_INFO
+ * Returns a description of the mapping from DESC_ADDR to TRGT_ADDR for the calling function's address space.
+ */
+#define MC_CMD_GET_DESC_ADDR_INFO 0x1b7
+#define MC_CMD_GET_DESC_ADDR_INFO_MSGSET 0x1b7
+#undef MC_CMD_0x1b7_PRIVILEGE_CTG
+
+#define MC_CMD_0x1b7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_DESC_ADDR_INFO_IN msgrequest */
+#define MC_CMD_GET_DESC_ADDR_INFO_IN_LEN 0
+
+/* MC_CMD_GET_DESC_ADDR_INFO_OUT msgresponse */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_LEN 4
+/* The type of mapping; see SF-nnnnnn-xx (EF100 driver writer's guide, once
+ * written) for details of each type.
+ */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_OFST 0
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_LEN 4
+/* enum: TRGT_ADDR = DESC_ADDR */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT 0x0
+/* enum: DESC_ADDR has one or more regions that map into TRGT_ADDR. The base
+ * TRGT_ADDR for each region is programmable via MCDI.
+ */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED 0x1
+
+
+/***********************************/
+/* MC_CMD_GET_DESC_ADDR_REGIONS
+ * Returns a list of the DESC_ADDR regions for the calling function's address space. Only valid if that function's address space has the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
+ */
+#define MC_CMD_GET_DESC_ADDR_REGIONS 0x1b8
+#define MC_CMD_GET_DESC_ADDR_REGIONS_MSGSET 0x1b8
+#undef MC_CMD_0x1b8_PRIVILEGE_CTG
+
+#define MC_CMD_0x1b8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_DESC_ADDR_REGIONS_IN msgrequest */
+#define MC_CMD_GET_DESC_ADDR_REGIONS_IN_LEN 0
+
+/* MC_CMD_GET_DESC_ADDR_REGIONS_OUT msgresponse */
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMIN 32
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX 224
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX_MCDI2 992
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LEN(num) (0+32*(num))
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)
+/* An array of DESC_ADDR_REGION strutures. The number of entries in the array
+ * indicates the number of available regions.
+ */
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_OFST 0
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_LEN 32
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MINNUM 1
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM 7
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM_MCDI2 31
+
+
+/***********************************/
+/* MC_CMD_SET_DESC_ADDR_REGIONS
+ * Set the base TRGT_ADDR for a set of DESC_ADDR regions for the calling function's address space. Only valid if that function's address space had the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
+ */
+#define MC_CMD_SET_DESC_ADDR_REGIONS 0x1b9
+#define MC_CMD_SET_DESC_ADDR_REGIONS_MSGSET 0x1b9
+#undef MC_CMD_0x1b9_PRIVILEGE_CTG
+
+#define MC_CMD_0x1b9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_DESC_ADDR_REGIONS_IN msgrequest */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMIN 16
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX 248
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX_MCDI2 1016
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LEN(num) (8+8*(num))
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_NUM(len) (((len)-8)/8)
+/* A bitmask indicating which regions should have their base TRGT_ADDR updated.
+ * To update the base TRGR_ADDR for a DESC_ADDR region, the corresponding bit
+ * should be set to 1.
+ */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_OFST 0
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_LEN 4
+/* Reserved field; must be set to zero. */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_OFST 4
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_LEN 4
+/* An array of values used to updated the base TRGT_ADDR for DESC_ADDR regions.
+ * Array indices corresponding to region numbers (i.e. the array is sparse, and
+ * included entries for regions even if the corresponding SET_REGION_MASK bit
+ * is zero).
*/
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI 0x2
-/* enum: First field refers to function-relative VI number on a specified
- * function
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI_PROXY 0x3
-/* Type of VI. Not needed if ADDRESS_MODE is QUEUE_NUMBER. */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_OFST 8
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_LEN 4
-/* enum: Return only entries used for ef100 queues (a single hardware queue) */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_EF100 0x0
-/* enum: Return entries used for virtio (Potentially two hardware queues,
- * depending on hardware implementation)
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VIRTIO 0x1
-/* Only if ADDRESS_MODE is REL_VI_PROXY. Interface of function the queue is on.
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_OFST 8
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LEN 8
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_OFST 8
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LEN 4
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LBN 64
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_WIDTH 32
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_OFST 12
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LEN 4
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LBN 96
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_WIDTH 32
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MINNUM 1
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM 30
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM_MCDI2 126
+
+/* MC_CMD_SET_DESC_ADDR_REGIONS_OUT msgresponse */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_CLIENT_CMD
+ * Execute an arbitrary MCDI command on behalf of a different client. The
+ * consequences of the command (e.g. ownership of any resources created) apply
+ * to the indicated client rather than the function client which actually sent
+ * this command. All inherent permission checks are also performed on the
+ * indicated client. The given client must be a descendant of the requestor.
+ * The command to be proxied follows immediately afterward in the host buffer
+ * (or on the UART). Chaining multiple MC_CMD_CLIENT_CMD is unnecessary and not
+ * supported. New dynamic clients may be created with MC_CMD_CLIENT_ALLOC.
*/
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_OFST 12
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_LEN 4
-/* Enum values, see field(s): */
-/* DEVEL_PCIE_INTERFACE */
-/* Only if ADDRESS_MODE is REL_VI_PROXY. PF number of the function the queue is
- * on.
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PF_OFST 16
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PF_LEN 2
-/* Only if ADDRESS_MODE is REL_VI_PROXY. VF number of the function the queue is
- * on.
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VF_OFST 18
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VF_LEN 2
-/* enum: The function is on a PF, not a VF. */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VF_NULL 0xffff
-
-/* MC_CMD_DEVEL_DUMP_VI_OUT msgresponse */
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LENMIN 4
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LENMAX 252
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LENMAX_MCDI2 1012
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LEN(num) (0+1*(num))
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_NUM(len) (((len)-0)/1)
-/* Number of dump entries returned */
-#define MC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_LBN 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_WIDTH 8
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_MINNUM 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM 252
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM_MCDI2 1020
-/* Array of MC_CMD_DEVEL_DUMP_VI_ENTRY structures of length NUM_ENTRIES */
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_OFST 4
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_LEN 28
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MINNUM 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM 8
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM_MCDI2 36
-
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structuredef */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_LEN 16
-/* What register this is */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_OFST 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LEN 4
-/* enum: Catchall for registers that aren't in this enum. Nothing should be in
- * this long-term
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_UNKNOWN 0xffffffff
-/* enum: S2IC Converter Debug Packet Counter register. Informs number of
- * packets passed through Converter.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_H2C_S2IC_DBG_PKT_CNT 0x0
-/* enum: IC2S Converter Debug Packet Counter register. Informs number of
- * packets passed through Converter.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_C2H_IC2S_DBG_PKT_CNT 0x1
-/* enum: Event Controller Tx path Debug register. Count of Moderator Tx events,
- * not incl D2C, VirtIO, Dproxy.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DEBUG 0x2
-/* enum: Event Controller Rx path Debug register. Count of Moderator Rx events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_DEBUG 0x3
-/* enum: Event Controller Debug register. Count of Total EVC events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TOTAL_DEBUG 0x4
-/* enum: Same info as EVC_RX_DEBUG; collected at different location in design
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EF100_DEBUG 0x5
-/* enum: Same info as EVC_TX_DEBUG; collected at different location in design
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_EF100_DEBUG 0x6
-/* enum: Event Controller Debug register. Count of Tx VirtIO events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTIO_DEBUG 0x7
-/* enum: Event Controller Debug register. Count of Tx Descriptor Proxy events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DPRXY_DEBUG 0x8
-/* enum: Event Controller Debug register. Count of Tx VirtQ Descriptor Proxy
- * events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_DPRXY_DEBUG 0x9
-/* enum: Event Controller Debug register. Count of Tx Descriptor-to-Completion
- * events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_D2C_DEBUG 0xa
-/* enum: Event Controller Debug register. Count of Tx VirtIO Descriptor-to-
- * Completion events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_D2C_DEBUG 0xb
-/* enum: Event Controller Debug register. Count of Tx Timestamp events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_TSTAMP_DEBUG 0xc
-/* enum: Event Controller Debug register. Count of Rx EvQ Timeout events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EVQ_TIMEOUT_DEBUG 0xd
-/* enum: Event Controller Debug register. Count of MC events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_MC_DEBUG 0xe
-/* enum: Event Controller Debug register. Count of EQDMA VirtIO Control events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_EQDMA_VIO_CTL_DEBUG 0xf
-/* enum: Counter of QDMA Dropped C2H packets. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_DMAC_C2H_DROP_CTR_REG 0x10
-/* enum: Number of packets received by c host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_IN_TBL 0x11
-/* enum: Number of packets sent by c host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_OUT_TBL 0x12
-/* enum: Number of packets received by c plugin fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_P_PACKETS_IN_TBL 0x13
-/* enum: Number of packets received by b host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_H_PACKETS_IN_TBL 0x14
-/* enum: Number of packets received by b net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_N_PACKETS_IN_TBL 0x15
-/* enum: Number of packets received by b host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PH_PACKETS_IN_TBL 0x16
-/* enum: Number of packets received by b net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PN_PACKETS_IN_TBL 0x17
-/* enum: Number of packets sent by b net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PACKETS_OUT_TBL 0x18
-/* enum: Number of packets received by c net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_IN_TBL 0x19
-/* enum: Number of packets sent by c net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_OUT_TBL 0x1a
-/* enum: Number of packets received by ha fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_IN_TBL 0x1b
-/* enum: Number of packets received by ha host shadow fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PH_PACKETS_IN_TBL 0x1c
-/* enum: Number of packets received by ha fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_OUT_TBL 0x1d
-/* enum: Number of packets received by d hub fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_IN_TBL 0x1e
-/* enum: Number of packets received by d hub plugin fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_P_PACKETS_IN_TBL 0x1f
-/* enum: Number of packets received by d hub plugin fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_O_PACKETS_IN_TBL 0x20
-/* enum: Number of packets sent to dmac. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_OUT_TBL 0x21
-/* enum: Number of packets received by na fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_IN_TBL 0x22
-/* enum: Number of packets dropped by na fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_DROPPED_TBL 0x23
-/* enum: Number of packets sent by na fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_OUT_TBL 0x24
-/* enum: Number of packets received by rp hub fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_IN_TBL 0x25
-/* enum: Number of packets removed from fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_OUT_TBL 0x26
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LBN 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_WIDTH 32
-/* If REG is a table, the table row. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_OFST 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LEN 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LBN 32
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_WIDTH 32
-/* Address of the register (as seen by the MC) */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_OFST 8
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LEN 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LBN 64
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_WIDTH 32
-/* Value of the register */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_OFST 12
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LEN 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LBN 96
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_WIDTH 32
-
-
-/***********************************/
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS
- * Dump an assortment of hopefully useful riverhead debug registers
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS 0x1b6
-#undef MC_CMD_0x1b6_PRIVILEGE_CTG
-
-#define MC_CMD_0x1b6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
-
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN msgrequest */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_LEN 4
-/* Which page of registers to retrieve. Page 0 always exists, later pages may
- * also exist if there are too many registers to fit in a single mcdi response.
- * NUM_PAGES in the response will tell you how many there are.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_OFST 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_LEN 4
-
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT msgresponse */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMIN 8
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX 248
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX_MCDI2 1016
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LEN(num) (8+16*(num))
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_NUM(len) (((len)-8)/16)
-/* Number of registers dumped in this response */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_OFST 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_LEN 4
-/* How many pages of registers are available to extract */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_OFST 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_LEN 4
-/* Array of MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structs, one for each register
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_OFST 8
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_LEN 16
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MINNUM 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM 15
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM_MCDI2 63
+#define MC_CMD_CLIENT_CMD 0x1ba
+#define MC_CMD_CLIENT_CMD_MSGSET 0x1ba
+#undef MC_CMD_0x1ba_PRIVILEGE_CTG
+
+#define MC_CMD_0x1ba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CLIENT_CMD_IN msgrequest */
+#define MC_CMD_CLIENT_CMD_IN_LEN 4
+/* The client as which to execute the following command. */
+#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_OFST 0
+#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_LEN 4
+
+/* MC_CMD_CLIENT_CMD_OUT msgresponse */
+#define MC_CMD_CLIENT_CMD_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_CLIENT_ALLOC
+ * Create a new client object. Clients are a system for delineating NIC
+ * resource ownership, such that groups of resources may be torn down as a
+ * unit. See also MC_CMD_CLIENT_CMD. See XN-200265-TC for background, concepts
+ * and a glossary. Clients created by this command are known as "dynamic
+ * clients". The newly-created client is a child of the client which sent this
+ * command. The caller must have the GRP_ALLOC_CLIENT privilege. The new client
+ * initially has no permission to do anything; see
+ * MC_CMD_DEVEL_CLIENT_PRIVILEGE_MODIFY.
+ */
+#define MC_CMD_CLIENT_ALLOC 0x1bb
+#define MC_CMD_CLIENT_ALLOC_MSGSET 0x1bb
+#undef MC_CMD_0x1bb_PRIVILEGE_CTG
+
+#define MC_CMD_0x1bb_PRIVILEGE_CTG SRIOV_CTG_ALLOC_CLIENT
+
+/* MC_CMD_CLIENT_ALLOC_IN msgrequest */
+#define MC_CMD_CLIENT_ALLOC_IN_LEN 0
+
+/* MC_CMD_CLIENT_ALLOC_OUT msgresponse */
+#define MC_CMD_CLIENT_ALLOC_OUT_LEN 4
+/* The ID of the new client object which has been created. */
+#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_OFST 0
+#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_LEN 4
+
+
+/***********************************/
+/* MC_CMD_CLIENT_FREE
+ * Destroy and release an existing client object. All resources owned by that
+ * client (including its child clients, and thus all resources owned by the
+ * entire family tree) are freed.
+ */
+#define MC_CMD_CLIENT_FREE 0x1bc
+#define MC_CMD_CLIENT_FREE_MSGSET 0x1bc
+#undef MC_CMD_0x1bc_PRIVILEGE_CTG
+
+#define MC_CMD_0x1bc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CLIENT_FREE_IN msgrequest */
+#define MC_CMD_CLIENT_FREE_IN_LEN 4
+/* The ID of the client to be freed. This client must be a descendant of the
+ * requestor. A client cannot free itself.
+ */
+#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_OFST 0
+#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_LEN 4
+
+/* MC_CMD_CLIENT_FREE_OUT msgresponse */
+#define MC_CMD_CLIENT_FREE_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_SET_VI_USER
+ * Assign partial rights over this VI to another client. VIs have an 'owner'
+ * and a 'user'. The owner is the client which allocated the VI
+ * (MC_CMD_ALLOC_VIS) and cannot be changed. The user is the client which has
+ * permission to create queues and other resources on that VI. Initially
+ * user==owner, but the user can be changed by this command; the resources thus
+ * created are then owned by the user-client. Only the VI owner can call this
+ * command, and the request will fail if there are any outstanding child
+ * resources (e.g. queues) currently allocated from this VI.
+ */
+#define MC_CMD_SET_VI_USER 0x1be
+#define MC_CMD_SET_VI_USER_MSGSET 0x1be
+#undef MC_CMD_0x1be_PRIVILEGE_CTG
+
+#define MC_CMD_0x1be_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_VI_USER_IN msgrequest */
+#define MC_CMD_SET_VI_USER_IN_LEN 8
+/* Function-relative VI number to modify. */
+#define MC_CMD_SET_VI_USER_IN_INSTANCE_OFST 0
+#define MC_CMD_SET_VI_USER_IN_INSTANCE_LEN 4
+/* Client ID to become the new user. This must be a descendant of the owning
+ * client, the owning client itself, or the special value MC_CMD_CLIENT_ID_SELF
+ * which is synonymous with the owning client.
+ */
+#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_OFST 4
+#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_LEN 4
+
+/* MC_CMD_SET_VI_USER_OUT msgresponse */
+#define MC_CMD_SET_VI_USER_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES
+ * A device reports a set of MAC addresses for each client to use, known as the
+ * "permanent MAC addresses". Those MAC addresses are provided by the client's
+ * administrator, e.g. via MC_CMD_SET_CLIENT_MAC_ADDRESSES, and are intended as
+ * a hint to that client which MAC address its administrator would like to use
+ * to identity itself. This API exists solely to allow communication of MAC
+ * address from administrator to adminstree, and has no inherent interaction
+ * with switching within the device. There is no guarantee that a client will
+ * be able to send traffic with a source MAC address taken from the list of MAC
+ * address reported, nor is there a guarantee that a client will be able to
+ * resource traffic with a destination MAC taken from the list of MAC
+ * addresses. Likewise, there is no guarantee that a client will not be able to
+ * use a MAC address not present in the list. Restrictions on switching are
+ * controlled either through the EVB API if operating in EVB mode, or via MAE
+ * rules if host software is directly managing the MAE. In order to allow
+ * tenants to use this API whilst a provider is using the EVB API, the MAC
+ * addresses reported by MC_CMD_GET_CLIENT_MAC_ADDRESSES will be augmented with
+ * any MAC addresses associated with the vPort assigned to the caller. In order
+ * to allow tenants to use the EVB API whilst a provider is using this API, if
+ * a client queries the MAC addresses for a vPort using the host_evb_port_id
+ * EVB_PORT_ASSIGNED, that list of MAC addresses will be augmented with the MAC
+ * addresses assigned to the calling client. This query can either be explicit
+ * (i.e. MC_CMD_VPORT_GET_MAC_ADDRESSES) or implicit (e.g. creation of a
+ * vAdaptor with a NULL/automatic MAC address). Changing the MAC address on a
+ * vAdaptor only affects VNIC steering filters; it has no effect on the MAC
+ * addresses assigned to the vAdaptor's owner. VirtIO clients behave as EVB
+ * clients. On VirtIO device reset, a vAdaptor is created with an automatic MAC
+ * address. Querying the VirtIO device's MAC address queries the underlying
+ * vAdaptor's MAC address. Setting the VirtIO device's MAC address sets the
+ * underlying vAdaptor's MAC addresses.
+ */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES 0x1c4
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_MSGSET 0x1c4
+#undef MC_CMD_0x1c4_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN msgrequest */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN 4
+/* A handle for the client for whom MAC address should be obtained. Use
+ * CLIENT_HANDLE_SELF to obtain the MAC addresses assigned to the calling
+ * client.
+ */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
+
+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMIN 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX 252
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(num) (0+6*(num))
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)
+/* An array of MAC addresses assigned to the client. */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_OFST 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_LEN 6
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MINNUM 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM 42
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM_MCDI2 170
+
+
+/***********************************/
+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES
+ * Set the permanent MAC addresses for a client. The caller must by an
+ * administrator of the target client. See MC_CMD_GET_CLIENT_MAC_ADDRESSES for
+ * additional detail.
+ */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES 0x1c5
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_MSGSET 0x1c5
+#undef MC_CMD_0x1c5_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN msgrequest */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMIN 4
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX 250
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX_MCDI2 1018
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LEN(num) (4+6*(num))
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_NUM(len) (((len)-4)/6)
+/* A handle for the client for whom MAC addresses should be set */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
+/* An array of MAC addresses to assign to the client. */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_OFST 4
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_LEN 6
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MINNUM 0
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM 41
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM_MCDI2 169
+
+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_BOARD_ATTR
+ * Retrieve physical build-level board attributes as configured at
+ * manufacturing stage. Fields originate from EEPROM and per-platform constants
+ * in firmware. Fields are used in development to identify/ differentiate
+ * boards based on build levels/parameters, and also in manufacturing to cross
+ * check "what was programmed in manufacturing" is same as "what firmware
+ * thinks has been programmed" as there are two layers to translation within
+ * firmware before the attributes reach this MCDI handler. Some parameters are
+ * retrieved as part of other commands and therefore not replicated here. See
+ * GET_VERSION_OUT.
+ */
+#define MC_CMD_GET_BOARD_ATTR 0x1c6
+#define MC_CMD_GET_BOARD_ATTR_MSGSET 0x1c6
+#undef MC_CMD_0x1c6_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_BOARD_ATTR_IN msgrequest */
+#define MC_CMD_GET_BOARD_ATTR_IN_LEN 0
+
+/* MC_CMD_GET_BOARD_ATTR_OUT msgresponse */
+#define MC_CMD_GET_BOARD_ATTR_OUT_LEN 16
+/* Defines board capabilities and validity of attributes returned in this
+ * response-message.
+ */
+#define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_LBN 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_LBN 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_LBN 2
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_LEN 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_LBN 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_LBN 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_LBN 16
+#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_WIDTH 8
+/* enum: The FPGA voltage on the adapter can be set to low */
+#define MC_CMD_FPGA_VOLTAGE_LOW 0x0
+/* enum: The FPGA voltage on the adapter can be set to regular */
+#define MC_CMD_FPGA_VOLTAGE_REG 0x1
+/* enum: The FPGA voltage on the adapter can be set to high */
+#define MC_CMD_FPGA_VOLTAGE_HIGH 0x2
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_LBN 24
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_WIDTH 8
+/* An array of cage types on the board */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_OFST 8
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_LEN 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_NUM 8
+/* enum: The cages are not known */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_UNKNOWN 0x0
+/* enum: The cages are SFP/SFP+ */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_SFP 0x1
+/* enum: The cages are QSFP/QSFP+ */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_QSFP 0x2
+
+
+/***********************************/
+/* MC_CMD_GET_SOC_STATE
+ * Retrieve current state of the System-on-Chip. This command is valid when
+ * MC_CMD_GET_BOARD_ATTR:HAS_SOC is set.
+ */
+#define MC_CMD_GET_SOC_STATE 0x1c7
+#define MC_CMD_GET_SOC_STATE_MSGSET 0x1c7
+#undef MC_CMD_0x1c7_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_SOC_STATE_IN msgrequest */
+#define MC_CMD_GET_SOC_STATE_IN_LEN 0
+
+/* MC_CMD_GET_SOC_STATE_OUT msgresponse */
+#define MC_CMD_GET_SOC_STATE_OUT_LEN 12
+/* Status flags for the SoC */
+#define MC_CMD_GET_SOC_STATE_OUT_FLAGS_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_LBN 0
+#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_WIDTH 1
+#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_LBN 1
+#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_WIDTH 1
+#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_LBN 2
+#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_WIDTH 1
+/* Status fields for the SoC */
+#define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_OFST 4
+#define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_LEN 4
+#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_OFST 4
+#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_LBN 0
+#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_WIDTH 8
+/* enum: Power on (set by SUC on power up) */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOT 0x0
+/* enum: Running bootloader */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOTLOADER 0x1
+/* enum: Bootloader has started OS. OS is booting */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_START 0x2
+/* enum: OS is running */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_RUNNING 0x3
+/* enum: Maintenance OS is running */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_MAINTENANCE 0x4
+/* Number of SoC resets since power on */
+#define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_OFST 8
+#define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_LEN 4
+
+
+/***********************************/
+/* MC_CMD_CHECK_SCHEDULER_CREDITS
+ * For debugging purposes. For each source and destination node in the hardware
+ * schedulers, check whether the number of credits is as it should be. This
+ * should only be used when the NIC is idle, because collection is not atomic
+ * and because the expected credit counts are only meaningful when no traffic
+ * is flowing.
+ */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS 0x1c8
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_MSGSET 0x1c8
+#undef MC_CMD_0x1c8_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
+
+/* MC_CMD_CHECK_SCHEDULER_CREDITS_IN msgrequest */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_LEN 8
+/* Flags for the request */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_OFST 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_LEN 4
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_OFST 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_LBN 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_WIDTH 1
+/* If there are too many results to fit into an MCDI response, they're split
+ * into pages. This field specifies which (0-indexed) page to request. A
+ * request with PAGE=0 will snapshot the results, and subsequent requests with
+ * PAGE>0 will return data from the most recent snapshot. The GENERATION field
+ * in the response allows callers to verify that all responses correspond to
+ * the same snapshot.
+ */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_OFST 4
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_LEN 4
+
+/* MC_CMD_CHECK_SCHEDULER_CREDITS_OUT msgresponse */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMIN 16
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX 240
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX_MCDI2 1008
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LEN(num) (16+16*(num))
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_NUM(len) (((len)-16)/16)
+/* The total number of results (across all pages). */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_OFST 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_LEN 4
+/* The number of pages that the response is split across. */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_OFST 4
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_LEN 4
+/* The number of results in this response. */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_OFST 8
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_LEN 4
+/* Result generation count. Incremented any time a request is made with PAGE=0.
+ */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_OFST 12
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_LEN 4
+/* The results, as an array of SCHED_CREDIT_CHECK_RESULT structures. */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_OFST 16
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_LEN 16
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM 14
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM_MCDI2 62
/* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are
* defined in SF-120734-TC with more information in SF-122717-TC.
@@ -24839,6 +27140,7 @@
* Get a list of the virtio features supported by the device.
*/
#define MC_CMD_VIRTIO_GET_FEATURES 0x168
+#define MC_CMD_VIRTIO_GET_FEATURES_MSGSET 0x168
#undef MC_CMD_0x168_PRIVILEGE_CTG
#define MC_CMD_0x168_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24867,7 +27169,13 @@
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LEN 8
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LEN 4
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LBN 0
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_WIDTH 32
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LEN 4
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LBN 32
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_WIDTH 32
/***********************************/
@@ -24877,6 +27185,7 @@
* the driver fails to request a feature which the device requires.
*/
#define MC_CMD_VIRTIO_TEST_FEATURES 0x169
+#define MC_CMD_VIRTIO_TEST_FEATURES_MSGSET 0x169
#undef MC_CMD_0x169_PRIVILEGE_CTG
#define MC_CMD_0x169_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24898,7 +27207,13 @@
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_OFST 8
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LEN 8
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_OFST 8
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LEN 4
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LBN 64
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_WIDTH 32
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_OFST 12
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LEN 4
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LBN 96
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_WIDTH 32
/* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */
#define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0
@@ -24912,6 +27227,7 @@
* invalid.
*/
#define MC_CMD_VIRTIO_INIT_QUEUE 0x16a
+#define MC_CMD_VIRTIO_INIT_QUEUE_MSGSET 0x16a
#undef MC_CMD_0x16a_PRIVILEGE_CTG
#define MC_CMD_0x16a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24956,17 +27272,35 @@
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_OFST 16
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_OFST 16
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LBN 128
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_OFST 20
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LBN 160
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_WIDTH 32
/* Address of the available ring in the virtqueue. */
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_OFST 24
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_OFST 24
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LBN 192
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_OFST 28
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LBN 224
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_WIDTH 32
/* Address of the used ring in the virtqueue. */
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_OFST 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_OFST 32
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LBN 256
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_OFST 36
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LBN 288
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_WIDTH 32
/* PASID to use on PCIe transactions involving this queue. Ignored if the
* USE_PASID flag is not set.
*/
@@ -24990,7 +27324,13 @@
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_OFST 48
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_OFST 48
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LBN 384
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_OFST 52
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LBN 416
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_WIDTH 32
/* Enum values, see field(s): */
/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_OUT/FEATURES */
/* The initial producer index for this queue's used ring. If this queue is
@@ -25023,6 +27363,7 @@
* Destroy a virtio virtqueue
*/
#define MC_CMD_VIRTIO_FINI_QUEUE 0x16b
+#define MC_CMD_VIRTIO_FINI_QUEUE_MSGSET 0x16b
#undef MC_CMD_0x16b_PRIVILEGE_CTG
#define MC_CMD_0x16b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -25063,6 +27404,7 @@
* queue(s) to be allocated.
*/
#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c
+#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_MSGSET 0x16c
#undef MC_CMD_0x16c_PRIVILEGE_CTG
#define MC_CMD_0x16c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -25132,12 +27474,18 @@
#define PCIE_FUNCTION_VF_NULL 0xffff
#define PCIE_FUNCTION_VF_LBN 16
#define PCIE_FUNCTION_VF_WIDTH 16
-/* PCIe interface of the function */
+/* PCIe interface of the function. Values should be taken from the
+ * PCIE_INTERFACE enum
+ */
#define PCIE_FUNCTION_INTF_OFST 4
#define PCIE_FUNCTION_INTF_LEN 4
-/* enum: Host PCIe interface */
+/* enum: Host PCIe interface. (Alias for HOST_PRIMARY, provided for backwards
+ * compatibility)
+ */
#define PCIE_FUNCTION_INTF_HOST 0x0
-/* enum: Application Processor interface */
+/* enum: Application Processor interface (alias for NIC_EMBEDDED, provided for
+ * backwards compatibility)
+ */
#define PCIE_FUNCTION_INTF_AP 0x1
#define PCIE_FUNCTION_INTF_LBN 32
#define PCIE_FUNCTION_INTF_WIDTH 32
@@ -25157,6 +27505,7 @@
* MC_CMD_DESC_PROXY_FUNC_COMMIT_IN.
*/
#define MC_CMD_DESC_PROXY_FUNC_CREATE 0x172
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_MSGSET 0x172
#undef MC_CMD_0x172_PRIVILEGE_CTG
#define MC_CMD_0x172_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25170,7 +27519,19 @@
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LEN 8
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LBN 0
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_WIDTH 32
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LBN 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_WIDTH 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_OFST 0
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_OFST 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_LEN 4
/* The personality to set. The meanings of the personalities are defined in
* SF-120734-TC with more information in SF-122717-TC. At present, we only
* support proxying for VIRTIO_BLK
@@ -25194,7 +27555,19 @@
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LEN 8
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LBN 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_WIDTH 32
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LBN 64
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_WIDTH 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_OFST 6
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_LEN 4
/***********************************/
@@ -25205,6 +27578,7 @@
* ownership is released.
*/
#define MC_CMD_DESC_PROXY_FUNC_DESTROY 0x173
+#define MC_CMD_DESC_PROXY_FUNC_DESTROY_MSGSET 0x173
#undef MC_CMD_0x173_PRIVILEGE_CTG
#define MC_CMD_0x173_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25235,7 +27609,13 @@
#define VIRTIO_BLK_CONFIG_FEATURES_OFST 0
#define VIRTIO_BLK_CONFIG_FEATURES_LEN 8
#define VIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0
+#define VIRTIO_BLK_CONFIG_FEATURES_LO_LEN 4
+#define VIRTIO_BLK_CONFIG_FEATURES_LO_LBN 0
+#define VIRTIO_BLK_CONFIG_FEATURES_LO_WIDTH 32
#define VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4
+#define VIRTIO_BLK_CONFIG_FEATURES_HI_LEN 4
+#define VIRTIO_BLK_CONFIG_FEATURES_HI_LBN 32
+#define VIRTIO_BLK_CONFIG_FEATURES_HI_WIDTH 32
#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0
#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0
#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1
@@ -25308,7 +27688,13 @@
#define VIRTIO_BLK_CONFIG_CAPACITY_OFST 8
#define VIRTIO_BLK_CONFIG_CAPACITY_LEN 8
#define VIRTIO_BLK_CONFIG_CAPACITY_LO_OFST 8
+#define VIRTIO_BLK_CONFIG_CAPACITY_LO_LEN 4
+#define VIRTIO_BLK_CONFIG_CAPACITY_LO_LBN 64
+#define VIRTIO_BLK_CONFIG_CAPACITY_LO_WIDTH 32
#define VIRTIO_BLK_CONFIG_CAPACITY_HI_OFST 12
+#define VIRTIO_BLK_CONFIG_CAPACITY_HI_LEN 4
+#define VIRTIO_BLK_CONFIG_CAPACITY_HI_LBN 96
+#define VIRTIO_BLK_CONFIG_CAPACITY_HI_WIDTH 32
#define VIRTIO_BLK_CONFIG_CAPACITY_LBN 64
#define VIRTIO_BLK_CONFIG_CAPACITY_WIDTH 64
/* Maximum size of any single segment. Only valid when VIRTIO_BLK_F_SIZE_MAX is
@@ -25445,6 +27831,7 @@
* not persisted until the caller commits with MC_CMD_DESC_PROXY_FUNC_COMMIT_IN
*/
#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174
+#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_MSGSET 0x174
#undef MC_CMD_0x174_PRIVILEGE_CTG
#define MC_CMD_0x174_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25485,6 +27872,7 @@
* delivered to callers MCDI event queue.
*/
#define MC_CMD_DESC_PROXY_FUNC_COMMIT 0x175
+#define MC_CMD_DESC_PROXY_FUNC_COMMIT_MSGSET 0x175
#undef MC_CMD_0x175_PRIVILEGE_CTG
#define MC_CMD_0x175_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25518,6 +27906,7 @@
* cycle. Returns ENODEV if no function with given label exists.
*/
#define MC_CMD_DESC_PROXY_FUNC_OPEN 0x176
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_MSGSET 0x176
#undef MC_CMD_0x176_PRIVILEGE_CTG
#define MC_CMD_0x176_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25543,7 +27932,19 @@
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LEN 8
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LBN 32
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_WIDTH 32
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LBN 64
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_WIDTH 32
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_OFST 6
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_LEN 4
/* Function personality */
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_OFST 12
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4
@@ -25588,6 +27989,7 @@
* error (for virtio, DEVICE_NEEDS_RESET flag would be set on the host side)
*/
#define MC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1
+#define MC_CMD_DESC_PROXY_FUNC_CLOSE_MSGSET 0x1a1
#undef MC_CMD_0x1a1_PRIVILEGE_CTG
#define MC_CMD_0x1a1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25607,9 +28009,27 @@
#define DESC_PROXY_FUNC_MAP_FUNC_OFST 0
#define DESC_PROXY_FUNC_MAP_FUNC_LEN 8
#define DESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0
+#define DESC_PROXY_FUNC_MAP_FUNC_LO_LEN 4
+#define DESC_PROXY_FUNC_MAP_FUNC_LO_LBN 0
+#define DESC_PROXY_FUNC_MAP_FUNC_LO_WIDTH 32
#define DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4
+#define DESC_PROXY_FUNC_MAP_FUNC_HI_LEN 4
+#define DESC_PROXY_FUNC_MAP_FUNC_HI_LBN 32
+#define DESC_PROXY_FUNC_MAP_FUNC_HI_WIDTH 32
#define DESC_PROXY_FUNC_MAP_FUNC_LBN 0
#define DESC_PROXY_FUNC_MAP_FUNC_WIDTH 64
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_OFST 0
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_LEN 2
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_LBN 0
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_WIDTH 16
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_OFST 2
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_LEN 2
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_LBN 16
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_WIDTH 16
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_OFST 4
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_LEN 4
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_LBN 32
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_WIDTH 32
/* Function personality */
#define DESC_PROXY_FUNC_MAP_PERSONALITY_OFST 8
#define DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4
@@ -25631,6 +28051,7 @@
* Enumerate existing descriptor proxy functions
*/
#define MC_CMD_DESC_PROXY_FUNC_ENUM 0x177
+#define MC_CMD_DESC_PROXY_FUNC_ENUM_MSGSET 0x177
#undef MC_CMD_0x177_PRIVILEGE_CTG
#define MC_CMD_0x177_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25670,6 +28091,7 @@
* function.
*/
#define MC_CMD_DESC_PROXY_FUNC_ENABLE 0x178
+#define MC_CMD_DESC_PROXY_FUNC_ENABLE_MSGSET 0x178
#undef MC_CMD_0x178_PRIVILEGE_CTG
#define MC_CMD_0x178_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25702,6 +28124,7 @@
* Disable descriptor proxying for function
*/
#define MC_CMD_DESC_PROXY_FUNC_DISABLE 0x179
+#define MC_CMD_DESC_PROXY_FUNC_DISABLE_MSGSET 0x179
#undef MC_CMD_0x179_PRIVILEGE_CTG
#define MC_CMD_0x179_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25725,6 +28148,7 @@
* descriptors.
*/
#define MC_CMD_GET_ADDR_SPC_ID 0x1a0
+#define MC_CMD_GET_ADDR_SPC_ID_MSGSET 0x1a0
#undef MC_CMD_0x1a0_PRIVILEGE_CTG
#define MC_CMD_0x1a0_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25769,7 +28193,19 @@
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LEN 8
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LBN 32
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_WIDTH 32
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_OFST 8
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LBN 64
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_WIDTH 32
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_OFST 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_LEN 2
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_OFST 6
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_LEN 2
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_OFST 8
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_LEN 4
/* PASID value. Only valid if TYPE is PCI_FUNC_PASID. */
#define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_OFST 12
#define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4
@@ -25789,7 +28225,72 @@
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LEN 8
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LBN 0
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_WIDTH 32
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LBN 32
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_GET_CLIENT_HANDLE
+ * Obtain a handle for a client given a description of that client. N.B. this
+ * command is subject to change given the open discussion about how PCIe
+ * functions should be referenced on an iEP (integrated endpoint: functions
+ * span multiple buses) and multihost (multiple PCIe interfaces) system.
+ */
+#define MC_CMD_GET_CLIENT_HANDLE 0x1c3
+#define MC_CMD_GET_CLIENT_HANDLE_MSGSET 0x1c3
+#undef MC_CMD_0x1c3_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_CLIENT_HANDLE_IN msgrequest */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_LEN 12
+/* Type of client to get a client handle for */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_OFST 0
+#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_LEN 4
+/* enum: Obtain a client handle for a PCIe function-type client. */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC 0x0
+/* PCIe Function ID (as struct PCIE_FUNCTION). Valid when TYPE==FUNC. Use: -
+ * INTF=CALLER, PF=PF_NULL, VF=VF_NULL to refer to the calling function -
+ * INTF=CALLER, PF=PF_NULL, VF=... to refer to a VF child of the calling PF or
+ * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
+ * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
+ * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF
+ * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
+ * interface where ... refers to a small integer for the VF/PF fields, and to
+ * values from the PCIE_INTERFACE enum for for the INTF field. It's only
+ * meaningful to use INTF=CALLER within a structure that's an argument to
+ * MC_CMD_DEVEL_GET_CLIENT_HANDLE.
+ */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_OFST 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LEN 8
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_OFST 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LEN 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LBN 32
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_WIDTH 32
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_OFST 8
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LEN 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LBN 64
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_WIDTH 32
+/* enum: NULL value for the INTF field of struct PCIE_FUNCTION. Provided for
+ * backwards compatibility only, callers should use PCIE_INTERFACE_CALLER.
+ */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_LEN 2
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_OFST 6
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_LEN 2
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_OFST 8
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_LEN 4
+
+/* MC_CMD_GET_CLIENT_HANDLE_OUT msgresponse */
+#define MC_CMD_GET_CLIENT_HANDLE_OUT_LEN 4
+#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_OFST 0
+#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_LEN 4
/* MAE_FIELD_FLAGS structuredef */
#define MAE_FIELD_FLAGS_LEN 4
@@ -25937,6 +28438,40 @@
#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LEN 1
#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LBN 1096
#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_LBN 0
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_LBN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_LBN 2
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LBN 1104
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LBN 1104
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_LBN 0
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_LBN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_LBN 2
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LBN 1112
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LBN 1112
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_WIDTH 8
#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_OFST 140
#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4
#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LBN 1120
@@ -26623,9 +29158,24 @@
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_OFST 344
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_LBN 3
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_WIDTH 1
-#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_OFST 344
-#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_LBN 4
-#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_WIDTH 28
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_LBN 4
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_LBN 5
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_LBN 6
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_LBN 7
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_LBN 8
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_LBN 9
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_WIDTH 1
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LBN 2752
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_WIDTH 32
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST 348
@@ -26707,16 +29257,34 @@
#define MAE_MPORT_SELECTOR_TYPE_WIDTH 8
/* enum: The MPORT connected to a given physical port */
#define MAE_MPORT_SELECTOR_TYPE_PPORT 0x2
-/* enum: The MPORT assigned to a given PCIe function */
+/* enum: The MPORT assigned to a given PCIe function. Deprecated in favour of
+ * MH_FUNC.
+ */
#define MAE_MPORT_SELECTOR_TYPE_FUNC 0x3
/* enum: An mport_id */
#define MAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4
+/* enum: The MPORT assigned to a given PCIe function (see also FWRIVERHD-1108)
+ */
+#define MAE_MPORT_SELECTOR_TYPE_MH_FUNC 0x5
+/* enum: This is guaranteed never to be a valid selector type */
+#define MAE_MPORT_SELECTOR_TYPE_INVALID 0xff
#define MAE_MPORT_SELECTOR_MPORT_ID_OFST 0
#define MAE_MPORT_SELECTOR_MPORT_ID_LBN 0
#define MAE_MPORT_SELECTOR_MPORT_ID_WIDTH 24
#define MAE_MPORT_SELECTOR_PPORT_ID_OFST 0
#define MAE_MPORT_SELECTOR_PPORT_ID_LBN 0
#define MAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_OFST 0
+#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define MAE_MPORT_SELECTOR_HOST_PRIMARY 0x1 /* enum */
+#define MAE_MPORT_SELECTOR_NIC_EMBEDDED 0x2 /* enum */
+/* enum: Deprecated, use CALLER_INTF instead. */
+#define MAE_MPORT_SELECTOR_CALLER 0xf
+#define MAE_MPORT_SELECTOR_CALLER_INTF 0xf /* enum */
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_OFST 0
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_LBN 16
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_WIDTH 8
@@ -26737,15 +29305,56 @@
* function.
*/
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff
+/* enum: Same as PF_ID_CALLER, but for use in the smaller MH_PF_ID field. Only
+ * valid if FUNC_INTF_ID is CALLER.
+ */
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_CALLER 0xf
#define MAE_MPORT_SELECTOR_FLAT_LBN 0
#define MAE_MPORT_SELECTOR_FLAT_WIDTH 32
+/* MAE_LINK_ENDPOINT_SELECTOR structuredef: Structure that identifies a real or
+ * virtual network port by MAE port and link end
+ */
+#define MAE_LINK_ENDPOINT_SELECTOR_LEN 8
+/* The MAE MPORT of interest */
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_WIDTH 32
+/* Which end of the link identified by MPORT to consider */
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_OFST 4
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LEN 4
+/* Enum values, see field(s): */
+/* MAE_MPORT_END */
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LBN 32
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_WIDTH 32
+/* A field for accessing the endpoint selector as a collection of bits */
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_OFST 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LEN 8
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_OFST 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LEN 4
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LBN 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_WIDTH 32
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_OFST 4
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LEN 4
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LBN 32
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_WIDTH 32
+/* enum: Set FLAT to this value to obtain backward-compatible behaviour in
+ * commands that have been extended to take a MAE_LINK_ENDPOINT_SELECTOR
+ * argument. New commands that are designed to take such an argument from the
+ * start will not support this.
+ */
+#define MAE_LINK_ENDPOINT_SELECTOR_MAE_LINK_ENDPOINT_COMPAT 0x0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LBN 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_WIDTH 64
+
/***********************************/
/* MC_CMD_MAE_GET_CAPS
* Describes capabilities of the MAE (Match-Action Engine)
*/
#define MC_CMD_MAE_GET_CAPS 0x140
+#define MC_CMD_MAE_GET_CAPS_MSGSET 0x140
#undef MC_CMD_0x140_PRIVILEGE_CTG
#define MC_CMD_0x140_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -26772,6 +29381,9 @@
#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4
#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_LBN 2
#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
+#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_OFST 4
+#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_LBN 3
+#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
/* The total number of counters available to allocate. */
#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_OFST 8
#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4
@@ -26823,6 +29435,7 @@
* Get a level of support for match fields when used in match-action rules
*/
#define MC_CMD_MAE_GET_AR_CAPS 0x141
+#define MC_CMD_MAE_GET_AR_CAPS_MSGSET 0x141
#undef MC_CMD_0x141_PRIVILEGE_CTG
#define MC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26855,6 +29468,7 @@
* Get a level of support for fields used in outer rule keys.
*/
#define MC_CMD_MAE_GET_OR_CAPS 0x142
+#define MC_CMD_MAE_GET_OR_CAPS_MSGSET 0x142
#undef MC_CMD_0x142_PRIVILEGE_CTG
#define MC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26885,6 +29499,7 @@
* Rules.
*/
#define MC_CMD_MAE_COUNTER_ALLOC 0x143
+#define MC_CMD_MAE_COUNTER_ALLOC_MSGSET 0x143
#undef MC_CMD_0x143_PRIVILEGE_CTG
#define MC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26928,6 +29543,7 @@
* Free match-action-engine counters
*/
#define MC_CMD_MAE_COUNTER_FREE 0x144
+#define MC_CMD_MAE_COUNTER_FREE_MSGSET 0x144
#undef MC_CMD_0x144_PRIVILEGE_CTG
#define MC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26995,6 +29611,7 @@
* delivering packets to the current queue first.
*/
#define MC_CMD_MAE_COUNTERS_STREAM_START 0x151
+#define MC_CMD_MAE_COUNTERS_STREAM_START_MSGSET 0x151
#undef MC_CMD_0x151_PRIVILEGE_CTG
#define MC_CMD_0x151_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27031,6 +29648,7 @@
* Stop streaming counter values to the specified RxQ.
*/
#define MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152
+#define MC_CMD_MAE_COUNTERS_STREAM_STOP_MSGSET 0x152
#undef MC_CMD_0x152_PRIVILEGE_CTG
#define MC_CMD_0x152_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27060,6 +29678,7 @@
* MAE_COUNTERS_PACKETISER_STREAM_START/PACKET_SIZE and rung the doorbell.
*/
#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153
+#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_MSGSET 0x153
#undef MC_CMD_0x153_PRIVILEGE_CTG
#define MC_CMD_0x153_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27076,9 +29695,15 @@
/***********************************/
/* MC_CMD_MAE_ENCAP_HEADER_ALLOC
- * Allocate encap action metadata
+ * Allocate an encapsulation header to be used in an Action Rule response. The
+ * header must be constructed as a valid packet with 0-length payload.
+ * Specifically, the L3/L4 lengths & checksums will only be incrementally fixed
+ * by the NIC, rather than recomputed entirely. Currently only IPv4, IPv6 and
+ * UDP are supported. If the maximum number of headers have already been
+ * allocated then the command will fail with MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148
+#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_MSGSET 0x148
#undef MC_CMD_0x148_PRIVILEGE_CTG
#define MC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27109,9 +29734,10 @@
/***********************************/
/* MC_CMD_MAE_ENCAP_HEADER_UPDATE
- * Update encap action metadata
+ * Update encap action metadata. See comments for MAE_ENCAP_HEADER_ALLOC.
*/
#define MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149
+#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_MSGSET 0x149
#undef MC_CMD_0x149_PRIVILEGE_CTG
#define MC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27141,6 +29767,7 @@
* Free encap action metadata
*/
#define MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a
+#define MC_CMD_MAE_ENCAP_HEADER_FREE_MSGSET 0x14a
#undef MC_CMD_0x14a_PRIVILEGE_CTG
#define MC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27176,9 +29803,12 @@
/* MC_CMD_MAE_MAC_ADDR_ALLOC
* Allocate MAC address. Hardware implementations have MAC addresses programmed
* into an indirection table, and clients should take care not to allocate the
- * same MAC address twice (but instead reuse its ID).
+ * same MAC address twice (but instead reuse its ID). If the maximum number of
+ * MAC addresses have already been allocated then the command will fail with
+ * MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e
+#define MC_CMD_MAE_MAC_ADDR_ALLOC_MSGSET 0x15e
#undef MC_CMD_0x15e_PRIVILEGE_CTG
#define MC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27204,6 +29834,7 @@
* Free MAC address.
*/
#define MC_CMD_MAE_MAC_ADDR_FREE 0x15f
+#define MC_CMD_MAE_MAC_ADDR_FREE_MSGSET 0x15f
#undef MC_CMD_0x15f_PRIVILEGE_CTG
#define MC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27238,9 +29869,12 @@
/***********************************/
/* MC_CMD_MAE_ACTION_SET_ALLOC
* Allocate an action set, which can be referenced either in response to an
- * Action Rule, or as part of an Action Set List.
+ * Action Rule, or as part of an Action Set List. If the maxmimum number of
+ * action sets have already been allocated then the command will fail with
+ * MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ACTION_SET_ALLOC 0x14d
+#define MC_CMD_MAE_ACTION_SET_ALLOC_MSGSET 0x14d
#undef MC_CMD_0x14d_PRIVILEGE_CTG
#define MC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27267,6 +29901,15 @@
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_LBN 11
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_LBN 12
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_LBN 13
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_LBN 14
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_LEN 2
@@ -27313,8 +29956,135 @@
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_OFST 40
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4
+/* MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN msgrequest: Only supported if
+ * MAE_ACTION_SET_ALLOC_V2_SUPPORTED is advertised in
+ * MC_CMD_GET_CAPABILITIES_V7_OUT.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LEN 51
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_LEN 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_LBN 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_WIDTH 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_LBN 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_WIDTH 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_LBN 8
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_LBN 9
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_LBN 10
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_LBN 11
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_LBN 12
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_LBN 13
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_LBN 14
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
+/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_LEN 2
+/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_OFST 6
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_LEN 2
+/* If VLAN_PUSH == 2, inner TCI value to be inserted. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_OFST 8
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_LEN 2
+/* If VLAN_PUSH == 2, inner TPID value to be inserted. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_OFST 10
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_LEN 2
+/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_OFST 12
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_LEN 4
+/* Set to ENCAP_HEADER_ID_NULL to request no encap action */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_OFST 16
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_LEN 4
+/* An m-port selector identifying the m-port that the modified packet should be
+ * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the
+ * packet.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_OFST 20
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4
+/* Allows an action set to trigger several counter updates. Set to
+ * COUNTER_LIST_ID_NULL to request no counter action.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_OFST 24
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4
+/* If a driver only wished to update one counter within this action set, then
+ * it can supply a COUNTER_ID instead of allocating a single-element counter
+ * list. This field should be set to COUNTER_ID_NULL if this behaviour is not
+ * required. It is not valid to supply a non-NULL value for both
+ * COUNTER_LIST_ID and COUNTER_ID.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_OFST 28
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_OFST 32
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4
+/* Set to MAC_ID_NULL to request no source MAC replacement. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_OFST 36
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_LEN 4
+/* Set to MAC_ID_NULL to request no destination MAC replacement. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_OFST 40
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_LEN 4
+/* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_OFST 44
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_LEN 4
+/* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
+ * within IPv4 and IPv6 headers.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_LEN 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_LBN 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_LBN 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_LBN 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_LBN 3
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_WIDTH 6
+/* Actions for modifying the Explicit Congestion Notification (ECN) bits within
+ * IPv4 and IPv6 headers.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_LEN 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_LBN 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_LBN 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_LBN 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_LBN 3
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_WIDTH 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_LBN 5
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_LBN 6
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_WIDTH 1
+
/* MC_CMD_MAE_ACTION_SET_ALLOC_OUT msgresponse */
#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4
+/* The MSB of the AS_ID is guaranteed to be clear if the ID is not
+ * ACTION_SET_ID_NULL. This allows an AS_ID to be distinguished from an ASL_ID
+ * returned from MC_CMD_MAE_ACTION_SET_LIST_ALLOC.
+ */
#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0
#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4
/* enum: An action set ID that is guaranteed never to represent an action set
@@ -27326,6 +30096,7 @@
/* MC_CMD_MAE_ACTION_SET_FREE
*/
#define MC_CMD_MAE_ACTION_SET_FREE 0x14e
+#define MC_CMD_MAE_ACTION_SET_FREE_MSGSET 0x14e
#undef MC_CMD_0x14e_PRIVILEGE_CTG
#define MC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27361,9 +30132,12 @@
/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC
* Allocate an action set list (ASL) that can be referenced by an ID. The ASL
* ID can be used when inserting an action rule, so that for each packet
- * matching the rule every action set in the list is applied.
+ * matching the rule every action set in the list is applied. If the maximum
+ * number of ASLs have already been allocated then the command will fail with
+ * MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f
+#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_MSGSET 0x14f
#undef MC_CMD_0x14f_PRIVILEGE_CTG
#define MC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27394,6 +30168,9 @@
/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT msgresponse */
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4
+/* The MSB of the ASL_ID is guaranteed to be set. This allows an ASL_ID to be
+ * distinguished from an AS_ID returned from MC_CMD_MAE_ACTION_SET_ALLOC.
+ */
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4
/* enum: An action set list ID that is guaranteed never to represent an action
@@ -27407,6 +30184,7 @@
* Free match-action-engine redirect_lists
*/
#define MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150
+#define MC_CMD_MAE_ACTION_SET_LIST_FREE_MSGSET 0x150
#undef MC_CMD_0x150_PRIVILEGE_CTG
#define MC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27441,9 +30219,11 @@
/***********************************/
/* MC_CMD_MAE_OUTER_RULE_INSERT
* Inserts an Outer Rule, which controls encapsulation parsing, and may
- * influence the Lookup Sequence.
+ * influence the Lookup Sequence. If the maximum number of rules have already
+ * been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_OUTER_RULE_INSERT 0x15a
+#define MC_CMD_MAE_OUTER_RULE_INSERT_MSGSET 0x15a
#undef MC_CMD_0x15a_PRIVILEGE_CTG
#define MC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27504,6 +30284,7 @@
/* MC_CMD_MAE_OUTER_RULE_REMOVE
*/
#define MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b
+#define MC_CMD_MAE_OUTER_RULE_REMOVE_MSGSET 0x15b
#undef MC_CMD_0x15b_PRIVILEGE_CTG
#define MC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27583,9 +30364,11 @@
/* MC_CMD_MAE_ACTION_RULE_INSERT
* Insert a rule specify that packets matching a filter be processed according
* to a previous allocated action. Masks can be set as indicated by
- * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES.
+ * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES. If the maximum number of rules have
+ * already been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ACTION_RULE_INSERT 0x15c
+#define MC_CMD_MAE_ACTION_RULE_INSERT_MSGSET 0x15c
#undef MC_CMD_0x15c_PRIVILEGE_CTG
#define MC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27627,6 +30410,7 @@
* ENOTSUP, in which case the driver should DELETE/INSERT.
*/
#define MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d
+#define MC_CMD_MAE_ACTION_RULE_UPDATE_MSGSET 0x15d
#undef MC_CMD_0x15d_PRIVILEGE_CTG
#define MC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27648,6 +30432,7 @@
/* MC_CMD_MAE_ACTION_RULE_DELETE
*/
#define MC_CMD_MAE_ACTION_RULE_DELETE 0x155
+#define MC_CMD_MAE_ACTION_RULE_DELETE_MSGSET 0x155
#undef MC_CMD_0x155_PRIVILEGE_CTG
#define MC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27684,6 +30469,7 @@
* Return the m-port corresponding to a selector.
*/
#define MC_CMD_MAE_MPORT_LOOKUP 0x160
+#define MC_CMD_MAE_MPORT_LOOKUP_MSGSET 0x160
#undef MC_CMD_0x160_PRIVILEGE_CTG
#define MC_CMD_0x160_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -27705,6 +30491,7 @@
* match or delivery argument.
*/
#define MC_CMD_MAE_MPORT_ALLOC 0x163
+#define MC_CMD_MAE_MPORT_ALLOC_MSGSET 0x163
#undef MC_CMD_0x163_PRIVILEGE_CTG
#define MC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27812,6 +30599,7 @@
* Free a m-port which was previously allocated by the driver.
*/
#define MC_CMD_MAE_MPORT_FREE 0x164
+#define MC_CMD_MAE_MPORT_FREE_MSGSET 0x164
#undef MC_CMD_0x164_PRIVILEGE_CTG
#define MC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27847,6 +30635,9 @@
#define MAE_MPORT_DESC_CAN_DELETE_OFST 8
#define MAE_MPORT_DESC_CAN_DELETE_LBN 2
#define MAE_MPORT_DESC_CAN_DELETE_WIDTH 1
+#define MAE_MPORT_DESC_IS_ZOMBIE_OFST 8
+#define MAE_MPORT_DESC_IS_ZOMBIE_LBN 3
+#define MAE_MPORT_DESC_IS_ZOMBIE_WIDTH 1
#define MAE_MPORT_DESC_CALLER_FLAGS_LBN 64
#define MAE_MPORT_DESC_CALLER_FLAGS_WIDTH 32
/* Not the ideal name; it's really the type of thing connected to the m-port */
@@ -27869,7 +30660,13 @@
#define MAE_MPORT_DESC_RESERVED_OFST 32
#define MAE_MPORT_DESC_RESERVED_LEN 8
#define MAE_MPORT_DESC_RESERVED_LO_OFST 32
+#define MAE_MPORT_DESC_RESERVED_LO_LEN 4
+#define MAE_MPORT_DESC_RESERVED_LO_LBN 256
+#define MAE_MPORT_DESC_RESERVED_LO_WIDTH 32
#define MAE_MPORT_DESC_RESERVED_HI_OFST 36
+#define MAE_MPORT_DESC_RESERVED_HI_LEN 4
+#define MAE_MPORT_DESC_RESERVED_HI_LBN 288
+#define MAE_MPORT_DESC_RESERVED_HI_WIDTH 32
#define MAE_MPORT_DESC_RESERVED_LBN 256
#define MAE_MPORT_DESC_RESERVED_WIDTH 64
/* Logical port index. Only valid when type NET Port. */
@@ -27916,8 +30713,11 @@
/***********************************/
/* MC_CMD_MAE_MPORT_ENUMERATE
+ * Deprecated in favour of MAE_MPORT_READ_JOURNAL. Support for this command
+ * will be removed at some future point.
*/
#define MC_CMD_MAE_MPORT_ENUMERATE 0x17c
+#define MC_CMD_MAE_MPORT_ENUMERATE_MSGSET 0x17c
#undef MC_CMD_0x17c_PRIVILEGE_CTG
#define MC_CMD_0x17c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -27945,4 +30745,50 @@
#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM 244
#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1012
+
+/***********************************/
+/* MC_CMD_MAE_MPORT_READ_JOURNAL
+ * Firmware maintains a per-client journal of mport creations and deletions.
+ * This journal is clear-on-read, i.e. repeated calls of this command will
+ * drain the buffer. Whenever the caller resets its function via FLR or
+ * MC_CMD_ENTITY_RESET, the journal is regenerated from a blank start.
+ */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL 0x147
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_MSGSET 0x147
+#undef MC_CMD_0x147_PRIVILEGE_CTG
+
+#define MC_CMD_0x147_PRIVILEGE_CTG SRIOV_CTG_MAE
+
+/* MC_CMD_MAE_MPORT_READ_JOURNAL_IN msgrequest */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_LEN 4
+/* Any unused flags are reserved and must be set to zero. */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_OFST 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_LEN 4
+
+/* MC_CMD_MAE_MPORT_READ_JOURNAL_OUT msgresponse */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMIN 12
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX 252
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LEN(num) (12+1*(num))
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_NUM(len) (((len)-12)/1)
+/* Any unused flags are reserved and must be ignored. */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_OFST 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_LEN 4
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_OFST 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_LBN 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_WIDTH 1
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_OFST 4
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_LEN 4
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_OFST 8
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_LEN 4
+/* Any array of MAE_MPORT_DESC structures. The MAE_MPORT_DESC structure may
+ * grow in future version of this command. Drivers should use a stride of
+ * SIZEOF_MPORT_DESC. Fields beyond SIZEOF_MPORT_DESC are not present.
+ */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_OFST 12
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_LEN 1
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MINNUM 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM 240
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1008
+
#endif /* _SIENA_MC_DRIVER_PCOL_H */
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h
index f7c89fabc..c45f678c2 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h
@@ -6,7 +6,7 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
* rebuild this file with "make mcdi_headers_v5".
*/
@@ -20,6 +20,7 @@
* Perform an FC operation
*/
#define MC_CMD_FC 0x9
+#define MC_CMD_FC_MSGSET 0x9
/* MC_CMD_FC_IN msgrequest */
#define MC_CMD_FC_IN_LEN 4
@@ -212,7 +213,13 @@
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LEN 4
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LBN 128
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_WIDTH 32
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LEN 4
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LBN 160
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_WIDTH 32
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_OFST 24
@@ -784,12 +791,24 @@
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LBN 96
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LBN 128
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_WIDTH 32
/* AOE address from which to transfer data */
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LBN 160
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LBN 192
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_WIDTH 32
/* Length of AOE transfer (total) */
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4
@@ -916,7 +935,13 @@
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LEN 4
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LBN 96
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_WIDTH 32
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LEN 4
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LBN 128
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_WIDTH 32
#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4
@@ -1016,7 +1041,13 @@
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LEN 4
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LBN 96
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LEN 4
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LBN 128
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_WIDTH 32
/* Port number of PTP packet for which timestamp required */
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4
@@ -1320,7 +1351,13 @@
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LEN 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LBN 32
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_WIDTH 32
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LEN 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LBN 64
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_WIDTH 32
/* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */
#define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8
@@ -1347,7 +1384,13 @@
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS
#define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */
#define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */
@@ -1382,7 +1425,13 @@
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS
#define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */
#define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */
@@ -1415,7 +1464,13 @@
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK
/* MC_CMD_FC_OUT_MAC msgresponse */
@@ -1636,7 +1691,13 @@
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LBN 128
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_WIDTH 32
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LBN 160
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_WIDTH 32
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28
@@ -1976,12 +2037,24 @@
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LBN 64
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LBN 96
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_WIDTH 32
/* Length of address map */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LBN 128
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LBN 160
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_WIDTH 32
/* Component information field */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24
#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4
@@ -1989,7 +2062,13 @@
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LBN 224
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LBN 256
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_WIDTH 32
/* Name of the component */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36
#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1
@@ -2132,7 +2211,13 @@
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LBN 96
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LBN 128
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_WIDTH 32
/* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */
#define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)
@@ -2153,7 +2238,13 @@
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LBN 32
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LBN 64
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK
/* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */
@@ -2222,12 +2313,24 @@
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LBN 32
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LBN 64
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_WIDTH 32
/* AOE address from which to transfer data */
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LBN 96
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LBN 128
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_WIDTH 32
/* Length of AOE transfer (total) */
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4
@@ -2243,12 +2346,24 @@
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LBN 288
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LBN 320
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_WIDTH 32
/* When active, end read time */
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LBN 352
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LBN 384
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_WIDTH 32
/* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */
#define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0
@@ -2263,7 +2378,13 @@
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LEN 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LBN 32
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_WIDTH 32
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LEN 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LBN 64
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_WIDTH 32
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16
@@ -2311,7 +2432,13 @@
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LBN 0
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LBN 32
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_WIDTH 32
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127
@@ -2391,6 +2518,7 @@
* AOE operations on MC
*/
#define MC_CMD_AOE 0xa
+#define MC_CMD_AOE_MSGSET 0xa
/* MC_CMD_AOE_IN msgrequest */
#define MC_CMD_AOE_IN_LEN 4
@@ -2580,7 +2708,13 @@
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LEN 4
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LBN 64
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LEN 4
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LBN 96
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4
#define MC_CMD_AOE_IN_MAC_STATS_DMA_OFST 16
@@ -3024,7 +3158,13 @@
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
/* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h
index be570bc0a..e8fbb6f94 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h
@@ -6,7 +6,7 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
* rebuild this file with "make mcdi_headers_v5".
*
* The version of this file has MCDI strings really used in the libefx.
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v3 2/3] common/sfc_efx/base: add MAE VLAN presence match bits
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (8 preceding siblings ...)
2021-05-24 11:18 ` [dpdk-dev] [PATCH v3 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
@ 2021-05-24 11:18 ` Ivan Malov
2021-05-24 11:18 ` [dpdk-dev] [PATCH v3 3/3] net/sfc: support matching on VLAN presence in transfer rules Ivan Malov
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
11 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-24 11:18 UTC (permalink / raw)
To: dev
Cc: Ray Kinsella, Ferruh Yigit, Andrew Rybchenko, Andy Moreton, Neil Horman
Introduce necessary infrastructure for these fields to
be set, validated and compared during class comparison.
Enumeration and mappings envisaged are MCDI-compatible.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
---
drivers/common/sfc_efx/base/efx.h | 18 ++
drivers/common/sfc_efx/base/efx_impl.h | 3 +-
drivers/common/sfc_efx/base/efx_mae.c | 235 ++++++++++++++++++++++++-
drivers/common/sfc_efx/version.map | 1 +
4 files changed, 254 insertions(+), 3 deletions(-)
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 771fe5a17..8e13075b0 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -4103,6 +4103,10 @@ efx_mae_match_spec_fini(
__in efx_mae_match_spec_t *spec);
typedef enum efx_mae_field_id_e {
+ /*
+ * Fields which can be set by efx_mae_match_spec_field_set()
+ * or by using dedicated field-specific helper APIs.
+ */
EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
EFX_MAE_FIELD_ETHER_TYPE_BE,
EFX_MAE_FIELD_ETH_SADDR_BE,
@@ -4140,6 +4144,12 @@ typedef enum efx_mae_field_id_e {
EFX_MAE_FIELD_ENC_VNET_ID_BE,
EFX_MAE_FIELD_OUTER_RULE_ID,
+ /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
+ EFX_MAE_FIELD_HAS_OVLAN,
+ EFX_MAE_FIELD_HAS_IVLAN,
+ EFX_MAE_FIELD_ENC_HAS_OVLAN,
+ EFX_MAE_FIELD_ENC_HAS_IVLAN,
+
EFX_MAE_FIELD_NIDS
} efx_mae_field_id_t;
@@ -4198,6 +4208,14 @@ efx_mae_match_spec_field_set(
__in size_t mask_size,
__in_bcount(mask_size) const uint8_t *mask);
+/* The corresponding mask will be set to B_TRUE. */
+LIBEFX_API
+extern __checkReturn efx_rc_t
+efx_mae_match_spec_bit_set(
+ __in efx_mae_match_spec_t *spec,
+ __in efx_mae_field_id_t field_id,
+ __in boolean_t value);
+
/* If the mask argument is NULL, the API will use full mask by default. */
LIBEFX_API
extern __checkReturn efx_rc_t
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 4a513171a..8b63cfb37 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1720,7 +1720,8 @@ struct efx_mae_match_spec_s {
efx_mae_rule_type_t emms_type;
uint32_t emms_prio;
union emms_mask_value_pairs {
- uint8_t action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
+ uint8_t action[
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN];
uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN];
} emms_mask_value_pairs;
};
diff --git a/drivers/common/sfc_efx/base/efx_mae.c b/drivers/common/sfc_efx/base/efx_mae.c
index c1784211e..569748804 100644
--- a/drivers/common/sfc_efx/base/efx_mae.c
+++ b/drivers/common/sfc_efx/base/efx_mae.c
@@ -465,6 +465,10 @@ typedef enum efx_mae_field_cap_id_e {
EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
+ EFX_MAE_FIELD_ID_HAS_OVLAN = MAE_FIELD_HAS_OVLAN,
+ EFX_MAE_FIELD_ID_HAS_IVLAN = MAE_FIELD_HAS_IVLAN,
+ EFX_MAE_FIELD_ID_ENC_HAS_OVLAN = MAE_FIELD_ENC_HAS_OVLAN,
+ EFX_MAE_FIELD_ID_ENC_HAS_IVLAN = MAE_FIELD_ENC_HAS_IVLAN,
EFX_MAE_FIELD_CAP_NIDS
} efx_mae_field_cap_id_t;
@@ -591,6 +595,65 @@ static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
#undef EFX_MAE_MV_DESC_ALT
#undef EFX_MAE_MV_DESC
+};
+
+/*
+ * The following structure is a means to describe an MAE bit.
+ * The information in it is meant to be used internally by
+ * APIs for addressing a given flag in a mask-value pairs
+ * structure and for validation purposes.
+ */
+typedef struct efx_mae_mv_bit_desc_s {
+ /*
+ * Arrays using this struct are indexed by field IDs.
+ * Fields which aren't meant to be referenced by these
+ * arrays comprise gaps (invalid entries). Below field
+ * helps to identify such entries.
+ */
+ boolean_t emmbd_entry_is_valid;
+ efx_mae_field_cap_id_t emmbd_bit_cap_id;
+ size_t emmbd_value_ofst;
+ unsigned int emmbd_value_lbn;
+ size_t emmbd_mask_ofst;
+ unsigned int emmbd_mask_lbn;
+} efx_mae_mv_bit_desc_t;
+
+static const efx_mae_mv_bit_desc_t __efx_mae_outer_rule_mv_bit_desc_set[] = {
+#define EFX_MAE_MV_BIT_DESC(_name) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ B_TRUE, \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_LBN, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_LBN, \
+ }
+
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
+
+#undef EFX_MAE_MV_BIT_DESC
+};
+
+static const efx_mae_mv_bit_desc_t __efx_mae_action_rule_mv_bit_desc_set[] = {
+#define EFX_MAE_MV_BIT_DESC(_name) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ B_TRUE, \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
+ }
+
+ EFX_MAE_MV_BIT_DESC(HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(HAS_IVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
+
+#undef EFX_MAE_MV_BIT_DESC
};
__checkReturn efx_rc_t
@@ -789,6 +852,70 @@ efx_mae_match_spec_field_set(
EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mae_match_spec_bit_set(
+ __in efx_mae_match_spec_t *spec,
+ __in efx_mae_field_id_t field_id,
+ __in boolean_t value)
+{
+ const efx_mae_mv_bit_desc_t *bit_descp;
+ unsigned int bit_desc_set_nentries;
+ unsigned int byte_idx;
+ unsigned int bit_idx;
+ uint8_t *mvp;
+ efx_rc_t rc;
+
+ switch (spec->emms_type) {
+ case EFX_MAE_RULE_OUTER:
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
+ bit_descp = &__efx_mae_outer_rule_mv_bit_desc_set[field_id];
+ mvp = spec->emms_mask_value_pairs.outer;
+ break;
+ case EFX_MAE_RULE_ACTION:
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
+ bit_descp = &__efx_mae_action_rule_mv_bit_desc_set[field_id];
+ mvp = spec->emms_mask_value_pairs.action;
+ break;
+ default:
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if ((unsigned int)field_id >= bit_desc_set_nentries) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE) {
+ rc = EINVAL;
+ goto fail3;
+ }
+
+ byte_idx = bit_descp->emmbd_value_ofst + bit_descp->emmbd_value_lbn / 8;
+ bit_idx = bit_descp->emmbd_value_lbn % 8;
+
+ if (value != B_FALSE)
+ mvp[byte_idx] |= (1U << bit_idx);
+ else
+ mvp[byte_idx] &= ~(1U << bit_idx);
+
+ byte_idx = bit_descp->emmbd_mask_ofst + bit_descp->emmbd_mask_lbn / 8;
+ bit_idx = bit_descp->emmbd_mask_lbn % 8;
+ mvp[byte_idx] |= (1U << bit_idx);
+
+ return (0);
+
fail3:
EFSYS_PROBE(fail3);
fail2:
@@ -905,6 +1032,8 @@ efx_mae_match_spec_is_valid(
const efx_mae_field_cap_t *field_caps;
const efx_mae_mv_desc_t *desc_setp;
unsigned int desc_set_nentries;
+ const efx_mae_mv_bit_desc_t *bit_desc_setp;
+ unsigned int bit_desc_set_nentries;
boolean_t is_valid = B_TRUE;
efx_mae_field_id_t field_id;
const uint8_t *mvp;
@@ -915,6 +1044,9 @@ efx_mae_match_spec_is_valid(
desc_setp = __efx_mae_outer_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
mvp = spec->emms_mask_value_pairs.outer;
break;
case EFX_MAE_RULE_ACTION:
@@ -922,6 +1054,9 @@ efx_mae_match_spec_is_valid(
desc_setp = __efx_mae_action_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
mvp = spec->emms_mask_value_pairs.action;
break;
default:
@@ -989,6 +1124,48 @@ efx_mae_match_spec_is_valid(
break;
}
+ if (is_valid == B_FALSE)
+ return (B_FALSE);
+ }
+
+ for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
+ ++field_id) {
+ const efx_mae_mv_bit_desc_t *bit_descp =
+ &bit_desc_setp[field_id];
+ unsigned int byte_idx =
+ bit_descp->emmbd_mask_ofst +
+ bit_descp->emmbd_mask_lbn / 8;
+ unsigned int bit_idx =
+ bit_descp->emmbd_mask_lbn % 8;
+ efx_mae_field_cap_id_t bit_cap_id =
+ bit_descp->emmbd_bit_cap_id;
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE)
+ continue; /* Skip array gap */
+
+ if ((unsigned int)bit_cap_id >= field_ncaps) {
+ /* No capability for this bit = unsupported. */
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
+ if (is_valid == B_FALSE)
+ break;
+ else
+ continue;
+ }
+
+ switch (field_caps[bit_cap_id].emfc_support) {
+ case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
+ is_valid = B_TRUE;
+ break;
+ case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) != 0);
+ break;
+ case MAE_FIELD_SUPPORTED_MATCH_NEVER:
+ case MAE_FIELD_UNSUPPORTED:
+ default:
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
+ break;
+ }
+
if (is_valid == B_FALSE)
break;
}
@@ -1542,6 +1719,8 @@ efx_mae_match_specs_class_cmp(
const efx_mae_field_cap_t *field_caps;
const efx_mae_mv_desc_t *desc_setp;
unsigned int desc_set_nentries;
+ const efx_mae_mv_bit_desc_t *bit_desc_setp;
+ unsigned int bit_desc_set_nentries;
boolean_t have_same_class = B_TRUE;
efx_mae_field_id_t field_id;
const uint8_t *mvpl;
@@ -1554,6 +1733,9 @@ efx_mae_match_specs_class_cmp(
desc_setp = __efx_mae_outer_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
mvpl = left->emms_mask_value_pairs.outer;
mvpr = right->emms_mask_value_pairs.outer;
break;
@@ -1562,6 +1744,9 @@ efx_mae_match_specs_class_cmp(
desc_setp = __efx_mae_action_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
mvpl = left->emms_mask_value_pairs.action;
mvpr = right->emms_mask_value_pairs.action;
break;
@@ -1634,6 +1819,52 @@ efx_mae_match_specs_class_cmp(
}
}
+ if (have_same_class == B_FALSE)
+ goto done;
+
+ for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
+ ++field_id) {
+ const efx_mae_mv_bit_desc_t *bit_descp =
+ &bit_desc_setp[field_id];
+ efx_mae_field_cap_id_t bit_cap_id =
+ bit_descp->emmbd_bit_cap_id;
+ unsigned int byte_idx;
+ unsigned int bit_idx;
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE)
+ continue; /* Skip array gap */
+
+ if ((unsigned int)bit_cap_id >= field_ncaps)
+ break;
+
+ byte_idx =
+ bit_descp->emmbd_mask_ofst +
+ bit_descp->emmbd_mask_lbn / 8;
+ bit_idx =
+ bit_descp->emmbd_mask_lbn % 8;
+
+ if (field_caps[bit_cap_id].emfc_mask_affects_class &&
+ (mvpl[byte_idx] & (1U << bit_idx)) !=
+ (mvpr[byte_idx] & (1U << bit_idx))) {
+ have_same_class = B_FALSE;
+ break;
+ }
+
+ byte_idx =
+ bit_descp->emmbd_value_ofst +
+ bit_descp->emmbd_value_lbn / 8;
+ bit_idx =
+ bit_descp->emmbd_value_lbn % 8;
+
+ if (field_caps[bit_cap_id].emfc_match_affects_class &&
+ (mvpl[byte_idx] & (1U << bit_idx)) !=
+ (mvpr[byte_idx] & (1U << bit_idx))) {
+ have_same_class = B_FALSE;
+ break;
+ }
+ }
+
+done:
*have_same_classp = have_same_class;
return (0);
@@ -2282,10 +2513,10 @@ efx_mae_action_rule_insert(
* MCDI request and are thus safe to be copied directly to the buffer.
*/
EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
- MAE_FIELD_MASK_VALUE_PAIRS_LEN);
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
memcpy(payload + offset, spec->emms_mask_value_pairs.action,
- MAE_FIELD_MASK_VALUE_PAIRS_LEN);
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
efx_mcdi_execute(enp, &req);
diff --git a/drivers/common/sfc_efx/version.map b/drivers/common/sfc_efx/version.map
index 5e724fd10..75da5aa5c 100644
--- a/drivers/common/sfc_efx/version.map
+++ b/drivers/common/sfc_efx/version.map
@@ -106,6 +106,7 @@ INTERNAL {
efx_mae_fini;
efx_mae_get_limits;
efx_mae_init;
+ efx_mae_match_spec_bit_set;
efx_mae_match_spec_field_set;
efx_mae_match_spec_fini;
efx_mae_match_spec_init;
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v3 3/3] net/sfc: support matching on VLAN presence in transfer rules
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (9 preceding siblings ...)
2021-05-24 11:18 ` [dpdk-dev] [PATCH v3 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
@ 2021-05-24 11:18 ` Ivan Malov
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
11 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-24 11:18 UTC (permalink / raw)
To: dev; +Cc: Ray Kinsella, Ferruh Yigit, Andrew Rybchenko, Andy Moreton
Take into account VLAN presence fields in items ETH and VLAN.
Provided that the item ETH does not match on the EtherType,
the pattern behaviour will be as follows:
- ETH (mask->has_vlan = 0) | IPv4 = match both tagged and untagged;
- ETH (mask->has_vlan = 1) | IPv4 = match as per spec->has_vlan;
- ETH (mask->has_vlan = 0) | VLAN | IPv4 = match only tagged.
Similar logic applies to double tagging.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
---
drivers/net/sfc/sfc_mae.c | 124 ++++++++++++++++++++++++++++++++------
drivers/net/sfc/sfc_mae.h | 19 +++++-
2 files changed, 123 insertions(+), 20 deletions(-)
diff --git a/drivers/net/sfc/sfc_mae.c b/drivers/net/sfc/sfc_mae.c
index a2c0aa143..33bff275c 100644
--- a/drivers/net/sfc/sfc_mae.c
+++ b/drivers/net/sfc/sfc_mae.c
@@ -728,6 +728,7 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
RTE_BE16(RTE_ETHER_TYPE_QINQ2),
RTE_BE16(RTE_ETHER_TYPE_QINQ3),
};
+ bool enforce_tag_presence[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {0};
unsigned int nb_supported_tpids = RTE_DIM(supported_tpids);
unsigned int ethertype_idx;
const uint8_t *valuep;
@@ -753,6 +754,22 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
ethertype_idx < pdata->nb_vlan_tags; ++ethertype_idx) {
unsigned int tpid_idx;
+ /*
+ * This loop can have only two iterations. On the second one,
+ * drop outer tag presence enforcement bit because the inner
+ * tag presence automatically assumes that for the outer tag.
+ */
+ enforce_tag_presence[0] = B_FALSE;
+
+ if (ethertypes[ethertype_idx].mask == RTE_BE16(0)) {
+ if (pdata->tci_masks[ethertype_idx] == RTE_BE16(0))
+ enforce_tag_presence[ethertype_idx] = B_TRUE;
+
+ /* No match on this field, and no value check. */
+ nb_supported_tpids = 1;
+ continue;
+ }
+
/* Exact match is supported only. */
if (ethertypes[ethertype_idx].mask != RTE_BE16(0xffff)) {
rc = EINVAL;
@@ -812,6 +829,24 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
}
}
+ if (enforce_tag_presence[0] || pdata->has_ovlan_mask) {
+ rc = efx_mae_match_spec_bit_set(ctx->match_spec,
+ fremap[EFX_MAE_FIELD_HAS_OVLAN],
+ enforce_tag_presence[0] ||
+ pdata->has_ovlan_value);
+ if (rc != 0)
+ goto fail;
+ }
+
+ if (enforce_tag_presence[1] || pdata->has_ivlan_mask) {
+ rc = efx_mae_match_spec_bit_set(ctx->match_spec,
+ fremap[EFX_MAE_FIELD_HAS_IVLAN],
+ enforce_tag_presence[1] ||
+ pdata->has_ivlan_value);
+ if (rc != 0)
+ goto fail;
+ }
+
valuep = (const uint8_t *)&pdata->l3_next_proto_value;
maskp = (const uint8_t *)&pdata->l3_next_proto_mask;
rc = efx_mae_match_spec_field_set(ctx->match_spec,
@@ -1154,6 +1189,7 @@ sfc_mae_rule_parse_item_eth(const struct rte_flow_item *item,
sfc_mae_item_build_supp_mask(flocs_eth, RTE_DIM(flocs_eth),
&supp_mask, sizeof(supp_mask));
+ supp_mask.has_vlan = 1;
rc = sfc_flow_parse_init(item,
(const void **)&spec, (const void **)&mask,
@@ -1172,14 +1208,23 @@ sfc_mae_rule_parse_item_eth(const struct rte_flow_item *item,
item_spec = (const struct rte_flow_item_eth *)spec;
item_mask = (const struct rte_flow_item_eth *)mask;
+ /*
+ * Remember various match criteria in the parsing context.
+ * sfc_mae_rule_process_pattern_data() will consider them
+ * altogether when the rest of the items have been parsed.
+ */
ethertypes[0].value = item_spec->type;
ethertypes[0].mask = item_mask->type;
+ if (item_mask->has_vlan) {
+ pdata->has_ovlan_mask = B_TRUE;
+ if (item_spec->has_vlan)
+ pdata->has_ovlan_value = B_TRUE;
+ }
} else {
/*
- * The specification is empty. This is wrong in the case
- * when there are more network patterns in line. Other
- * than that, any Ethernet can match. All of that is
- * checked at the end of parsing.
+ * The specification is empty. The overall pattern
+ * validity will be enforced at the end of parsing.
+ * See sfc_mae_rule_process_pattern_data().
*/
return 0;
}
@@ -1229,6 +1274,16 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
{
struct sfc_mae_parse_ctx *ctx_mae = ctx->mae;
struct sfc_mae_pattern_data *pdata = &ctx_mae->pattern_data;
+ boolean_t *has_vlan_mp_by_nb_tags[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {
+ &pdata->has_ovlan_mask,
+ &pdata->has_ivlan_mask,
+ };
+ boolean_t *has_vlan_vp_by_nb_tags[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {
+ &pdata->has_ovlan_value,
+ &pdata->has_ivlan_value,
+ };
+ boolean_t *cur_tag_presence_bit_mp;
+ boolean_t *cur_tag_presence_bit_vp;
const struct sfc_mae_field_locator *flocs;
struct rte_flow_item_vlan supp_mask;
const uint8_t *spec = NULL;
@@ -1244,14 +1299,27 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
"Can't match that many VLAN tags");
}
+ cur_tag_presence_bit_mp = has_vlan_mp_by_nb_tags[pdata->nb_vlan_tags];
+ cur_tag_presence_bit_vp = has_vlan_vp_by_nb_tags[pdata->nb_vlan_tags];
+
+ if (*cur_tag_presence_bit_mp == B_TRUE &&
+ *cur_tag_presence_bit_vp == B_FALSE) {
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "The previous item enforces no (more) VLAN, "
+ "so the current item (VLAN) must not exist");
+ }
+
nb_flocs = RTE_DIM(flocs_vlan) / SFC_MAE_MATCH_VLAN_MAX_NTAGS;
flocs = flocs_vlan + pdata->nb_vlan_tags * nb_flocs;
- /* If parsing fails, this can remain incremented. */
- ++pdata->nb_vlan_tags;
-
sfc_mae_item_build_supp_mask(flocs, nb_flocs,
&supp_mask, sizeof(supp_mask));
+ /*
+ * This only means that the field is supported by the driver and libefx.
+ * Support on NIC level will be checked when all items have been parsed.
+ */
+ supp_mask.has_more_vlan = 1;
rc = sfc_flow_parse_init(item,
(const void **)&spec, (const void **)&mask,
@@ -1262,26 +1330,44 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
return rc;
if (spec != NULL) {
- struct sfc_mae_ethertype *ethertypes = pdata->ethertypes;
+ struct sfc_mae_ethertype *et = pdata->ethertypes;
const struct rte_flow_item_vlan *item_spec;
const struct rte_flow_item_vlan *item_mask;
item_spec = (const struct rte_flow_item_vlan *)spec;
item_mask = (const struct rte_flow_item_vlan *)mask;
- ethertypes[pdata->nb_vlan_tags].value = item_spec->inner_type;
- ethertypes[pdata->nb_vlan_tags].mask = item_mask->inner_type;
- } else {
/*
- * The specification is empty. This is wrong in the case
- * when there are more network patterns in line. Other
- * than that, any Ethernet can match. All of that is
- * checked at the end of parsing.
+ * Remember various match criteria in the parsing context.
+ * sfc_mae_rule_process_pattern_data() will consider them
+ * altogether when the rest of the items have been parsed.
*/
- return 0;
+ et[pdata->nb_vlan_tags + 1].value = item_spec->inner_type;
+ et[pdata->nb_vlan_tags + 1].mask = item_mask->inner_type;
+ pdata->tci_masks[pdata->nb_vlan_tags] = item_mask->tci;
+ if (item_mask->has_more_vlan) {
+ if (pdata->nb_vlan_tags ==
+ SFC_MAE_MATCH_VLAN_MAX_NTAGS) {
+ return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "Can't use 'has_more_vlan' in "
+ "the second item VLAN");
+ }
+ pdata->has_ivlan_mask = B_TRUE;
+ if (item_spec->has_more_vlan)
+ pdata->has_ivlan_value = B_TRUE;
+ }
+
+ /* Convert TCI to MAE representation right now. */
+ rc = sfc_mae_parse_item(flocs, nb_flocs, spec, mask,
+ ctx_mae, error);
+ if (rc != 0)
+ return rc;
}
- return sfc_mae_parse_item(flocs, nb_flocs, spec, mask, ctx_mae, error);
+ ++(pdata->nb_vlan_tags);
+
+ return 0;
}
static const struct sfc_mae_field_locator flocs_ipv4[] = {
@@ -1612,6 +1698,8 @@ static const efx_mae_field_id_t field_ids_no_remap[] = {
FIELD_ID_NO_REMAP(L4_SPORT_BE),
FIELD_ID_NO_REMAP(L4_DPORT_BE),
FIELD_ID_NO_REMAP(TCP_FLAGS_BE),
+ FIELD_ID_NO_REMAP(HAS_OVLAN),
+ FIELD_ID_NO_REMAP(HAS_IVLAN),
#undef FIELD_ID_NO_REMAP
};
@@ -1642,6 +1730,8 @@ static const efx_mae_field_id_t field_ids_remap_to_encap[] = {
FIELD_ID_REMAP_TO_ENCAP(DST_IP6_BE),
FIELD_ID_REMAP_TO_ENCAP(L4_SPORT_BE),
FIELD_ID_REMAP_TO_ENCAP(L4_DPORT_BE),
+ FIELD_ID_REMAP_TO_ENCAP(HAS_OVLAN),
+ FIELD_ID_REMAP_TO_ENCAP(HAS_IVLAN),
#undef FIELD_ID_REMAP_TO_ENCAP
};
diff --git a/drivers/net/sfc/sfc_mae.h b/drivers/net/sfc/sfc_mae.h
index 9740e54e4..0241fe33c 100644
--- a/drivers/net/sfc/sfc_mae.h
+++ b/drivers/net/sfc/sfc_mae.h
@@ -130,12 +130,14 @@ struct sfc_mae_pattern_data {
*
* - If an item ETH is followed by a single item VLAN,
* the former must have "type" set to one of supported
- * TPID values (0x8100, 0x88a8, 0x9100, 0x9200, 0x9300).
+ * TPID values (0x8100, 0x88a8, 0x9100, 0x9200, 0x9300),
+ * or 0x0000/0x0000.
*
* - If an item ETH is followed by two items VLAN, the
* item ETH must have "type" set to one of supported TPID
- * values (0x88a8, 0x9100, 0x9200, 0x9300), and the outermost
- * VLAN item must have "inner_type" set to TPID value 0x8100.
+ * values (0x88a8, 0x9100, 0x9200, 0x9300), or 0x0000/0x0000,
+ * and the outermost VLAN item must have "inner_type" set
+ * to TPID value 0x8100, or 0x0000/0x0000
*
* - If a L2 item is followed by a L3 one, the former must
* indicate "type" ("inner_type") which corresponds to
@@ -156,6 +158,9 @@ struct sfc_mae_pattern_data {
* VLAN (L3 EtherType) --> ETHER_TYPE_BE
*/
struct sfc_mae_ethertype ethertypes[SFC_MAE_L2_MAX_NITEMS];
+
+ rte_be16_t tci_masks[SFC_MAE_MATCH_VLAN_MAX_NTAGS];
+
unsigned int nb_vlan_tags;
/**
@@ -191,6 +196,14 @@ struct sfc_mae_pattern_data {
*/
uint8_t l3_next_proto_restriction_value;
uint8_t l3_next_proto_restriction_mask;
+
+ /* Projected state of EFX_MAE_FIELD_HAS_OVLAN match bit */
+ bool has_ovlan_value;
+ bool has_ovlan_mask;
+
+ /* Projected state of EFX_MAE_FIELD_HAS_IVLAN match bit */
+ bool has_ivlan_value;
+ bool has_ivlan_mask;
};
struct sfc_mae_parse_ctx {
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows
2021-04-28 9:49 [dpdk-dev] [PATCH 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (10 preceding siblings ...)
2021-05-24 11:18 ` [dpdk-dev] [PATCH v3 3/3] net/sfc: support matching on VLAN presence in transfer rules Ivan Malov
@ 2021-05-24 11:48 ` Ivan Malov
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
` (3 more replies)
11 siblings, 4 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-24 11:48 UTC (permalink / raw)
To: dev; +Cc: Ray Kinsella, Ferruh Yigit
Changes in v2:
* [1/3] no longer triggers spelling warnings
Changes in v3:
* Attempt to correct mailing order of the patches
Changes in v4:
* Yet another attempt to correct mailing order of the patches
Andrew Rybchenko (1):
common/sfc_efx/base: update MCDI headers
Ivan Malov (2):
common/sfc_efx/base: add MAE VLAN presence match bits
net/sfc: support matching on VLAN presence in transfer rules
drivers/common/sfc_efx/base/efx.h | 18 +
drivers/common/sfc_efx/base/efx_impl.h | 3 +-
drivers/common/sfc_efx/base/efx_mae.c | 235 +-
drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3532 +++++++++++++++--
.../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
.../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
drivers/common/sfc_efx/version.map | 1 +
drivers/net/sfc/sfc_mae.c | 124 +-
drivers/net/sfc/sfc_mae.h | 19 +-
9 files changed, 3708 insertions(+), 368 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v4 1/3] common/sfc_efx/base: update MCDI headers
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
@ 2021-05-24 11:48 ` Ivan Malov
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
` (2 subsequent siblings)
3 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-24 11:48 UTC (permalink / raw)
To: dev; +Cc: Ray Kinsella, Ferruh Yigit, Andrew Rybchenko
From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
---
drivers/common/sfc_efx/base/efx_regs_mcdi.h | 3532 +++++++++++++++--
.../common/sfc_efx/base/efx_regs_mcdi_aoe.h | 142 +-
.../common/sfc_efx/base/efx_regs_mcdi_strs.h | 2 +-
3 files changed, 3331 insertions(+), 345 deletions(-)
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
index 976db37d6..a3c9f076e 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi.h
@@ -6,7 +6,7 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
* rebuild this file with "make mcdi_headers_v5".
*/
@@ -410,6 +410,48 @@
#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */
+/* MC_CMD_FPGA_FLASH_INDEX enum */
+#define MC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */
+#define MC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */
+
+/* MC_CMD_EXTERNAL_MAE_LINK_MODE enum */
+/* enum: Legacy mode as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0
+/* enum: Switchdev mode as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1
+/* enum: Bootstrap mode as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2
+/* enum: Link-mode change is in-progress as described in XN-200039-TC. */
+#define MC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf
+
+/* PCIE_INTERFACE enum: From EF100 onwards, SFC products can have multiple PCIe
+ * interfaces. There is a need to refer to interfaces explicitly from drivers
+ * (for example, a management driver on one interface administering a function
+ * on another interface). This enumeration provides stable identifiers to all
+ * interfaces present on a product. Product documentation will specify which
+ * interfaces exist and their associated identifier. In general, drivers,
+ * should not assign special meanings to specific values. Instead, behaviour
+ * should be determined by NIC configuration, which will identify interfaces
+ * where appropriate.
+ */
+/* enum: Primary host interfaces. Typically (i.e. for all known SFC products)
+ * the interface exposed on the edge connector (or form factor equivalent).
+ */
+#define PCIE_INTERFACE_HOST_PRIMARY 0x0
+/* enum: Riverhead and keystone products have a second PCIe interface to which
+ * an on-NIC ARM module is expected to be connected.
+ */
+#define PCIE_INTERFACE_NIC_EMBEDDED 0x1
+/* enum: For MCDI commands issued over a PCIe interface, this value is
+ * translated into the interface over which the command was issued. Not
+ * meaningful for other MCDI transports.
+ */
+#define PCIE_INTERFACE_CALLER 0xffffffff
+
+/* MC_CLIENT_ID_SPECIFIER enum */
+/* enum: Equivalent to the caller's client ID */
+#define MC_CMD_CLIENT_ID_SELF 0xffffffff
+
/* MAE_FIELD_SUPPORT_STATUS enum */
/* enum: The NIC does not support this field. The driver must ensure that any
* mask associated with this field in a match rule is zeroed. The NIC may
@@ -470,6 +512,20 @@
#define MAE_FIELD_CT_PRIVATE_FLAGS 0x8
/* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
#define MAE_FIELD_IS_FROM_NETWORK 0x9
+/* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
+#define MAE_FIELD_HAS_OVLAN 0xa
+/* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
+#define MAE_FIELD_HAS_IVLAN 0xb
+/* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
+ * when encap
+ */
+#define MAE_FIELD_ENC_HAS_OVLAN 0xc
+/* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
+ * when encap
+ */
+#define MAE_FIELD_ENC_HAS_IVLAN 0xd
+/* enum: Packet is IP fragment */
+#define MAE_FIELD_ENC_IP_FRAG 0xe
#define MAE_FIELD_ETHER_TYPE 0x21 /* enum */
#define MAE_FIELD_VLAN0_TCI 0x22 /* enum */
#define MAE_FIELD_VLAN0_PROTO 0x23 /* enum */
@@ -508,6 +564,10 @@
#define MAE_FIELD_L4_DPORT 0x33
/* enum: Inner when encap */
#define MAE_FIELD_TCP_FLAGS 0x34
+/* enum: TCP packet with any of SYN, FIN or RST flag set */
+#define MAE_FIELD_TCP_SYN_FIN_RST 0x35
+/* enum: Packet is IP fragment with fragment offset 0 */
+#define MAE_FIELD_IP_FIRST_FRAG 0x36
/* enum: The type of encapsulated used for this packet. Value as per
* ENCAP_TYPE_*.
*/
@@ -550,8 +610,8 @@
#define MAE_FIELD_ENC_L4_SPORT 0x52
/* enum: Outer; only present when encap */
#define MAE_FIELD_ENC_L4_DPORT 0x53
-/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Outer; only present when
- * encap
+/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Bottom 24 bits of Key
+ * (when L2GRE) Outer; only present when encap
*/
#define MAE_FIELD_ENC_VNET_ID 0x54
@@ -566,6 +626,14 @@
#define MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */
#define MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */
+/* MAE_MPORT_END enum: Selects which end of the logical link identified by an
+ * MPORT_SELECTOR is targeted by an operation.
+ */
+/* enum: Selects the port on the MAE virtual switch */
+#define MAE_MPORT_END_MAE 0x1
+/* enum: Selects the virtual NIC plugged into the MAE switch */
+#define MAE_MPORT_END_VNIC 0x2
+
/* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF100
* platforms
*/
@@ -647,17 +715,21 @@
#define MCDI_EVENT_TX_ERR_TYPE_OFST 0
#define MCDI_EVENT_TX_ERR_TYPE_LBN 12
#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
-/* enum: Descriptor loader reported failure */
+/* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */
#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
-/* enum: Descriptor ring empty and no EOP seen for packet */
+/* enum: Descriptor ring empty and no EOP seen for packet. Specific to
+ * EF10-family NICs
+ */
#define MCDI_EVENT_TX_ERR_NO_EOP 0x2
-/* enum: Overlength packet */
+/* enum: Overlength packet. Specific to EF10-family NICs. */
#define MCDI_EVENT_TX_ERR_2BIG 0x3
-/* enum: Malformed option descriptor */
+/* enum: Malformed option descriptor. Specific to EF10-family NICs. */
#define MCDI_EVENT_TX_BAD_OPTDESC 0x5
-/* enum: Option descriptor part way through a packet */
+/* enum: Option descriptor part way through a packet. Specific to EF10-family
+ * NICs.
+ */
#define MCDI_EVENT_TX_OPT_IN_PKT 0x8
-/* enum: DMA or PIO data access error */
+/* enum: DMA or PIO data access error. Specific to EF10-family NICs */
#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
#define MCDI_EVENT_TX_ERR_INFO_OFST 0
#define MCDI_EVENT_TX_ERR_INFO_LBN 16
@@ -1270,7 +1342,13 @@
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 4
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LBN 64
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_WIDTH 32
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 4
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LBN 96
+#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_WIDTH 32
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126
@@ -1384,6 +1462,7 @@
* has additional checks to reject insecure calls.
*/
#define MC_CMD_READ32 0x1
+#define MC_CMD_READ32_MSGSET 0x1
#undef MC_CMD_0x1_PRIVILEGE_CTG
#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -1413,6 +1492,7 @@
* Write multiple 32byte words to MC memory.
*/
#define MC_CMD_WRITE32 0x2
+#define MC_CMD_WRITE32_MSGSET 0x2
#undef MC_CMD_0x2_PRIVILEGE_CTG
#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -1442,6 +1522,7 @@
* has additional checks to reject insecure calls.
*/
#define MC_CMD_COPYCODE 0x3
+#define MC_CMD_COPYCODE_MSGSET 0x3
#undef MC_CMD_0x3_PRIVILEGE_CTG
#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -1505,6 +1586,7 @@
* Select function for function-specific commands.
*/
#define MC_CMD_SET_FUNC 0x4
+#define MC_CMD_SET_FUNC_MSGSET 0x4
#undef MC_CMD_0x4_PRIVILEGE_CTG
#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -1524,6 +1606,7 @@
* Get the instruction address from which the MC booted.
*/
#define MC_CMD_GET_BOOT_STATUS 0x5
+#define MC_CMD_GET_BOOT_STATUS_MSGSET 0x5
#undef MC_CMD_0x5_PRIVILEGE_CTG
#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -1558,6 +1641,7 @@
* fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
*/
#define MC_CMD_GET_ASSERTS 0x6
+#define MC_CMD_GET_ASSERTS_MSGSET 0x6
#undef MC_CMD_0x6_PRIVILEGE_CTG
#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -1682,12 +1766,24 @@
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LBN 2080
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_WIDTH 32
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LBN 2112
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_WIDTH 32
/* MC firmware version number */
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LBN 2144
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_WIDTH 32
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LBN 2176
+#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_WIDTH 32
/* MC firmware security level */
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276
#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
@@ -1705,6 +1801,7 @@
* sensor notifications and MCDI completions
*/
#define MC_CMD_LOG_CTRL 0x7
+#define MC_CMD_LOG_CTRL_MSGSET 0x7
#undef MC_CMD_0x7_PRIVILEGE_CTG
#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -1731,6 +1828,7 @@
* Get version information about adapter components.
*/
#define MC_CMD_GET_VERSION 0x8
+#define MC_CMD_GET_VERSION_MSGSET 0x8
#undef MC_CMD_0x8_PRIVILEGE_CTG
#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -1771,7 +1869,13 @@
#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_OUT_VERSION_LO_WIDTH 32
#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_OUT_VERSION_HI_WIDTH 32
/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
@@ -1787,7 +1891,13 @@
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_WIDTH 32
#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
@@ -1811,7 +1921,13 @@
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_WIDTH 32
#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_WIDTH 32
/* extra info */
#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32
#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16
@@ -1833,6 +1949,33 @@
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
/* MC firmware unique build ID (as binary SHA-1 value) */
#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52
#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20
@@ -1850,7 +1993,13 @@
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
/* The ID of the SUC chip. This is specific to the platform but typically
* indicates family, memory sizes etc. See SF-116728-SW for further details.
*/
@@ -1864,7 +2013,13 @@
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
/* FPGA version as three numbers. On Riverhead based systems this field uses
* the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
* FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
@@ -1886,12 +2041,496 @@
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240
#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64
+/* MC_CMD_GET_VERSION_V3_OUT msgresponse: Extended response providing version
+ * information for all adapter components. For Riverhead based designs, base MC
+ * firmware version fields refer to NMC firmware, while CMC firmware data is in
+ * dedicated CMC fields. Flags indicate which data is present in the response
+ * (depending on which components exist on a particular adapter)
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_LEN 328
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_WIDTH 32
+/* extra info */
+#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_LEN 64
+/* The version of the datapath hardware design as three number - a.b.c */
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_OFST 304
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_NUM 3
+/* The version of the firmware library used to control the datapath as three
+ * number - a.b.c
+ */
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_OFST 316
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_NUM 3
+
+/* MC_CMD_GET_VERSION_V4_OUT msgresponse: Extended response providing SoC
+ * version information
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_LEN 392
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_WIDTH 32
+/* extra info */
+#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_LEN 64
+/* The version of the datapath hardware design as three number - a.b.c */
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_OFST 304
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_NUM 3
+/* The version of the firmware library used to control the datapath as three
+ * number - a.b.c
+ */
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_OFST 316
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_NUM 3
+/* The SOC boot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_OFST 328
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4
+/* The SOC uboot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_OFST 344
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4
+/* The SOC main rootfs version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
+/* The SOC recovery buildroot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
+
+/* MC_CMD_GET_VERSION_V5_OUT msgresponse: Extended response providing bundle
+ * and board version information
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_LEN 424
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
+/* Enum values, see field(s): */
+/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4
+#define MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4
+/* 128bit mask of functions supported by the current firmware */
+#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_OFST 8
+#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_LEN 16
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_OFST 24
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LEN 8
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_OFST 24
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LBN 192
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_OFST 28
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LBN 224
+#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_WIDTH 32
+/* extra info */
+#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_OFST 32
+#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_LEN 16
+/* Flags indicating which extended fields are valid */
+#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_LBN 2
+#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_LBN 11
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_LBN 12
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_WIDTH 1
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_OFST 48
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_LBN 13
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
+/* MC firmware unique build ID (as binary SHA-1 value) */
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_OFST 52
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_LEN 20
+/* MC firmware security level */
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_OFST 72
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4
+/* MC firmware build name (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_OFST 76
+#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_LEN 64
+/* The SUC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_OFST 140
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4
+/* SUC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_OFST 156
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_OFST 156
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_OFST 160
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
+/* The ID of the SUC chip. This is specific to the platform but typically
+ * indicates family, memory sizes etc. See SF-116728-SW for further details.
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_OFST 164
+#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4
+/* The CMC firmware version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_OFST 168
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4
+/* CMC firmware build date (as 64-bit Unix timestamp) */
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_OFST 184
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LEN 8
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_OFST 184
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_OFST 188
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
+#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
+/* FPGA version as three numbers. On Riverhead based systems this field uses
+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
+ * => B, ...) FPGA_VERSION[2]: Sub-revision number
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_OFST 192
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_NUM 3
+/* Extra FPGA revision information (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_OFST 204
+#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_LEN 16
+/* Board name / adapter model (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_OFST 220
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_LEN 16
+/* Board revision number */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_OFST 236
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4
+/* Board serial number (as null-terminated US-ASCII string) */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_OFST 240
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_LEN 64
+/* The version of the datapath hardware design as three number - a.b.c */
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_OFST 304
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_NUM 3
+/* The version of the firmware library used to control the datapath as three
+ * number - a.b.c
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_OFST 316
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_NUM 3
+/* The SOC boot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_OFST 328
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4
+/* The SOC uboot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_OFST 344
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4
+/* The SOC main rootfs version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
+/* The SOC recovery buildroot version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
+/* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
+ * BOARD_REVISION field
+ */
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_OFST 392
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4
+/* Bundle version as four numbers - a.b.c.d */
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_OFST 408
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4
+#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4
+
/***********************************/
/* MC_CMD_PTP
* Perform PTP operation
*/
#define MC_CMD_PTP 0xb
+#define MC_CMD_PTP_MSGSET 0xb
#undef MC_CMD_0xb_PRIVILEGE_CTG
#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -2066,7 +2705,13 @@
#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
+#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LBN 64
+#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_WIDTH 32
#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
+#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LBN 96
+#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_WIDTH 32
/* enum: Number of fractional bits in frequency adjustment */
#define MC_CMD_PTP_IN_ADJUST_BITS 0x28
/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
@@ -2097,7 +2742,13 @@
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LBN 64
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_WIDTH 32
#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LBN 96
+#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_WIDTH 32
/* enum: Number of fractional bits in frequency adjustment */
/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
@@ -2136,7 +2787,13 @@
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LBN 96
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_WIDTH 32
#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LBN 128
+#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_WIDTH 32
/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
@@ -2252,7 +2909,13 @@
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LBN 64
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_WIDTH 32
#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LBN 96
+#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_WIDTH 32
/* Enum values, see field(s): */
/* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */
@@ -2283,7 +2946,13 @@
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LBN 96
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_WIDTH 32
#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LBN 128
+#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_WIDTH 32
/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
@@ -2745,6 +3414,7 @@
* Read 32bit words from the indirect memory map.
*/
#define MC_CMD_CSR_READ32 0xc
+#define MC_CMD_CSR_READ32_MSGSET 0xc
#undef MC_CMD_0xc_PRIVILEGE_CTG
#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -2778,6 +3448,7 @@
* Write 32bit dwords to the indirect memory map.
*/
#define MC_CMD_CSR_WRITE32 0xd
+#define MC_CMD_CSR_WRITE32_MSGSET 0xd
#undef MC_CMD_0xd_PRIVILEGE_CTG
#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -2811,6 +3482,7 @@
* MCDI command to avoid creating too many MCDI commands.
*/
#define MC_CMD_HP 0x54
+#define MC_CMD_HP_MSGSET 0x54
#undef MC_CMD_0x54_PRIVILEGE_CTG
#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -2834,7 +3506,13 @@
#define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
#define MC_CMD_HP_IN_OCSD_ADDR_LEN 8
#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
+#define MC_CMD_HP_IN_OCSD_ADDR_LO_LEN 4
+#define MC_CMD_HP_IN_OCSD_ADDR_LO_LBN 32
+#define MC_CMD_HP_IN_OCSD_ADDR_LO_WIDTH 32
#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
+#define MC_CMD_HP_IN_OCSD_ADDR_HI_LEN 4
+#define MC_CMD_HP_IN_OCSD_ADDR_HI_LBN 64
+#define MC_CMD_HP_IN_OCSD_ADDR_HI_WIDTH 32
/* The requested update interval, in seconds. (Or the sub-command if ADDR is
* NULL.)
*/
@@ -2858,6 +3536,7 @@
* Get stack information.
*/
#define MC_CMD_STACKINFO 0xf
+#define MC_CMD_STACKINFO_MSGSET 0xf
#undef MC_CMD_0xf_PRIVILEGE_CTG
#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -2884,6 +3563,7 @@
* MDIO register read.
*/
#define MC_CMD_MDIO_READ 0x10
+#define MC_CMD_MDIO_READ_MSGSET 0x10
#undef MC_CMD_0x10_PRIVILEGE_CTG
#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -2932,6 +3612,7 @@
* MDIO register write.
*/
#define MC_CMD_MDIO_WRITE 0x11
+#define MC_CMD_MDIO_WRITE_MSGSET 0x11
#undef MC_CMD_0x11_PRIVILEGE_CTG
#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -2980,6 +3661,7 @@
* Write DBI register(s).
*/
#define MC_CMD_DBI_WRITE 0x12
+#define MC_CMD_DBI_WRITE_MSGSET 0x12
#undef MC_CMD_0x12_PRIVILEGE_CTG
#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3033,6 +3715,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_READ32 0x14
+#define MC_CMD_PORT_READ32_MSGSET 0x14
/* MC_CMD_PORT_READ32_IN msgrequest */
#define MC_CMD_PORT_READ32_IN_LEN 4
@@ -3056,6 +3739,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_WRITE32 0x15
+#define MC_CMD_PORT_WRITE32_MSGSET 0x15
/* MC_CMD_PORT_WRITE32_IN msgrequest */
#define MC_CMD_PORT_WRITE32_IN_LEN 8
@@ -3079,6 +3763,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_READ128 0x16
+#define MC_CMD_PORT_READ128_MSGSET 0x16
/* MC_CMD_PORT_READ128_IN msgrequest */
#define MC_CMD_PORT_READ128_IN_LEN 4
@@ -3102,6 +3787,7 @@
* access is implied by the Shared memory channel used.
*/
#define MC_CMD_PORT_WRITE128 0x17
+#define MC_CMD_PORT_WRITE128_MSGSET 0x17
/* MC_CMD_PORT_WRITE128_IN msgrequest */
#define MC_CMD_PORT_WRITE128_IN_LEN 20
@@ -3150,6 +3836,7 @@
* Returns the MC firmware configuration structure.
*/
#define MC_CMD_GET_BOARD_CFG 0x18
+#define MC_CMD_GET_BOARD_CFG_MSGSET 0x18
#undef MC_CMD_0x18_PRIVILEGE_CTG
#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3225,6 +3912,7 @@
* Read DBI register(s) -- extended functionality
*/
#define MC_CMD_DBI_READX 0x19
+#define MC_CMD_DBI_READX_MSGSET 0x19
#undef MC_CMD_0x19_PRIVILEGE_CTG
#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3239,7 +3927,13 @@
#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
+#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 4
+#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 0
+#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_WIDTH 32
#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
+#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 4
+#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LBN 32
+#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_WIDTH 32
#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127
@@ -3283,6 +3977,7 @@
* Set the 16byte seed for the MC pseudo-random generator.
*/
#define MC_CMD_SET_RAND_SEED 0x1a
+#define MC_CMD_SET_RAND_SEED_MSGSET 0x1a
#undef MC_CMD_0x1a_PRIVILEGE_CTG
#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3302,6 +3997,7 @@
* Retrieve the history of the LTSSM, if the build supports it.
*/
#define MC_CMD_LTSSM_HIST 0x1b
+#define MC_CMD_LTSSM_HIST_MSGSET 0x1b
/* MC_CMD_LTSSM_HIST_IN msgrequest */
#define MC_CMD_LTSSM_HIST_IN_LEN 0
@@ -3330,6 +4026,7 @@
* platforms.
*/
#define MC_CMD_DRV_ATTACH 0x1c
+#define MC_CMD_DRV_ATTACH_MSGSET 0x1c
#undef MC_CMD_0x1c_PRIVILEGE_CTG
#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3524,6 +4221,7 @@
* Route UART output to circular buffer in shared memory instead.
*/
#define MC_CMD_SHMUART 0x1f
+#define MC_CMD_SHMUART_MSGSET 0x1f
/* MC_CMD_SHMUART_IN msgrequest */
#define MC_CMD_SHMUART_IN_LEN 4
@@ -3542,6 +4240,7 @@
* use MC_CMD_ENTITY_RESET instead.
*/
#define MC_CMD_PORT_RESET 0x20
+#define MC_CMD_PORT_RESET_MSGSET 0x20
#undef MC_CMD_0x20_PRIVILEGE_CTG
#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3560,6 +4259,7 @@
* extended version of the deprecated MC_CMD_PORT_RESET with added fields.
*/
#define MC_CMD_ENTITY_RESET 0x20
+#define MC_CMD_ENTITY_RESET_MSGSET 0x20
/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
/* MC_CMD_ENTITY_RESET_IN msgrequest */
@@ -3582,6 +4282,7 @@
* Read instantaneous and minimum flow control thresholds.
*/
#define MC_CMD_PCIE_CREDITS 0x21
+#define MC_CMD_PCIE_CREDITS_MSGSET 0x21
/* MC_CMD_PCIE_CREDITS_IN msgrequest */
#define MC_CMD_PCIE_CREDITS_IN_LEN 8
@@ -3617,6 +4318,7 @@
* Get histogram of RX queue fill level.
*/
#define MC_CMD_RXD_MONITOR 0x22
+#define MC_CMD_RXD_MONITOR_MSGSET 0x22
/* MC_CMD_RXD_MONITOR_IN msgrequest */
#define MC_CMD_RXD_MONITOR_IN_LEN 12
@@ -3676,6 +4378,7 @@
* Copy the given ASCII string out onto UART and/or out of the network port.
*/
#define MC_CMD_PUTS 0x23
+#define MC_CMD_PUTS_MSGSET 0x23
#undef MC_CMD_0x23_PRIVILEGE_CTG
#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -3712,6 +4415,7 @@
* 'zombie' state. Locks required: None
*/
#define MC_CMD_GET_PHY_CFG 0x24
+#define MC_CMD_GET_PHY_CFG_MSGSET 0x24
#undef MC_CMD_0x24_PRIVILEGE_CTG
#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -3868,6 +4572,7 @@
* Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
*/
#define MC_CMD_START_BIST 0x25
+#define MC_CMD_START_BIST_MSGSET 0x25
#undef MC_CMD_0x25_PRIVILEGE_CTG
#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -3908,6 +4613,7 @@
* EACCES (if PHY_LOCK is not held).
*/
#define MC_CMD_POLL_BIST 0x26
+#define MC_CMD_POLL_BIST_MSGSET 0x26
#undef MC_CMD_0x26_PRIVILEGE_CTG
#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -4077,6 +4783,7 @@
* returns). The driver must still wait for flush done/failure events as usual.
*/
#define MC_CMD_FLUSH_RX_QUEUES 0x27
+#define MC_CMD_FLUSH_RX_QUEUES_MSGSET 0x27
/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
@@ -4099,6 +4806,7 @@
* Returns a bitmask of loopback modes available at each speed.
*/
#define MC_CMD_GET_LOOPBACK_MODES 0x28
+#define MC_CMD_GET_LOOPBACK_MODES_MSGSET 0x28
#undef MC_CMD_0x28_PRIVILEGE_CTG
#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4112,7 +4820,13 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LBN 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_WIDTH 32
/* enum: None. */
#define MC_CMD_LOOPBACK_NONE 0x0
/* enum: Data. */
@@ -4195,28 +4909,52 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LBN 64
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LBN 96
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LBN 128
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LBN 160
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LBN 192
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LBN 224
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LBN 256
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LBN 288
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
@@ -4228,7 +4966,13 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LBN 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_WIDTH 32
/* enum: None. */
/* MC_CMD_LOOPBACK_NONE 0x0 */
/* enum: Data. */
@@ -4311,49 +5055,91 @@
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LBN 64
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LBN 96
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LBN 128
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LBN 160
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LBN 192
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LBN 224
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LBN 256
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LBN 288
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported 25G loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LBN 320
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LBN 352
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported 50 loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LBN 384
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LBN 416
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
/* Supported 100G loopbacks. */
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LBN 448
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_WIDTH 32
#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LBN 480
+#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_WIDTH 32
/* Enum values, see field(s): */
/* 100M */
@@ -4395,6 +5181,7 @@
* ETIME.
*/
#define MC_CMD_GET_LINK 0x29
+#define MC_CMD_GET_LINK_MSGSET 0x29
#undef MC_CMD_0x29_PRIVILEGE_CTG
#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4596,6 +5383,7 @@
* code: 0, EINVAL, ETIME, EAGAIN
*/
#define MC_CMD_SET_LINK 0x2a
+#define MC_CMD_SET_LINK_MSGSET 0x2a
#undef MC_CMD_0x2a_PRIVILEGE_CTG
#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -4686,6 +5474,7 @@
* Set identification LED state. Locks required: None. Return code: 0, EINVAL
*/
#define MC_CMD_SET_ID_LED 0x2b
+#define MC_CMD_SET_ID_LED_MSGSET 0x2b
#undef MC_CMD_0x2b_PRIVILEGE_CTG
#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -4708,6 +5497,7 @@
* Set MAC configuration. Locks required: None. Return code: 0, EINVAL
*/
#define MC_CMD_SET_MAC 0x2c
+#define MC_CMD_SET_MAC_MSGSET 0x2c
#undef MC_CMD_0x2c_PRIVILEGE_CTG
#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4724,7 +5514,13 @@
#define MC_CMD_SET_MAC_IN_ADDR_OFST 8
#define MC_CMD_SET_MAC_IN_ADDR_LEN 8
#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
+#define MC_CMD_SET_MAC_IN_ADDR_LO_LEN 4
+#define MC_CMD_SET_MAC_IN_ADDR_LO_LBN 64
+#define MC_CMD_SET_MAC_IN_ADDR_LO_WIDTH 32
#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
+#define MC_CMD_SET_MAC_IN_ADDR_HI_LEN 4
+#define MC_CMD_SET_MAC_IN_ADDR_HI_LBN 96
+#define MC_CMD_SET_MAC_IN_ADDR_HI_WIDTH 32
#define MC_CMD_SET_MAC_IN_REJECT_OFST 16
#define MC_CMD_SET_MAC_IN_REJECT_LEN 4
#define MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16
@@ -4765,7 +5561,13 @@
#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LBN 64
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_WIDTH 32
#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LBN 96
+#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_WIDTH 32
#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
#define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16
@@ -4816,6 +5618,129 @@
#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
+/* MC_CMD_SET_MAC_V3_IN msgrequest */
+#define MC_CMD_SET_MAC_V3_IN_LEN 40
+/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
+ * EtherII, VLAN, bug16011 padding).
+ */
+#define MC_CMD_SET_MAC_V3_IN_MTU_OFST 0
+#define MC_CMD_SET_MAC_V3_IN_MTU_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4
+#define MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_ADDR_OFST 8
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LEN 8
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_OFST 8
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LBN 64
+#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_OFST 12
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LBN 96
+#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_REJECT_OFST 16
+#define MC_CMD_SET_MAC_V3_IN_REJECT_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_OFST 16
+#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0
+#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_OFST 16
+#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_LBN 1
+#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_FCNTL_OFST 20
+#define MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4
+/* enum: Flow control is off. */
+/* MC_CMD_FCNTL_OFF 0x0 */
+/* enum: Respond to flow control. */
+/* MC_CMD_FCNTL_RESPOND 0x1 */
+/* enum: Respond to and Issue flow control. */
+/* MC_CMD_FCNTL_BIDIR 0x2 */
+/* enum: Auto neg flow control. */
+/* MC_CMD_FCNTL_AUTO 0x3 */
+/* enum: Priority flow control (eftest builds only). */
+/* MC_CMD_FCNTL_QBB 0x4 */
+/* enum: Issue flow control. */
+/* MC_CMD_FCNTL_GENERATE 0x5 */
+#define MC_CMD_SET_MAC_V3_IN_FLAGS_OFST 24
+#define MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_OFST 24
+#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0
+#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_WIDTH 1
+/* Select which parameters to configure. A parameter will only be modified if
+ * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
+ * capabilities then this field is ignored (and all flags are assumed to be
+ * set).
+ */
+#define MC_CMD_SET_MAC_V3_IN_CONTROL_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0
+#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_LBN 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_LBN 2
+#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_LBN 3
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_WIDTH 1
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_OFST 28
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4
+#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 1
+/* Identifies the MAC to update by the specifying the end of a logical MAE
+ * link. Setting TARGET to MAE_LINK_ENDPOINT_COMPAT is equivalent to using the
+ * previous version of the command (MC_CMD_SET_MAC_EXT). Not all possible
+ * combinations of MPORT_END and MPORT_SELECTOR in TARGET will work in all
+ * circumstances. 1. Some will always work (e.g. a VF can always address its
+ * logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC), 2. Some are not
+ * meaningful and will always fail with EINVAL (e.g. attempting to address the
+ * VNIC end of a link to a physical port), 3. Some are meaningful but require
+ * the MCDI client to have the required permission and fail with EPERM
+ * otherwise (e.g. trying to set the MAC on a VF the caller cannot administer),
+ * and 4. Some could be implementation-specific and fail with ENOTSUP if not
+ * available (no examples exist right now). See SF-123581-TC section 4.3 for
+ * more details.
+ */
+#define MC_CMD_SET_MAC_V3_IN_TARGET_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LEN 8
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LBN 256
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_OFST 36
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LBN 288
+#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 35
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 256
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 276
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 272
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 34
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_OFST 36
+#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LEN 8
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_OFST 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LBN 256
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_WIDTH 32
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_OFST 36
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LBN 288
+#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_WIDTH 32
+
/* MC_CMD_SET_MAC_OUT msgresponse */
#define MC_CMD_SET_MAC_OUT_LEN 0
@@ -4839,6 +5764,7 @@
* Returns: 0, ETIME
*/
#define MC_CMD_PHY_STATS 0x2d
+#define MC_CMD_PHY_STATS_MSGSET 0x2d
#undef MC_CMD_0x2d_PRIVILEGE_CTG
#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -4849,7 +5775,13 @@
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_WIDTH 32
/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
@@ -4921,6 +5853,7 @@
* effect. Returns: 0, ETIME
*/
#define MC_CMD_MAC_STATS 0x2e
+#define MC_CMD_MAC_STATS_MSGSET 0x2e
#undef MC_CMD_0x2e_PRIVILEGE_CTG
#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -4931,7 +5864,13 @@
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_MAC_STATS_IN_CMD_OFST 8
#define MC_CMD_MAC_STATS_IN_CMD_LEN 4
#define MC_CMD_MAC_STATS_IN_DMA_OFST 8
@@ -4974,7 +5913,13 @@
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
@@ -5130,7 +6075,13 @@
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
/* enum: Start of FEC stats buffer space, Medford2 and up */
#define MC_CMD_MAC_FEC_DMABUF_START 0x61
@@ -5163,7 +6114,13 @@
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
/* enum: Start of CTPIO stats buffer space, Medford2 and up */
#define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
@@ -5237,7 +6194,13 @@
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4
/* enum: Start of V4 stats buffer space */
#define MC_CMD_MAC_V4_DMABUF_START 0x79
@@ -5266,6 +6229,7 @@
* to be documented
*/
#define MC_CMD_SRIOV 0x30
+#define MC_CMD_SRIOV_MSGSET 0x30
/* MC_CMD_SRIOV_IN msgrequest */
#define MC_CMD_SRIOV_IN_LEN 12
@@ -5297,7 +6261,13 @@
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LBN 64
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LBN 96
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
@@ -5308,7 +6278,13 @@
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LBN 160
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 4
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LBN 192
+#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_WIDTH 32
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
@@ -5338,6 +6314,7 @@
* Returns: 0, EINVAL (invalid RID)
*/
#define MC_CMD_MEMCPY 0x31
+#define MC_CMD_MEMCPY_MSGSET 0x31
/* MC_CMD_MEMCPY_IN msgrequest */
#define MC_CMD_MEMCPY_IN_LENMIN 32
@@ -5361,6 +6338,7 @@
* Set a WoL filter.
*/
#define MC_CMD_WOL_FILTER_SET 0x32
+#define MC_CMD_WOL_FILTER_SET_MSGSET 0x32
#undef MC_CMD_0x32_PRIVILEGE_CTG
#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -5401,7 +6379,13 @@
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LBN 64
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_WIDTH 32
#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LBN 96
+#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_WIDTH 32
/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
@@ -5476,6 +6460,7 @@
* Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
*/
#define MC_CMD_WOL_FILTER_REMOVE 0x33
+#define MC_CMD_WOL_FILTER_REMOVE_MSGSET 0x33
#undef MC_CMD_0x33_PRIVILEGE_CTG
#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -5495,6 +6480,7 @@
* ENOSYS
*/
#define MC_CMD_WOL_FILTER_RESET 0x34
+#define MC_CMD_WOL_FILTER_RESET_MSGSET 0x34
#undef MC_CMD_0x34_PRIVILEGE_CTG
#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -5515,6 +6501,7 @@
* Set the MCAST hash value without otherwise reconfiguring the MAC
*/
#define MC_CMD_SET_MCAST_HASH 0x35
+#define MC_CMD_SET_MCAST_HASH_MSGSET 0x35
/* MC_CMD_SET_MCAST_HASH_IN msgrequest */
#define MC_CMD_SET_MCAST_HASH_IN_LEN 32
@@ -5533,6 +6520,7 @@
* Locks required: none. Returns: 0
*/
#define MC_CMD_NVRAM_TYPES 0x36
+#define MC_CMD_NVRAM_TYPES_MSGSET 0x36
#undef MC_CMD_0x36_PRIVILEGE_CTG
#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5595,6 +6583,7 @@
* EINVAL (bad type).
*/
#define MC_CMD_NVRAM_INFO 0x37
+#define MC_CMD_NVRAM_INFO_MSGSET 0x37
#undef MC_CMD_0x37_PRIVILEGE_CTG
#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5692,6 +6681,7 @@
* EPERM.
*/
#define MC_CMD_NVRAM_UPDATE_START 0x38
+#define MC_CMD_NVRAM_UPDATE_START_MSGSET 0x38
#undef MC_CMD_0x38_PRIVILEGE_CTG
#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5732,6 +6722,7 @@
* PHY_LOCK required and not held)
*/
#define MC_CMD_NVRAM_READ 0x39
+#define MC_CMD_NVRAM_READ_MSGSET 0x39
#undef MC_CMD_0x39_PRIVILEGE_CTG
#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5803,6 +6794,7 @@
* PHY_LOCK required and not held)
*/
#define MC_CMD_NVRAM_WRITE 0x3a
+#define MC_CMD_NVRAM_WRITE_MSGSET 0x3a
#undef MC_CMD_0x3a_PRIVILEGE_CTG
#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5838,6 +6830,7 @@
* PHY_LOCK required and not held)
*/
#define MC_CMD_NVRAM_ERASE 0x3b
+#define MC_CMD_NVRAM_ERASE_MSGSET 0x3b
#undef MC_CMD_0x3b_PRIVILEGE_CTG
#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5868,6 +6861,7 @@
* the error EPERM.
*/
#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
+#define MC_CMD_NVRAM_UPDATE_FINISH_MSGSET 0x3c
#undef MC_CMD_0x3c_PRIVILEGE_CTG
#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -5906,6 +6900,9 @@
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2
#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_OFST 8
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_LBN 3
+#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_WIDTH 1
/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
* response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
@@ -6036,6 +7033,7 @@
* DATALEN=0
*/
#define MC_CMD_REBOOT 0x3d
+#define MC_CMD_REBOOT_MSGSET 0x3d
#undef MC_CMD_0x3d_PRIVILEGE_CTG
#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -6057,6 +7055,7 @@
* thread address.
*/
#define MC_CMD_SCHEDINFO 0x3e
+#define MC_CMD_SCHEDINFO_MSGSET 0x3e
#undef MC_CMD_0x3e_PRIVILEGE_CTG
#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6083,6 +7082,7 @@
* mode to the specified value. Returns the old mode.
*/
#define MC_CMD_REBOOT_MODE 0x3f
+#define MC_CMD_REBOOT_MODE_MSGSET 0x3f
#undef MC_CMD_0x3f_PRIVILEGE_CTG
#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -6141,6 +7141,7 @@
* Locks required: None Returns: 0
*/
#define MC_CMD_SENSOR_INFO 0x41
+#define MC_CMD_SENSOR_INFO_MSGSET 0x41
#undef MC_CMD_0x41_PRIVILEGE_CTG
#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -6380,7 +7381,13 @@
#define MC_CMD_SENSOR_ENTRY_OFST 4
#define MC_CMD_SENSOR_ENTRY_LEN 8
#define MC_CMD_SENSOR_ENTRY_LO_OFST 4
+#define MC_CMD_SENSOR_ENTRY_LO_LEN 4
+#define MC_CMD_SENSOR_ENTRY_LO_LBN 32
+#define MC_CMD_SENSOR_ENTRY_LO_WIDTH 32
#define MC_CMD_SENSOR_ENTRY_HI_OFST 8
+#define MC_CMD_SENSOR_ENTRY_HI_LEN 4
+#define MC_CMD_SENSOR_ENTRY_HI_LBN 64
+#define MC_CMD_SENSOR_ENTRY_HI_WIDTH 32
#define MC_CMD_SENSOR_ENTRY_MINNUM 0
#define MC_CMD_SENSOR_ENTRY_MAXNUM 31
#define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127
@@ -6402,7 +7409,13 @@
/* MC_CMD_SENSOR_ENTRY_OFST 4 */
/* MC_CMD_SENSOR_ENTRY_LEN 8 */
/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
+/* MC_CMD_SENSOR_ENTRY_LO_LEN 4 */
+/* MC_CMD_SENSOR_ENTRY_LO_LBN 32 */
+/* MC_CMD_SENSOR_ENTRY_LO_WIDTH 32 */
/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
+/* MC_CMD_SENSOR_ENTRY_HI_LEN 4 */
+/* MC_CMD_SENSOR_ENTRY_HI_LBN 64 */
+/* MC_CMD_SENSOR_ENTRY_HI_WIDTH 32 */
/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
/* MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */
@@ -6445,6 +7458,7 @@
* STATE_WARNING. Otherwise the board should not be expected to function.
*/
#define MC_CMD_READ_SENSORS 0x42
+#define MC_CMD_READ_SENSORS_MSGSET 0x42
#undef MC_CMD_0x42_PRIVILEGE_CTG
#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -6459,7 +7473,13 @@
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_WIDTH 32
/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
@@ -6471,7 +7491,13 @@
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LBN 32
+#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_WIDTH 32
/* Size in bytes of host buffer. */
#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
@@ -6486,7 +7512,13 @@
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LBN 32
+#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_WIDTH 32
/* Size in bytes of host buffer. */
#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8
#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
@@ -6540,6 +7572,7 @@
* code: 0
*/
#define MC_CMD_GET_PHY_STATE 0x43
+#define MC_CMD_GET_PHY_STATE_MSGSET 0x43
#undef MC_CMD_0x43_PRIVILEGE_CTG
#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -6563,6 +7596,7 @@
* disable 802.Qbb for a given priority.
*/
#define MC_CMD_SETUP_8021QBB 0x44
+#define MC_CMD_SETUP_8021QBB_MSGSET 0x44
/* MC_CMD_SETUP_8021QBB_IN msgrequest */
#define MC_CMD_SETUP_8021QBB_IN_LEN 32
@@ -6578,6 +7612,7 @@
* Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
*/
#define MC_CMD_WOL_FILTER_GET 0x45
+#define MC_CMD_WOL_FILTER_GET_MSGSET 0x45
#undef MC_CMD_0x45_PRIVILEGE_CTG
#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -6597,6 +7632,7 @@
* Returns: 0, ENOSYS
*/
#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
+#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_MSGSET 0x46
#undef MC_CMD_0x46_PRIVILEGE_CTG
#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -6649,6 +7685,7 @@
* None. Returns: 0, ENOSYS
*/
#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
+#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_MSGSET 0x47
#undef MC_CMD_0x47_PRIVILEGE_CTG
#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
@@ -6669,6 +7706,7 @@
* Restore MAC after block reset. Locks required: None. Returns: 0.
*/
#define MC_CMD_MAC_RESET_RESTORE 0x48
+#define MC_CMD_MAC_RESET_RESTORE_MSGSET 0x48
/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
@@ -6684,6 +7722,7 @@
* required: None Returns: 0
*/
#define MC_CMD_TESTASSERT 0x49
+#define MC_CMD_TESTASSERT_MSGSET 0x49
#undef MC_CMD_0x49_PRIVILEGE_CTG
#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -6727,6 +7766,7 @@
* basis. Locks required: None. Returns: 0, EINVAL .
*/
#define MC_CMD_WORKAROUND 0x4a
+#define MC_CMD_WORKAROUND_MSGSET 0x4a
#undef MC_CMD_0x4a_PRIVILEGE_CTG
#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6790,6 +7830,7 @@
* Anything else: currently undefined. Locks required: None. Return code: 0.
*/
#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
+#define MC_CMD_GET_PHY_MEDIA_INFO_MSGSET 0x4b
#undef MC_CMD_0x4b_PRIVILEGE_CTG
#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6821,6 +7862,7 @@
* on the type of partition).
*/
#define MC_CMD_NVRAM_TEST 0x4c
+#define MC_CMD_NVRAM_TEST_MSGSET 0x4c
#undef MC_CMD_0x4c_PRIVILEGE_CTG
#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -6851,6 +7893,7 @@
* they are configured first. Locks required: None. Return code: 0, EINVAL.
*/
#define MC_CMD_MRSFP_TWEAK 0x4d
+#define MC_CMD_MRSFP_TWEAK_MSGSET 0x4d
/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
@@ -6894,6 +7937,7 @@
* of range.
*/
#define MC_CMD_SENSOR_SET_LIMS 0x4e
+#define MC_CMD_SENSOR_SET_LIMS_MSGSET 0x4e
#undef MC_CMD_0x4e_PRIVILEGE_CTG
#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -6925,6 +7969,7 @@
/* MC_CMD_GET_RESOURCE_LIMITS
*/
#define MC_CMD_GET_RESOURCE_LIMITS 0x4f
+#define MC_CMD_GET_RESOURCE_LIMITS_MSGSET 0x4f
/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
@@ -6947,6 +7992,7 @@
* none. Returns: 0, EINVAL (bad type).
*/
#define MC_CMD_NVRAM_PARTITIONS 0x51
+#define MC_CMD_NVRAM_PARTITIONS_MSGSET 0x51
#undef MC_CMD_0x51_PRIVILEGE_CTG
#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -6977,6 +8023,7 @@
* none. Returns: 0, EINVAL (bad type).
*/
#define MC_CMD_NVRAM_METADATA 0x52
+#define MC_CMD_NVRAM_METADATA_MSGSET 0x52
#undef MC_CMD_0x52_PRIVILEGE_CTG
#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -7035,6 +8082,7 @@
* Returns the base MAC, count and stride for the requesting function
*/
#define MC_CMD_GET_MAC_ADDRESSES 0x55
+#define MC_CMD_GET_MAC_ADDRESSES_MSGSET 0x55
#undef MC_CMD_0x55_PRIVILEGE_CTG
#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -7066,6 +8114,7 @@
* SF-120509-TC and SF-117282-PS.
*/
#define MC_CMD_CLP 0x56
+#define MC_CMD_CLP_MSGSET 0x56
#undef MC_CMD_0x56_PRIVILEGE_CTG
#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -7188,6 +8237,7 @@
* Perform a MUM operation
*/
#define MC_CMD_MUM 0x57
+#define MC_CMD_MUM_MSGSET 0x57
#undef MC_CMD_0x57_PRIVILEGE_CTG
#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -7604,7 +8654,13 @@
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 4
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LBN 32
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_WIDTH 32
#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 4
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LBN 64
+#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_WIDTH 32
/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
#define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
@@ -7789,7 +8845,13 @@
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 4
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LBN 64
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_WIDTH 32
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 4
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LBN 96
+#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_WIDTH 32
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126
@@ -7986,6 +9048,7 @@
* sensor_query SPHINX service.
*/
#define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
+#define MC_CMD_DYNAMIC_SENSORS_LIST_MSGSET 0x66
#undef MC_CMD_0x66_PRIVILEGE_CTG
#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8031,6 +9094,7 @@
* `get_descriptions` in the sensor_query SPHINX service.
*/
#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
+#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_MSGSET 0x67
#undef MC_CMD_0x67_PRIVILEGE_CTG
#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8080,6 +9144,7 @@
* in the sensor_query SPHINX service.
*/
#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
+#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_MSGSET 0x68
#undef MC_CMD_0x68_PRIVILEGE_CTG
#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8117,6 +9182,7 @@
* receive (Riverhead).
*/
#define MC_CMD_EVENT_CTRL 0x69
+#define MC_CMD_EVENT_CTRL_MSGSET 0x69
#undef MC_CMD_0x69_PRIVILEGE_CTG
#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8197,7 +9263,13 @@
#define BUFTBL_ENTRY_RAWADDR_OFST 4
#define BUFTBL_ENTRY_RAWADDR_LEN 8
#define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
+#define BUFTBL_ENTRY_RAWADDR_LO_LEN 4
+#define BUFTBL_ENTRY_RAWADDR_LO_LBN 32
+#define BUFTBL_ENTRY_RAWADDR_LO_WIDTH 32
#define BUFTBL_ENTRY_RAWADDR_HI_OFST 8
+#define BUFTBL_ENTRY_RAWADDR_HI_LEN 4
+#define BUFTBL_ENTRY_RAWADDR_HI_LBN 64
+#define BUFTBL_ENTRY_RAWADDR_HI_WIDTH 32
#define BUFTBL_ENTRY_RAWADDR_LBN 32
#define BUFTBL_ENTRY_RAWADDR_WIDTH 64
@@ -8207,14 +9279,25 @@
#define NVRAM_PARTITION_TYPE_ID_LEN 2
/* enum: Primary MC firmware partition */
#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
+/* enum: NMC firmware partition (this is intentionally an alias of MC_FIRMWARE)
+ */
+#define NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100
/* enum: Secondary MC firmware partition */
#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
/* enum: Expansion ROM partition */
#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
/* enum: Static configuration TLV partition */
#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
+/* enum: Factory configuration TLV partition (this is intentionally an alias of
+ * STATIC_CONFIG)
+ */
+#define NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400
/* enum: Dynamic configuration TLV partition */
#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
+/* enum: User configuration TLV partition (this is intentionally an alias of
+ * DYNAMIC_CONFIG)
+ */
+#define NVRAM_PARTITION_TYPE_USER_CONFIG 0x500
/* enum: Expansion ROM configuration data for port 0 */
#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
@@ -8227,10 +9310,16 @@
#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
/* enum: Non-volatile log output partition */
#define NVRAM_PARTITION_TYPE_LOG 0x700
+/* enum: Non-volatile log output partition for NMC firmware (this is
+ * intentionally an alias of LOG)
+ */
+#define NVRAM_PARTITION_TYPE_NMC_LOG 0x700
/* enum: Non-volatile log output of second core on dual-core device */
#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
/* enum: Device state dump output partition */
#define NVRAM_PARTITION_TYPE_DUMP 0x800
+/* enum: Crash log partition for NMC firmware */
+#define NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801
/* enum: Application license key storage partition */
#define NVRAM_PARTITION_TYPE_LICENSE 0x900
/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
@@ -8247,6 +9336,20 @@
#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
/* enum: Non-volatile log output partition for FC */
#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
+/* enum: FPGA Stage 1 bitstream */
+#define NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05
+/* enum: FPGA Stage 2 bitstream */
+#define NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06
+/* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */
+#define NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07
+/* enum: FPGA User XCLBIN (this is intentionally an alias of FPGA_REGION0) */
+#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07
+/* enum: FPGA jump instruction (a.k.a. boot) partition to select Stage1
+ * bitstream
+ */
+#define NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08
+/* enum: FPGA Validate XCLBIN */
+#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09
/* enum: MUM firmware partition */
#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
/* enum: SUC firmware partition (this is intentionally an alias of
@@ -8255,6 +9358,10 @@
#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
/* enum: MUM Non-volatile log output partition. */
#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
+/* enum: SUC Non-volatile log output partition (this is intentionally an alias
+ * of MUM_LOG).
+ */
+#define NVRAM_PARTITION_TYPE_SUC_LOG 0xc01
/* enum: MUM Application table partition. */
#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
/* enum: MUM boot rom partition. */
@@ -8269,6 +9376,10 @@
#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
/* enum: Used by the expansion ROM for logging */
#define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
+/* enum: Non-volatile log output partition for Expansion ROM (this is
+ * intentionally an alias of PXE_LOG).
+ */
+#define NVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000
/* enum: Used for XIP code of shmbooted images */
#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
/* enum: Spare partition 2 */
@@ -8277,6 +9388,10 @@
* between XJTAG and Manftest.
*/
#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
+/* enum: Deployment configuration TLV partition (this is intentionally an alias
+ * of MANUFACTURING)
+ */
+#define NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300
/* enum: Spare partition 4 */
#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
/* enum: Spare partition 5 */
@@ -8312,14 +9427,43 @@
#define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */
#define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
+/* enum: Test partition on SmartNIC system microcontroller (SUC) */
+#define NVRAM_PARTITION_TYPE_SUC_TEST 0x1f00
+/* enum: System microcontroller access to primary FPGA flash. */
+#define NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01
+/* enum: System microcontroller access to secondary FPGA flash (if present) */
+#define NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02
+/* enum: System microcontroller access to primary System-on-Chip flash */
+#define NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03
+/* enum: System microcontroller access to secondary System-on-Chip flash (if
+ * present)
+ */
+#define NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04
+/* enum: System microcontroller critical failure logs. Contains structured
+ * details of sensors leading up to a critical failure (where the board is shut
+ * down).
+ */
+#define NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05
+/* enum: System-on-Chip configuration information (see XN-200467-PS). */
+#define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07
+/* enum: System-on-Chip update information. */
+#define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003
/* enum: Start of reserved value range (firmware may use for any purpose) */
#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
/* enum: End of reserved value range (firmware may use for any purpose) */
#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
/* enum: Recovery partition map (provided if real map is missing or corrupt) */
#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
+/* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is
+ * intentionally an alias of RECOVERY_MAP)
+ */
+#define NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe
/* enum: Partition map (real map as stored in flash) */
#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
+/* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an
+ * alias of PARTITION_MAP)
+ */
+#define NVRAM_PARTITION_TYPE_FPT 0xffff
#define NVRAM_PARTITION_TYPE_ID_LBN 0
#define NVRAM_PARTITION_TYPE_ID_WIDTH 16
@@ -8368,7 +9512,13 @@
#define LICENSED_FEATURES_MASK_OFST 0
#define LICENSED_FEATURES_MASK_LEN 8
#define LICENSED_FEATURES_MASK_LO_OFST 0
+#define LICENSED_FEATURES_MASK_LO_LEN 4
+#define LICENSED_FEATURES_MASK_LO_LBN 0
+#define LICENSED_FEATURES_MASK_LO_WIDTH 32
#define LICENSED_FEATURES_MASK_HI_OFST 4
+#define LICENSED_FEATURES_MASK_HI_LEN 4
+#define LICENSED_FEATURES_MASK_HI_LBN 32
+#define LICENSED_FEATURES_MASK_HI_WIDTH 32
#define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
@@ -8408,7 +9558,13 @@
#define LICENSED_V3_APPS_MASK_OFST 0
#define LICENSED_V3_APPS_MASK_LEN 8
#define LICENSED_V3_APPS_MASK_LO_OFST 0
+#define LICENSED_V3_APPS_MASK_LO_LEN 4
+#define LICENSED_V3_APPS_MASK_LO_LBN 0
+#define LICENSED_V3_APPS_MASK_LO_WIDTH 32
#define LICENSED_V3_APPS_MASK_HI_OFST 4
+#define LICENSED_V3_APPS_MASK_HI_LEN 4
+#define LICENSED_V3_APPS_MASK_HI_LBN 32
+#define LICENSED_V3_APPS_MASK_HI_WIDTH 32
#define LICENSED_V3_APPS_ONLOAD_OFST 0
#define LICENSED_V3_APPS_ONLOAD_LBN 0
#define LICENSED_V3_APPS_ONLOAD_WIDTH 1
@@ -8466,7 +9622,13 @@
#define LICENSED_V3_FEATURES_MASK_OFST 0
#define LICENSED_V3_FEATURES_MASK_LEN 8
#define LICENSED_V3_FEATURES_MASK_LO_OFST 0
+#define LICENSED_V3_FEATURES_MASK_LO_LEN 4
+#define LICENSED_V3_FEATURES_MASK_LO_LBN 0
+#define LICENSED_V3_FEATURES_MASK_LO_WIDTH 32
#define LICENSED_V3_FEATURES_MASK_HI_OFST 4
+#define LICENSED_V3_FEATURES_MASK_HI_LEN 4
+#define LICENSED_V3_FEATURES_MASK_HI_LBN 32
+#define LICENSED_V3_FEATURES_MASK_HI_WIDTH 32
#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
@@ -8617,6 +9779,7 @@
* Get a dump of the MCPU registers
*/
#define MC_CMD_READ_REGS 0x50
+#define MC_CMD_READ_REGS_MSGSET 0x50
#undef MC_CMD_0x50_PRIVILEGE_CTG
#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -8643,6 +9806,7 @@
* end with an address for each 4k of host memory required to back the EVQ.
*/
#define MC_CMD_INIT_EVQ 0x80
+#define MC_CMD_INIT_EVQ_MSGSET 0x80
#undef MC_CMD_0x80_PRIVILEGE_CTG
#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8657,7 +9821,8 @@
#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
#define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
@@ -8729,7 +9894,13 @@
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LBN 288
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LBN 320
+#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 64
@@ -8750,7 +9921,8 @@
#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
@@ -8847,7 +10019,13 @@
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LBN 288
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LBN 320
+#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 64
@@ -8900,6 +10078,7 @@
* the RXQ.
*/
#define MC_CMD_INIT_RXQ 0x81
+#define MC_CMD_INIT_RXQ_MSGSET 0x81
#undef MC_CMD_0x81_PRIVILEGE_CTG
#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -8923,7 +10102,8 @@
#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
@@ -8964,7 +10144,13 @@
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
@@ -8988,7 +10174,8 @@
#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
@@ -9062,7 +10249,13 @@
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9085,7 +10278,8 @@
#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
@@ -9159,7 +10353,13 @@
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9211,7 +10411,8 @@
#define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
@@ -9285,7 +10486,13 @@
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9350,7 +10557,8 @@
#define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8
#define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
@@ -9424,7 +10632,13 @@
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 64
/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540
@@ -9497,6 +10711,7 @@
/* MC_CMD_INIT_TXQ
*/
#define MC_CMD_INIT_TXQ 0x82
+#define MC_CMD_INIT_TXQ_MSGSET 0x82
#undef MC_CMD_0x82_PRIVILEGE_CTG
#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9521,7 +10736,8 @@
#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
#define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
@@ -9565,7 +10781,13 @@
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
@@ -9586,7 +10808,8 @@
#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
@@ -9648,7 +10871,13 @@
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 4
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LBN 224
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 4
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LBN 256
+#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64
@@ -9674,6 +10903,7 @@
* or the operation will fail with EBUSY
*/
#define MC_CMD_FINI_EVQ 0x83
+#define MC_CMD_FINI_EVQ_MSGSET 0x83
#undef MC_CMD_0x83_PRIVILEGE_CTG
#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9695,6 +10925,7 @@
* Teardown a RXQ.
*/
#define MC_CMD_FINI_RXQ 0x84
+#define MC_CMD_FINI_RXQ_MSGSET 0x84
#undef MC_CMD_0x84_PRIVILEGE_CTG
#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9714,6 +10945,7 @@
* Teardown a TXQ.
*/
#define MC_CMD_FINI_TXQ 0x85
+#define MC_CMD_FINI_TXQ_MSGSET 0x85
#undef MC_CMD_0x85_PRIVILEGE_CTG
#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9733,6 +10965,7 @@
* Generate an event on an EVQ belonging to the function issuing the command.
*/
#define MC_CMD_DRIVER_EVENT 0x86
+#define MC_CMD_DRIVER_EVENT_MSGSET 0x86
#undef MC_CMD_0x86_PRIVILEGE_CTG
#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -9746,7 +10979,13 @@
#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
+#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 4
+#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LBN 32
+#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_WIDTH 32
#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
+#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 4
+#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LBN 64
+#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_WIDTH 32
/* MC_CMD_DRIVER_EVENT_OUT msgresponse */
#define MC_CMD_DRIVER_EVENT_OUT_LEN 0
@@ -9760,6 +10999,7 @@
* MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
*/
#define MC_CMD_PROXY_CMD 0x5b
+#define MC_CMD_PROXY_CMD_MSGSET 0x5b
#undef MC_CMD_0x5b_PRIVILEGE_CTG
#define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -9828,6 +11068,7 @@
* a designated admin function
*/
#define MC_CMD_PROXY_CONFIGURE 0x58
+#define MC_CMD_PROXY_CONFIGURE_MSGSET 0x58
#undef MC_CMD_0x58_PRIVILEGE_CTG
#define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -9845,7 +11086,13 @@
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LBN 32
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LBN 64
+#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12
#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
@@ -9855,7 +11102,13 @@
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LBN 128
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LBN 160
+#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24
#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
@@ -9866,7 +11119,13 @@
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LBN 224
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LBN 256
+#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2, or zero if this buffer is not provided */
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36
#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
@@ -9890,7 +11149,13 @@
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LBN 32
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LBN 64
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
@@ -9900,7 +11165,13 @@
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LBN 128
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LBN 160
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2 */
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
@@ -9911,7 +11182,13 @@
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LBN 224
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_WIDTH 32
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LEN 4
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LBN 256
+#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_WIDTH 32
/* Must be a power of 2, or zero if this buffer is not provided */
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36
#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
@@ -9936,6 +11213,7 @@
* MC_CMD_PROXY_CONFIGURE).
*/
#define MC_CMD_PROXY_COMPLETE 0x5f
+#define MC_CMD_PROXY_COMPLETE_MSGSET 0x5f
#undef MC_CMD_0x5f_PRIVILEGE_CTG
#define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -9974,6 +11252,7 @@
* cannot do so). The buffer table entries will initially be zeroed.
*/
#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
+#define MC_CMD_ALLOC_BUFTBL_CHUNK_MSGSET 0x87
#undef MC_CMD_0x87_PRIVILEGE_CTG
#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -10005,6 +11284,7 @@
* Reprogram a set of buffer table entries in the specified chunk.
*/
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_MSGSET 0x88
#undef MC_CMD_0x88_PRIVILEGE_CTG
#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -10027,7 +11307,13 @@
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LEN 4
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LBN 96
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_WIDTH 32
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LEN 4
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LBN 128
+#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_WIDTH 32
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 32
@@ -10040,6 +11326,7 @@
/* MC_CMD_FREE_BUFTBL_CHUNK
*/
#define MC_CMD_FREE_BUFTBL_CHUNK 0x89
+#define MC_CMD_FREE_BUFTBL_CHUNK_MSGSET 0x89
#undef MC_CMD_0x89_PRIVILEGE_CTG
#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -10058,6 +11345,7 @@
* Multiplexed MCDI call for filter operations
*/
#define MC_CMD_FILTER_OP 0x8a
+#define MC_CMD_FILTER_OP_MSGSET 0x8a
#undef MC_CMD_0x8a_PRIVILEGE_CTG
#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -10083,7 +11371,13 @@
#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_IN_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_IN_HANDLE_HI_WIDTH 32
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
@@ -10239,7 +11533,13 @@
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_WIDTH 32
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
@@ -10518,7 +11818,13 @@
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_WIDTH 32
/* The port ID associated with the v-adaptor which should contain this filter.
*/
#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12
@@ -10779,15 +12085,15 @@
*/
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156
#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16
-/* Flags controlling mutations of the user_mark and user_flag fields of
- * matching packets, with logic as follows: if (req.MATCH_BITOR_FLAG == 1)
- * user_flag = req.MATCH_SET_FLAG bit_or user_flag; else user_flag =
- * req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark = 0; else if
- * (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK bit_or user_mark;
- * else user_mark = req.MATCH_SET_MARK; N.B. These flags overlap with the
- * MATCH_ACTION field, which is deprecated in favour of this field. For the
- * cases where these flags induce a valid encoding of the MATCH_ACTION field,
- * the semantics agree.
+/* Flags controlling mutations of the packet and/or metadata when the filter is
+ * matched. The user_mark and user_flag fields' logic is as follows: if
+ * (req.MATCH_BITOR_FLAG == 1) user_flag = req.MATCH_SET_FLAG bit_or user_flag;
+ * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark
+ * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK
+ * bit_or user_mark; else user_mark = req.MATCH_SET_MARK; N.B. These flags
+ * overlap with the MATCH_ACTION field, which is deprecated in favour of this
+ * field. For the cases where these flags induce a valid encoding of the
+ * MATCH_ACTION field, the semantics agree.
*/
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_OFST 172
#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4
@@ -10803,6 +12109,9 @@
#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_OFST 172
#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_LBN 3
#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_WIDTH 1
+#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_OFST 172
+#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 4
+#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_WIDTH 1
/* Deprecated: the overlapping MATCH_ACTION_FLAGS field exposes all of the
* functionality of this field in an ABI-backwards-compatible manner, and
* should be used instead. Any future extensions should be made to the
@@ -10848,7 +12157,13 @@
#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_WIDTH 32
/* enum: guaranteed invalid filter handle (low 32 bits) */
#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
/* enum: guaranteed invalid filter handle (high 32 bits) */
@@ -10868,7 +12183,13 @@
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 4
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LBN 32
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_WIDTH 32
#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 4
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LBN 64
+#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_WIDTH 32
/* Enum values, see field(s): */
/* MC_CMD_FILTER_OP_OUT/HANDLE */
@@ -10878,6 +12199,7 @@
* Get information related to the parser-dispatcher subsystem
*/
#define MC_CMD_GET_PARSER_DISP_INFO 0xe4
+#define MC_CMD_GET_PARSER_DISP_INFO_MSGSET 0xe4
#undef MC_CMD_0xe4_PRIVILEGE_CTG
#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11025,6 +12347,7 @@
* permitted.
*/
#define MC_CMD_PARSER_DISP_RW 0xe5
+#define MC_CMD_PARSER_DISP_RW_MSGSET 0xe5
#undef MC_CMD_0xe5_PRIVILEGE_CTG
#define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11115,6 +12438,7 @@
* Get number of PFs on the device.
*/
#define MC_CMD_GET_PF_COUNT 0xb6
+#define MC_CMD_GET_PF_COUNT_MSGSET 0xb6
#undef MC_CMD_0xb6_PRIVILEGE_CTG
#define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11134,6 +12458,7 @@
* Set number of PFs on the device.
*/
#define MC_CMD_SET_PF_COUNT 0xb7
+#define MC_CMD_SET_PF_COUNT_MSGSET 0xb7
/* MC_CMD_SET_PF_COUNT_IN msgrequest */
#define MC_CMD_SET_PF_COUNT_IN_LEN 4
@@ -11150,6 +12475,7 @@
* Get port assignment for current PCI function.
*/
#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
+#define MC_CMD_GET_PORT_ASSIGNMENT_MSGSET 0xb8
#undef MC_CMD_0xb8_PRIVILEGE_CTG
#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11175,6 +12501,7 @@
* Set port assignment for current PCI function.
*/
#define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
+#define MC_CMD_SET_PORT_ASSIGNMENT_MSGSET 0xb9
#undef MC_CMD_0xb9_PRIVILEGE_CTG
#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11194,6 +12521,7 @@
* Allocate VIs for current PCI function.
*/
#define MC_CMD_ALLOC_VIS 0x8b
+#define MC_CMD_ALLOC_VIS_MSGSET 0x8b
#undef MC_CMD_0x8b_PRIVILEGE_CTG
#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11241,6 +12569,7 @@
* but not freed.
*/
#define MC_CMD_FREE_VIS 0x8c
+#define MC_CMD_FREE_VIS_MSGSET 0x8c
#undef MC_CMD_0x8c_PRIVILEGE_CTG
#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11257,6 +12586,7 @@
* Get SRIOV config for this PF.
*/
#define MC_CMD_GET_SRIOV_CFG 0xba
+#define MC_CMD_GET_SRIOV_CFG_MSGSET 0xba
#undef MC_CMD_0xba_PRIVILEGE_CTG
#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11290,6 +12620,7 @@
* Set SRIOV config for this PF.
*/
#define MC_CMD_SET_SRIOV_CFG 0xbb
+#define MC_CMD_SET_SRIOV_CFG_MSGSET 0xbb
#undef MC_CMD_0xbb_PRIVILEGE_CTG
#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11325,9 +12656,11 @@
/***********************************/
/* MC_CMD_GET_VI_ALLOC_INFO
* Get information about number of VI's and base VI number allocated to this
- * function.
+ * function. This message is not available to dynamic clients created by
+ * MC_CMD_CLIENT_ALLOC.
*/
#define MC_CMD_GET_VI_ALLOC_INFO 0x8d
+#define MC_CMD_GET_VI_ALLOC_INFO_MSGSET 0x8d
#undef MC_CMD_0x8d_PRIVILEGE_CTG
#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11352,9 +12685,12 @@
/***********************************/
/* MC_CMD_DUMP_VI_STATE
- * For CmdClient use. Dump pertinent information on a specific absolute VI.
+ * For CmdClient use. Dump pertinent information on a specific absolute VI. The
+ * VI must be owned by the calling client or one of its ancestors; usership of
+ * the VI (as set by MC_CMD_SET_VI_USER) is not sufficient.
*/
#define MC_CMD_DUMP_VI_STATE 0x8e
+#define MC_CMD_DUMP_VI_STATE_MSGSET 0x8e
#undef MC_CMD_0x8e_PRIVILEGE_CTG
#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11366,7 +12702,7 @@
#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
-#define MC_CMD_DUMP_VI_STATE_OUT_LEN 96
+#define MC_CMD_DUMP_VI_STATE_OUT_LEN 100
/* The PF part of the function owning this VI. */
#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
@@ -11389,12 +12725,24 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LBN 96
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LBN 128
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_WIDTH 32
/* Raw evq timer table data. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LBN 160
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LBN 192
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_WIDTH 32
/* Combined metadata field. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
@@ -11411,22 +12759,46 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LBN 256
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LBN 288
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_WIDTH 32
/* TXDPCPU raw table data for queue. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LBN 320
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LBN 352
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_WIDTH 32
/* TXDPCPU raw table data for queue. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LBN 384
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LBN 416
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_WIDTH 32
/* Combined metadata field. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LBN 448
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LBN 480
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
@@ -11446,22 +12818,46 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LBN 512
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LBN 544
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_WIDTH 32
/* RXDPCPU raw table data for queue. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LBN 576
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LBN 608
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_WIDTH 32
/* Reserved, currently 0. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LBN 640
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LBN 672
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_WIDTH 32
/* Combined metadata field. */
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LBN 704
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LEN 4
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LBN 736
+#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_WIDTH 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
@@ -11474,6 +12870,9 @@
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
+/* Current user, as assigned by MC_CMD_SET_VI_USER. */
+#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_OFST 96
+#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_LEN 4
/***********************************/
@@ -11481,6 +12880,7 @@
* Allocate a push I/O buffer for later use with a tx queue.
*/
#define MC_CMD_ALLOC_PIOBUF 0x8f
+#define MC_CMD_ALLOC_PIOBUF_MSGSET 0x8f
#undef MC_CMD_0x8f_PRIVILEGE_CTG
#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -11500,6 +12900,7 @@
* Free a push I/O buffer.
*/
#define MC_CMD_FREE_PIOBUF 0x90
+#define MC_CMD_FREE_PIOBUF_MSGSET 0x90
#undef MC_CMD_0x90_PRIVILEGE_CTG
#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -11516,9 +12917,12 @@
/***********************************/
/* MC_CMD_GET_VI_TLP_PROCESSING
- * Get TLP steering and ordering information for a VI.
+ * Get TLP steering and ordering information for a VI. The caller must have the
+ * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
+ * an ancestor of the current user (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
+#define MC_CMD_GET_VI_TLP_PROCESSING_MSGSET 0xb0
#undef MC_CMD_0xb0_PRIVILEGE_CTG
#define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11555,9 +12959,12 @@
/***********************************/
/* MC_CMD_SET_VI_TLP_PROCESSING
- * Set TLP steering and ordering information for a VI.
+ * Set TLP steering and ordering information for a VI. The caller must have the
+ * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
+ * an ancestor of the current user (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
+#define MC_CMD_SET_VI_TLP_PROCESSING_MSGSET 0xb1
#undef MC_CMD_0xb1_PRIVILEGE_CTG
#define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -11597,6 +13004,7 @@
* Get global PCIe steering and transaction processing configuration.
*/
#define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
+#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_MSGSET 0xbc
#undef MC_CMD_0xbc_PRIVILEGE_CTG
#define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11681,6 +13089,7 @@
* Set global PCIe steering and transaction processing configuration.
*/
#define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
+#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_MSGSET 0xbd
#undef MC_CMD_0xbd_PRIVILEGE_CTG
#define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -11746,6 +13155,7 @@
* Download a new set of images to the satellite CPUs from the host.
*/
#define MC_CMD_SATELLITE_DOWNLOAD 0x91
+#define MC_CMD_SATELLITE_DOWNLOAD_MSGSET 0x91
#undef MC_CMD_0x91_PRIVILEGE_CTG
#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -11873,6 +13283,7 @@
* reference inherent device capabilities as opposed to current NVRAM config.
*/
#define MC_CMD_GET_CAPABILITIES 0xbe
+#define MC_CMD_GET_CAPABILITIES_MSGSET 0xbe
#undef MC_CMD_0xbe_PRIVILEGE_CTG
#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -14813,6 +16224,18 @@
#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */
#define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160
@@ -15299,6 +16722,18 @@
#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
@@ -15306,7 +16741,13 @@
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LBN 1216
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_WIDTH 32
#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LBN 1248
+#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_WIDTH 32
/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */
#define MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184
@@ -15793,6 +17234,18 @@
#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
@@ -15800,7 +17253,13 @@
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LBN 1216
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_WIDTH 32
#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LBN 1248
+#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_WIDTH 32
/* The minimum size (in table entries) of indirection table to be allocated
* from the pool for an RSS context. Note that the table size used must be a
* power of 2.
@@ -16322,6 +17781,18 @@
#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
@@ -16329,7 +17800,13 @@
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_OFST 152
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LEN 8
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_OFST 152
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LBN 1216
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_WIDTH 32
#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_OFST 156
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 4
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LBN 1248
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_WIDTH 32
/* The minimum size (in table entries) of indirection table to be allocated
* from the pool for an RSS context. Note that the table size used must be a
* power of 2.
@@ -16386,6 +17863,7 @@
* Encapsulation for a v2 extended command
*/
#define MC_CMD_V2_EXTN 0x7f
+#define MC_CMD_V2_EXTN_MSGSET 0x7f
/* MC_CMD_V2_EXTN_IN msgrequest */
#define MC_CMD_V2_EXTN_IN_LEN 4
@@ -16417,6 +17895,7 @@
* Allocate a pacer bucket (for qau rp or a snapper test)
*/
#define MC_CMD_TCM_BUCKET_ALLOC 0xb2
+#define MC_CMD_TCM_BUCKET_ALLOC_MSGSET 0xb2
#undef MC_CMD_0xb2_PRIVILEGE_CTG
#define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16436,6 +17915,7 @@
* Free a pacer bucket
*/
#define MC_CMD_TCM_BUCKET_FREE 0xb3
+#define MC_CMD_TCM_BUCKET_FREE_MSGSET 0xb3
#undef MC_CMD_0xb3_PRIVILEGE_CTG
#define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16455,6 +17935,7 @@
* Initialise pacer bucket with a given rate
*/
#define MC_CMD_TCM_BUCKET_INIT 0xb4
+#define MC_CMD_TCM_BUCKET_INIT_MSGSET 0xb4
#undef MC_CMD_0xb4_PRIVILEGE_CTG
#define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16489,6 +17970,7 @@
* Initialise txq in pacer with given options or set options
*/
#define MC_CMD_TCM_TXQ_INIT 0xb5
+#define MC_CMD_TCM_TXQ_INIT_MSGSET 0xb5
#undef MC_CMD_0xb5_PRIVILEGE_CTG
#define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16579,6 +18061,7 @@
* Link a push I/O buffer to a TxQ
*/
#define MC_CMD_LINK_PIOBUF 0x92
+#define MC_CMD_LINK_PIOBUF_MSGSET 0x92
#undef MC_CMD_0x92_PRIVILEGE_CTG
#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -16588,7 +18071,7 @@
/* Handle for allocated push I/O buffer. */
#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
-/* Function Local Instance (VI) number. */
+/* Function Local Instance (VI) number which has a TxQ allocated to it. */
#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
@@ -16601,6 +18084,7 @@
* Unlink a push I/O buffer from a TxQ
*/
#define MC_CMD_UNLINK_PIOBUF 0x93
+#define MC_CMD_UNLINK_PIOBUF_MSGSET 0x93
#undef MC_CMD_0x93_PRIVILEGE_CTG
#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -16620,6 +18104,7 @@
* allocate and initialise a v-switch.
*/
#define MC_CMD_VSWITCH_ALLOC 0x94
+#define MC_CMD_VSWITCH_ALLOC_MSGSET 0x94
#undef MC_CMD_0x94_PRIVILEGE_CTG
#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16667,6 +18152,7 @@
* de-allocate a v-switch.
*/
#define MC_CMD_VSWITCH_FREE 0x95
+#define MC_CMD_VSWITCH_FREE_MSGSET 0x95
#undef MC_CMD_0x95_PRIVILEGE_CTG
#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16688,6 +18174,7 @@
* not, then the command returns ENOENT).
*/
#define MC_CMD_VSWITCH_QUERY 0x63
+#define MC_CMD_VSWITCH_QUERY_MSGSET 0x63
#undef MC_CMD_0x63_PRIVILEGE_CTG
#define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16707,6 +18194,7 @@
* allocate a v-port.
*/
#define MC_CMD_VPORT_ALLOC 0x96
+#define MC_CMD_VPORT_ALLOC_MSGSET 0x96
#undef MC_CMD_0x96_PRIVILEGE_CTG
#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16774,6 +18262,7 @@
* de-allocate a v-port.
*/
#define MC_CMD_VPORT_FREE 0x97
+#define MC_CMD_VPORT_FREE_MSGSET 0x97
#undef MC_CMD_0x97_PRIVILEGE_CTG
#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16793,6 +18282,7 @@
* allocate a v-adaptor.
*/
#define MC_CMD_VADAPTOR_ALLOC 0x98
+#define MC_CMD_VADAPTOR_ALLOC_MSGSET 0x98
#undef MC_CMD_0x98_PRIVILEGE_CTG
#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16841,6 +18331,7 @@
* de-allocate a v-adaptor.
*/
#define MC_CMD_VADAPTOR_FREE 0x99
+#define MC_CMD_VADAPTOR_FREE_MSGSET 0x99
#undef MC_CMD_0x99_PRIVILEGE_CTG
#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16860,6 +18351,7 @@
* assign a new MAC address to a v-adaptor.
*/
#define MC_CMD_VADAPTOR_SET_MAC 0x5d
+#define MC_CMD_VADAPTOR_SET_MAC_MSGSET 0x5d
#undef MC_CMD_0x5d_PRIVILEGE_CTG
#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16882,6 +18374,7 @@
* read the MAC address assigned to a v-adaptor.
*/
#define MC_CMD_VADAPTOR_GET_MAC 0x5e
+#define MC_CMD_VADAPTOR_GET_MAC_MSGSET 0x5e
#undef MC_CMD_0x5e_PRIVILEGE_CTG
#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16904,6 +18397,7 @@
* read some config of v-adaptor.
*/
#define MC_CMD_VADAPTOR_QUERY 0x61
+#define MC_CMD_VADAPTOR_QUERY_MSGSET 0x61
#undef MC_CMD_0x61_PRIVILEGE_CTG
#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16932,6 +18426,7 @@
* assign a port to a PCI function.
*/
#define MC_CMD_EVB_PORT_ASSIGN 0x9a
+#define MC_CMD_EVB_PORT_ASSIGN_MSGSET 0x9a
#undef MC_CMD_0x9a_PRIVILEGE_CTG
#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -16960,6 +18455,7 @@
* Assign the 64 bit region addresses.
*/
#define MC_CMD_RDWR_A64_REGIONS 0x9b
+#define MC_CMD_RDWR_A64_REGIONS_MSGSET 0x9b
#undef MC_CMD_0x9b_PRIVILEGE_CTG
#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -16999,6 +18495,7 @@
* Allocate an Onload stack ID.
*/
#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
+#define MC_CMD_ONLOAD_STACK_ALLOC_MSGSET 0x9c
#undef MC_CMD_0x9c_PRIVILEGE_CTG
#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -17021,6 +18518,7 @@
* Free an Onload stack ID.
*/
#define MC_CMD_ONLOAD_STACK_FREE 0x9d
+#define MC_CMD_ONLOAD_STACK_FREE_MSGSET 0x9d
#undef MC_CMD_0x9d_PRIVILEGE_CTG
#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
@@ -17040,6 +18538,7 @@
* Allocate an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
+#define MC_CMD_RSS_CONTEXT_ALLOC_MSGSET 0x9e
#undef MC_CMD_0x9e_PRIVILEGE_CTG
#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17140,6 +18639,7 @@
* Free an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_FREE 0x9f
+#define MC_CMD_RSS_CONTEXT_FREE_MSGSET 0x9f
#undef MC_CMD_0x9f_PRIVILEGE_CTG
#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17159,6 +18659,7 @@
* Set the Toeplitz hash key for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
+#define MC_CMD_RSS_CONTEXT_SET_KEY_MSGSET 0xa0
#undef MC_CMD_0xa0_PRIVILEGE_CTG
#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17181,6 +18682,7 @@
* Get the Toeplitz hash key for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
+#define MC_CMD_RSS_CONTEXT_GET_KEY_MSGSET 0xa1
#undef MC_CMD_0xa1_PRIVILEGE_CTG
#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17205,6 +18707,7 @@
* when the RSS context is allocated without specifying a table size.
*/
#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
+#define MC_CMD_RSS_CONTEXT_SET_TABLE_MSGSET 0xa2
#undef MC_CMD_0xa2_PRIVILEGE_CTG
#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17229,6 +18732,7 @@
* when the RSS context is allocated without specifying a table size.
*/
#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
+#define MC_CMD_RSS_CONTEXT_GET_TABLE_MSGSET 0xa3
#undef MC_CMD_0xa3_PRIVILEGE_CTG
#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17253,6 +18757,7 @@
* RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
*/
#define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e
+#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_MSGSET 0x13e
#undef MC_CMD_0x13e_PRIVILEGE_CTG
#define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17299,6 +18804,7 @@
* RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
*/
#define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f
+#define MC_CMD_RSS_CONTEXT_READ_TABLE_MSGSET 0x13f
#undef MC_CMD_0x13f_PRIVILEGE_CTG
#define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17338,6 +18844,7 @@
* Set various control flags for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
+#define MC_CMD_RSS_CONTEXT_SET_FLAGS_MSGSET 0xe1
#undef MC_CMD_0xe1_PRIVILEGE_CTG
#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17404,6 +18911,7 @@
* Get various control flags for an RSS context.
*/
#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
+#define MC_CMD_RSS_CONTEXT_GET_FLAGS_MSGSET 0xe2
#undef MC_CMD_0xe2_PRIVILEGE_CTG
#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17471,6 +18979,7 @@
* Allocate a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
+#define MC_CMD_DOT1P_MAPPING_ALLOC_MSGSET 0xa4
#undef MC_CMD_0xa4_PRIVILEGE_CTG
#define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17504,6 +19013,7 @@
* Free a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_FREE 0xa5
+#define MC_CMD_DOT1P_MAPPING_FREE_MSGSET 0xa5
#undef MC_CMD_0xa5_PRIVILEGE_CTG
#define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17523,6 +19033,7 @@
* Set the mapping table for a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
+#define MC_CMD_DOT1P_MAPPING_SET_TABLE_MSGSET 0xa6
#undef MC_CMD_0xa6_PRIVILEGE_CTG
#define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17547,6 +19058,7 @@
* Get the mapping table for a .1p mapping.
*/
#define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
+#define MC_CMD_DOT1P_MAPPING_GET_TABLE_MSGSET 0xa7
#undef MC_CMD_0xa7_PRIVILEGE_CTG
#define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17571,6 +19083,7 @@
* Get Interrupt Vector config for this PF.
*/
#define MC_CMD_GET_VECTOR_CFG 0xbf
+#define MC_CMD_GET_VECTOR_CFG_MSGSET 0xbf
#undef MC_CMD_0xbf_PRIVILEGE_CTG
#define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17596,6 +19109,7 @@
* Set Interrupt Vector config for this PF.
*/
#define MC_CMD_SET_VECTOR_CFG 0xc0
+#define MC_CMD_SET_VECTOR_CFG_MSGSET 0xc0
#undef MC_CMD_0xc0_PRIVILEGE_CTG
#define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17623,6 +19137,7 @@
* Add a MAC address to a v-port
*/
#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
+#define MC_CMD_VPORT_ADD_MAC_ADDRESS_MSGSET 0xa8
#undef MC_CMD_0xa8_PRIVILEGE_CTG
#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17645,6 +19160,7 @@
* Delete a MAC address from a v-port
*/
#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
+#define MC_CMD_VPORT_DEL_MAC_ADDRESS_MSGSET 0xa9
#undef MC_CMD_0xa9_PRIVILEGE_CTG
#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17667,6 +19183,7 @@
* Delete a MAC address from a v-port
*/
#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
+#define MC_CMD_VPORT_GET_MAC_ADDRESSES_MSGSET 0xaa
#undef MC_CMD_0xaa_PRIVILEGE_CTG
#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17701,6 +19218,7 @@
* function will be reset before applying the changes.
*/
#define MC_CMD_VPORT_RECONFIGURE 0xeb
+#define MC_CMD_VPORT_RECONFIGURE_MSGSET 0xeb
#undef MC_CMD_0xeb_PRIVILEGE_CTG
#define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17756,6 +19274,7 @@
* read some config of v-port.
*/
#define MC_CMD_EVB_PORT_QUERY 0x62
+#define MC_CMD_EVB_PORT_QUERY_MSGSET 0x62
#undef MC_CMD_0x62_PRIVILEGE_CTG
#define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17786,6 +19305,7 @@
* lifted in future.
*/
#define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
+#define MC_CMD_DUMP_BUFTBL_ENTRIES_MSGSET 0xab
#undef MC_CMD_0xab_PRIVILEGE_CTG
#define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -17818,6 +19338,7 @@
* Set global RXDP configuration settings
*/
#define MC_CMD_SET_RXDP_CONFIG 0xc1
+#define MC_CMD_SET_RXDP_CONFIG_MSGSET 0xc1
#undef MC_CMD_0xc1_PRIVILEGE_CTG
#define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -17848,6 +19369,7 @@
* Get global RXDP configuration settings
*/
#define MC_CMD_GET_RXDP_CONFIG 0xc2
+#define MC_CMD_GET_RXDP_CONFIG_MSGSET 0xc2
#undef MC_CMD_0xc2_PRIVILEGE_CTG
#define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17874,6 +19396,7 @@
* Return the system and PDCPU clock frequencies.
*/
#define MC_CMD_GET_CLOCK 0xac
+#define MC_CMD_GET_CLOCK_MSGSET 0xac
#undef MC_CMD_0xac_PRIVILEGE_CTG
#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -17896,6 +19419,7 @@
* Control the system and DPCPU clock frequencies. Changes are lost reboot.
*/
#define MC_CMD_SET_CLOCK 0xad
+#define MC_CMD_SET_CLOCK_MSGSET 0xad
#undef MC_CMD_0xad_PRIVILEGE_CTG
#define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -17982,6 +19506,7 @@
* Send an arbitrary DPCPU message.
*/
#define MC_CMD_DPCPU_RPC 0xae
+#define MC_CMD_DPCPU_RPC_MSGSET 0xae
#undef MC_CMD_0xae_PRIVILEGE_CTG
#define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18100,6 +19625,7 @@
* Trigger an interrupt by prodding the BIU.
*/
#define MC_CMD_TRIGGER_INTERRUPT 0xe3
+#define MC_CMD_TRIGGER_INTERRUPT_MSGSET 0xe3
#undef MC_CMD_0xe3_PRIVILEGE_CTG
#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18119,6 +19645,7 @@
* Special operations to support (for now) shmboot.
*/
#define MC_CMD_SHMBOOT_OP 0xe6
+#define MC_CMD_SHMBOOT_OP_MSGSET 0xe6
#undef MC_CMD_0xe6_PRIVILEGE_CTG
#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -18140,6 +19667,7 @@
* Read multiple 64bit words from capture block memory
*/
#define MC_CMD_CAP_BLK_READ 0xe7
+#define MC_CMD_CAP_BLK_READ_MSGSET 0xe7
#undef MC_CMD_0xe7_PRIVILEGE_CTG
#define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18162,7 +19690,13 @@
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LEN 4
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LBN 0
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_WIDTH 32
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LEN 4
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LBN 32
+#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_WIDTH 32
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31
#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM_MCDI2 127
@@ -18173,6 +19707,7 @@
* Take a dump of the DUT state
*/
#define MC_CMD_DUMP_DO 0xe8
+#define MC_CMD_DUMP_DO_MSGSET 0xe8
#undef MC_CMD_0xe8_PRIVILEGE_CTG
#define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18253,6 +19788,7 @@
* Configure unsolicited dumps
*/
#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
+#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_MSGSET 0xe9
#undef MC_CMD_0xe9_PRIVILEGE_CTG
#define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18322,6 +19858,7 @@
* the parameter is out of range.
*/
#define MC_CMD_SET_PSU 0xea
+#define MC_CMD_SET_PSU_MSGSET 0xea
#undef MC_CMD_0xea_PRIVILEGE_CTG
#define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18348,6 +19885,7 @@
* Get function information. PF and VF number.
*/
#define MC_CMD_GET_FUNCTION_INFO 0xec
+#define MC_CMD_GET_FUNCTION_INFO_MSGSET 0xec
#undef MC_CMD_0xec_PRIVILEGE_CTG
#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18370,6 +19908,7 @@
* reboot.
*/
#define MC_CMD_ENABLE_OFFLINE_BIST 0xed
+#define MC_CMD_ENABLE_OFFLINE_BIST_MSGSET 0xed
#undef MC_CMD_0xed_PRIVILEGE_CTG
#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -18388,6 +19927,7 @@
* forget.
*/
#define MC_CMD_UART_SEND_DATA 0xee
+#define MC_CMD_UART_SEND_DATA_MSGSET 0xee
#undef MC_CMD_0xee_PRIVILEGE_CTG
#define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18426,6 +19966,7 @@
* subject to change and not currently implemented.
*/
#define MC_CMD_UART_RECV_DATA 0xef
+#define MC_CMD_UART_RECV_DATA_MSGSET 0xef
#undef MC_CMD_0xef_PRIVILEGE_CTG
#define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -18475,6 +20016,7 @@
* Read data programmed into the device One-Time-Programmable (OTP) Fuses
*/
#define MC_CMD_READ_FUSES 0xf0
+#define MC_CMD_READ_FUSES_MSGSET 0xf0
#undef MC_CMD_0xf0_PRIVILEGE_CTG
#define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -18510,6 +20052,7 @@
* Get or set KR Serdes RXEQ and TX Driver settings
*/
#define MC_CMD_KR_TUNE 0xf1
+#define MC_CMD_KR_TUNE_MSGSET 0xf1
#undef MC_CMD_0xf1_PRIVILEGE_CTG
#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -19066,6 +20609,7 @@
* Get or set PCIE Serdes RXEQ and TX Driver settings
*/
#define MC_CMD_PCIE_TUNE 0xf2
+#define MC_CMD_PCIE_TUNE_MSGSET 0xf2
#undef MC_CMD_0xf2_PRIVILEGE_CTG
#define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -19323,6 +20867,7 @@
* - not used for V3 licensing
*/
#define MC_CMD_LICENSING 0xf3
+#define MC_CMD_LICENSING_MSGSET 0xf3
#undef MC_CMD_0xf3_PRIVILEGE_CTG
#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19379,6 +20924,7 @@
* - V3 licensing (Medford)
*/
#define MC_CMD_LICENSING_V3 0xd0
+#define MC_CMD_LICENSING_V3_MSGSET 0xd0
#undef MC_CMD_0xd0_PRIVILEGE_CTG
#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19429,7 +20975,13 @@
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LBN 192
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_WIDTH 32
#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LBN 224
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_WIDTH 32
/* reserved for future use */
#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
@@ -19437,7 +20989,13 @@
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LBN 448
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_WIDTH 32
#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LEN 4
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LBN 480
+#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_WIDTH 32
/* reserved for future use */
#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
@@ -19449,6 +21007,7 @@
* partition - V3 licensing (Medford)
*/
#define MC_CMD_LICENSING_GET_ID_V3 0xd1
+#define MC_CMD_LICENSING_GET_ID_V3_MSGSET 0xd1
#undef MC_CMD_0xd1_PRIVILEGE_CTG
#define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19482,6 +21041,7 @@
* This will fail on a single-core system.
*/
#define MC_CMD_MC2MC_PROXY 0xf4
+#define MC_CMD_MC2MC_PROXY_MSGSET 0xf4
#undef MC_CMD_0xf4_PRIVILEGE_CTG
#define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19500,6 +21060,7 @@
* or a reboot of the MC.) Not used for V3 licensing
*/
#define MC_CMD_GET_LICENSED_APP_STATE 0xf5
+#define MC_CMD_GET_LICENSED_APP_STATE_MSGSET 0xf5
#undef MC_CMD_0xf5_PRIVILEGE_CTG
#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19528,6 +21089,7 @@
* operation or a reboot of the MC.) Used for V3 licensing (Medford)
*/
#define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_MSGSET 0xd2
#undef MC_CMD_0xd2_PRIVILEGE_CTG
#define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19540,7 +21102,13 @@
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LEN 4
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LBN 0
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_WIDTH 32
#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LEN 4
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LBN 32
+#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_WIDTH 32
/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */
#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
@@ -19560,6 +21128,7 @@
* operation or a reboot of the MC.) Used for V3 licensing (Medford)
*/
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_MSGSET 0xd3
#undef MC_CMD_0xd3_PRIVILEGE_CTG
#define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19572,7 +21141,13 @@
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LBN 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_WIDTH 32
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LBN 32
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_WIDTH 32
/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8
@@ -19580,7 +21155,13 @@
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LBN 0
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_WIDTH 32
#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LEN 4
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LBN 32
+#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_WIDTH 32
/***********************************/
@@ -19589,6 +21170,7 @@
* licensing.
*/
#define MC_CMD_LICENSED_APP_OP 0xf6
+#define MC_CMD_LICENSED_APP_OP_MSGSET 0xf6
#undef MC_CMD_0xf6_PRIVILEGE_CTG
#define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19672,6 +21254,7 @@
* (Medford)
*/
#define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_MSGSET 0xd4
#undef MC_CMD_0xd4_PRIVILEGE_CTG
#define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19685,7 +21268,13 @@
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LEN 4
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LBN 384
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_WIDTH 32
#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LEN 4
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LBN 416
+#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_WIDTH 32
/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */
#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116
@@ -19725,6 +21314,7 @@
* Mask features - V3 licensing (Medford)
*/
#define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_MSGSET 0xd5
#undef MC_CMD_0xd5_PRIVILEGE_CTG
#define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -19735,7 +21325,13 @@
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LEN 4
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LBN 0
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_WIDTH 32
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LEN 4
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LBN 32
+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_WIDTH 32
/* whether to turn on or turn off the masked features */
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
@@ -19757,6 +21353,7 @@
* erased when the adapter is power cycled
*/
#define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
+#define MC_CMD_LICENSING_V3_TEMPORARY_MSGSET 0xd6
#undef MC_CMD_0xd6_PRIVILEGE_CTG
#define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -19815,7 +21412,13 @@
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LEN 4
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LBN 32
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_WIDTH 32
#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LEN 4
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LBN 64
+#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_WIDTH 32
/***********************************/
@@ -19827,6 +21430,7 @@
* delivered to a specific queue, or a set of queues with RSS.
*/
#define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
+#define MC_CMD_SET_PORT_SNIFF_CONFIG_MSGSET 0xf7
#undef MC_CMD_0xf7_PRIVILEGE_CTG
#define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -19870,6 +21474,7 @@
* the configuration.
*/
#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
+#define MC_CMD_GET_PORT_SNIFF_CONFIG_MSGSET 0xf8
#undef MC_CMD_0xf8_PRIVILEGE_CTG
#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19908,6 +21513,7 @@
* Change configuration related to the parser-dispatcher subsystem.
*/
#define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
+#define MC_CMD_SET_PARSER_DISP_CONFIG_MSGSET 0xf9
#undef MC_CMD_0xf9_PRIVILEGE_CTG
#define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19953,6 +21559,7 @@
* Read configuration related to the parser-dispatcher subsystem.
*/
#define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
+#define MC_CMD_GET_PARSER_DISP_CONFIG_MSGSET 0xfa
#undef MC_CMD_0xfa_PRIVILEGE_CTG
#define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -19997,6 +21604,7 @@
* dedicated as TX sniff receivers.
*/
#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
+#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_MSGSET 0xfb
#undef MC_CMD_0xfb_PRIVILEGE_CTG
#define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20037,6 +21645,7 @@
* the configuration.
*/
#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
+#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_MSGSET 0xfc
#undef MC_CMD_0xfc_PRIVILEGE_CTG
#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20072,6 +21681,7 @@
* Per queue rx error stats.
*/
#define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
+#define MC_CMD_RMON_STATS_RX_ERRORS_MSGSET 0xfe
#undef MC_CMD_0xfe_PRIVILEGE_CTG
#define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20104,6 +21714,7 @@
* Find out about available PCIE resources
*/
#define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
+#define MC_CMD_GET_PCIE_RESOURCE_INFO_MSGSET 0xfd
#undef MC_CMD_0xfd_PRIVILEGE_CTG
#define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20143,6 +21754,7 @@
* Find out about available port modes
*/
#define MC_CMD_GET_PORT_MODES 0xff
+#define MC_CMD_GET_PORT_MODES_MSGSET 0xff
#undef MC_CMD_0xff_PRIVILEGE_CTG
#define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20199,6 +21811,7 @@
* the new port mode, as the override does not affect PF configuration.
*/
#define MC_CMD_OVERRIDE_PORT_MODE 0x137
+#define MC_CMD_OVERRIDE_PORT_MODE_MSGSET 0x137
#undef MC_CMD_0x137_PRIVILEGE_CTG
#define MC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20223,6 +21836,7 @@
* Sample voltages on the ATB
*/
#define MC_CMD_READ_ATB 0x100
+#define MC_CMD_READ_ATB_MSGSET 0x100
#undef MC_CMD_0x100_PRIVILEGE_CTG
#define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20253,6 +21867,7 @@
* enums here must correspond with those in MC_CMD_WORKAROUND.
*/
#define MC_CMD_GET_WORKAROUNDS 0x59
+#define MC_CMD_GET_WORKAROUNDS_MSGSET 0x59
#undef MC_CMD_0x59_PRIVILEGE_CTG
#define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20290,6 +21905,7 @@
* Read/set privileges of an arbitrary PCIe function
*/
#define MC_CMD_PRIVILEGE_MASK 0x5a
+#define MC_CMD_PRIVILEGE_MASK_MSGSET 0x5a
#undef MC_CMD_0x5a_PRIVILEGE_CTG
#define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20351,6 +21967,20 @@
#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
/* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */
#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000
+/* enum: This Function/client may call MC_CMD_CLIENT_ALLOC to create new
+ * dynamic client children of itself.
+ */
+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALLOC_CLIENT 0x20000
+/* enum: A dynamic client with this privilege may perform all the same DMA
+ * operations as the function client from which it is descended.
+ */
+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_FUNC_DMA 0x40000
+/* enum: A client with this privilege may perform DMA as any PCIe function on
+ * the device and to on-device DDR. It allows clients to use TX-DESC2CMPT-DESC
+ * descriptors, and to use TX-SEG-DESC and TX-MEM2MEM-DESC with an address
+ * space override (i.e. with the ADDR_SPC_EN bit set).
+ */
+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ARBITRARY_DMA 0x80000
/* enum: Set this bit to indicate that a new privilege mask is to be set,
* otherwise the command will only read the existing mask.
*/
@@ -20368,6 +21998,7 @@
* Read/set link state mode of a VF
*/
#define MC_CMD_LINK_STATE_MODE 0x5c
+#define MC_CMD_LINK_STATE_MODE_MSGSET 0x5c
#undef MC_CMD_0x5c_PRIVILEGE_CTG
#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20407,6 +22038,7 @@
* parameter to MC_CMD_INIT_RXQ.
*/
#define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
+#define MC_CMD_GET_SNAPSHOT_LENGTH_MSGSET 0x101
#undef MC_CMD_0x101_PRIVILEGE_CTG
#define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -20429,6 +22061,7 @@
* Additional fuse diagnostics
*/
#define MC_CMD_FUSE_DIAGS 0x102
+#define MC_CMD_FUSE_DIAGS_MSGSET 0x102
#undef MC_CMD_0x102_PRIVILEGE_CTG
#define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20483,6 +22116,7 @@
* included in one of the masks provided.
*/
#define MC_CMD_PRIVILEGE_MODIFY 0x60
+#define MC_CMD_PRIVILEGE_MODIFY_MSGSET 0x60
#undef MC_CMD_0x60_PRIVILEGE_CTG
#define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20527,6 +22161,7 @@
* Read XPM memory
*/
#define MC_CMD_XPM_READ_BYTES 0x103
+#define MC_CMD_XPM_READ_BYTES_MSGSET 0x103
#undef MC_CMD_0x103_PRIVILEGE_CTG
#define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -20559,6 +22194,7 @@
* Write XPM memory
*/
#define MC_CMD_XPM_WRITE_BYTES 0x104
+#define MC_CMD_XPM_WRITE_BYTES_MSGSET 0x104
#undef MC_CMD_0x104_PRIVILEGE_CTG
#define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20591,6 +22227,7 @@
* Read XPM sector
*/
#define MC_CMD_XPM_READ_SECTOR 0x105
+#define MC_CMD_XPM_READ_SECTOR_MSGSET 0x105
#undef MC_CMD_0x105_PRIVILEGE_CTG
#define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20631,6 +22268,7 @@
* Write XPM sector
*/
#define MC_CMD_XPM_WRITE_SECTOR 0x106
+#define MC_CMD_XPM_WRITE_SECTOR_MSGSET 0x106
#undef MC_CMD_0x106_PRIVILEGE_CTG
#define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20677,6 +22315,7 @@
* Invalidate XPM sector
*/
#define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
+#define MC_CMD_XPM_INVALIDATE_SECTOR_MSGSET 0x107
#undef MC_CMD_0x107_PRIVILEGE_CTG
#define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20696,6 +22335,7 @@
* Blank-check XPM memory and report bad locations
*/
#define MC_CMD_XPM_BLANK_CHECK 0x108
+#define MC_CMD_XPM_BLANK_CHECK_MSGSET 0x108
#undef MC_CMD_0x108_PRIVILEGE_CTG
#define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20733,6 +22373,7 @@
* Blank-check and repair XPM memory
*/
#define MC_CMD_XPM_REPAIR 0x109
+#define MC_CMD_XPM_REPAIR_MSGSET 0x109
#undef MC_CMD_0x109_PRIVILEGE_CTG
#define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20756,6 +22397,7 @@
* be performed on an unprogrammed part.
*/
#define MC_CMD_XPM_DECODER_TEST 0x10a
+#define MC_CMD_XPM_DECODER_TEST_MSGSET 0x10a
#undef MC_CMD_0x10a_PRIVILEGE_CTG
#define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20776,6 +22418,7 @@
* first available location to use, or fail with ENOSPC if none left.
*/
#define MC_CMD_XPM_WRITE_TEST 0x10b
+#define MC_CMD_XPM_WRITE_TEST_MSGSET 0x10b
#undef MC_CMD_0x10b_PRIVILEGE_CTG
#define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -20797,6 +22440,7 @@
* does match, otherwise it will respond with success before it jumps to IMEM.
*/
#define MC_CMD_EXEC_SIGNED 0x10c
+#define MC_CMD_EXEC_SIGNED_MSGSET 0x10c
#undef MC_CMD_0x10c_PRIVILEGE_CTG
#define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -20827,6 +22471,7 @@
* MC_CMD_EXEC_SIGNED.
*/
#define MC_CMD_PREPARE_SIGNED 0x10d
+#define MC_CMD_PREPARE_SIGNED_MSGSET 0x10d
#undef MC_CMD_0x10d_PRIVILEGE_CTG
#define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -20850,6 +22495,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_SET_SECURITY_RULE 0x10f
+#define MC_CMD_SET_SECURITY_RULE_MSGSET 0x10f
#undef MC_CMD_0x10f_PRIVILEGE_CTG
#define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21040,6 +22686,7 @@
* development. This note will be removed once it is regarded as stable.
*/
#define MC_CMD_RESET_SECURITY_RULES 0x110
+#define MC_CMD_RESET_SECURITY_RULES_MSGSET 0x110
#undef MC_CMD_0x110_PRIVILEGE_CTG
#define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21066,6 +22713,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111
+#define MC_CMD_GET_SECURITY_RULESET_VERSION_MSGSET 0x111
#undef MC_CMD_0x111_PRIVILEGE_CTG
#define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -21096,6 +22744,7 @@
* removed once it is regarded as stable.
*/
#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112
+#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_MSGSET 0x112
#undef MC_CMD_0x112_PRIVILEGE_CTG
#define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21134,6 +22783,7 @@
* removed once it is regarded as stable.
*/
#define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113
+#define MC_CMD_SECURITY_RULE_COUNTER_FREE_MSGSET 0x113
#undef MC_CMD_0x113_PRIVILEGE_CTG
#define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21169,6 +22819,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_SUBNET_MAP_SET_NODE 0x114
+#define MC_CMD_SUBNET_MAP_SET_NODE_MSGSET 0x114
#undef MC_CMD_0x114_PRIVILEGE_CTG
#define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21224,6 +22875,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115
+#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_MSGSET 0x115
#undef MC_CMD_0x115_PRIVILEGE_CTG
#define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21258,6 +22910,7 @@
* will be removed once it is regarded as stable.
*/
#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116
+#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_MSGSET 0x116
#undef MC_CMD_0x116_PRIVILEGE_CTG
#define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21311,6 +22964,7 @@
* cause all functions to see a reset. (Available on Medford only.)
*/
#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
+#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_MSGSET 0x117
#undef MC_CMD_0x117_PRIVILEGE_CTG
#define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -21357,6 +23011,7 @@
* priority.
*/
#define MC_CMD_RX_BALANCING 0x118
+#define MC_CMD_RX_BALANCING_MSGSET 0x118
#undef MC_CMD_0x118_PRIVILEGE_CTG
#define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -21386,6 +23041,7 @@
* info in respect to the binding protocol.
*/
#define MC_CMD_TSA_BIND 0x119
+#define MC_CMD_TSA_BIND_MSGSET 0x119
#undef MC_CMD_0x119_PRIVILEGE_CTG
#define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -21951,6 +23607,7 @@
* OP_GET_CACHED_VERSION. All other sub-operations are prohibited.
*/
#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a
+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_MSGSET 0x11a
#undef MC_CMD_0x11a_PRIVILEGE_CTG
#define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22007,6 +23664,7 @@
* if the tag is already present.
*/
#define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
+#define MC_CMD_NVRAM_PRIVATE_APPEND_MSGSET 0x11c
#undef MC_CMD_0x11c_PRIVILEGE_CTG
#define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22041,6 +23699,7 @@
* correctly at ATE.
*/
#define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
+#define MC_CMD_XPM_VERIFY_CONTENTS_MSGSET 0x11b
#undef MC_CMD_0x11b_PRIVILEGE_CTG
#define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22084,6 +23743,7 @@
* and TMR_RELOAD_ACT_NS).
*/
#define MC_CMD_SET_EVQ_TMR 0x120
+#define MC_CMD_SET_EVQ_TMR_MSGSET 0x120
#undef MC_CMD_0x120_PRIVILEGE_CTG
#define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22122,6 +23782,7 @@
* Query properties about the event queue timers.
*/
#define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
+#define MC_CMD_GET_EVQ_TMR_PROPERTIES_MSGSET 0x122
#undef MC_CMD_0x122_PRIVILEGE_CTG
#define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22191,6 +23852,7 @@
* non used switch buffers.
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_MSGSET 0x11d
#undef MC_CMD_0x11d_PRIVILEGE_CTG
#define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22198,7 +23860,8 @@
/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
/* Desired instance. Must be set to a specific instance, which is a function
- * local queue index.
+ * local queue index. The calling client must be the currently-assigned user of
+ * this VI (see MC_CMD_SET_VI_USER).
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
@@ -22243,6 +23906,7 @@
* previously allocated common pools.
*/
#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_MSGSET 0x11e
#undef MC_CMD_0x11e_PRIVILEGE_CTG
#define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22296,6 +23960,7 @@
* ready to be re-used.
*/
#define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
+#define MC_CMD_TEARDOWN_TX_VFIFO_VF_MSGSET 0x11f
#undef MC_CMD_0x11f_PRIVILEGE_CTG
#define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22316,6 +23981,7 @@
* it ready to be re-used.
*/
#define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
+#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_MSGSET 0x121
#undef MC_CMD_0x121_PRIVILEGE_CTG
#define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22344,6 +24010,7 @@
* or 0 if there has not been a previous rekey.
*/
#define MC_CMD_REKEY 0x123
+#define MC_CMD_REKEY_MSGSET 0x123
#undef MC_CMD_0x123_PRIVILEGE_CTG
#define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22368,6 +24035,7 @@
* not yet assigned.
*/
#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
+#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_MSGSET 0x124
#undef MC_CMD_0x124_PRIVILEGE_CTG
#define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -22396,6 +24064,7 @@
* the required bits were not set.
*/
#define MC_CMD_SET_SECURITY_FUSES 0x126
+#define MC_CMD_SET_SECURITY_FUSES_MSGSET 0x126
#undef MC_CMD_0x126_PRIVILEGE_CTG
#define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22438,6 +24107,7 @@
* SF-117371-SW
*/
#define MC_CMD_TSA_INFO 0x127
+#define MC_CMD_TSA_INFO_MSGSET 0x127
#undef MC_CMD_0x127_PRIVILEGE_CTG
#define MC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22614,6 +24284,7 @@
* Doxbox reference SF-117371-SW
*/
#define MC_CMD_HOST_INFO 0x128
+#define MC_CMD_HOST_INFO_MSGSET 0x128
#undef MC_CMD_0x128_PRIVILEGE_CTG
#define MC_CMD_0x128_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22681,6 +24352,7 @@
* section 'Adapter Information'
*/
#define MC_CMD_TSAN_INFO 0x129
+#define MC_CMD_TSAN_INFO_MSGSET 0x129
#undef MC_CMD_0x129_PRIVILEGE_CTG
#define MC_CMD_0x129_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -22780,6 +24452,7 @@
* TSA adapter statistics operations.
*/
#define MC_CMD_TSA_STATISTICS 0x130
+#define MC_CMD_TSA_STATISTICS_MSGSET 0x130
#undef MC_CMD_0x130_PRIVILEGE_CTG
#define MC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22884,14 +24557,26 @@
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LEN 8
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_LBN 0
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_OFST 4
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_LBN 32
+#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0
#define MC_TSA_STATISTICS_ENTRY_TX_STAT_WIDTH 64
/* Rx statistics counter */
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_OFST 8
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LEN 8
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_OFST 8
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_LBN 64
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_OFST 12
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_LEN 4
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_LBN 96
+#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_WIDTH 32
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64
#define MC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64
@@ -22904,6 +24589,7 @@
* installing TSA binding certificates. See SF-117631-TC.
*/
#define MC_CMD_ERASE_INITIAL_NIC_SECRET 0x131
+#define MC_CMD_ERASE_INITIAL_NIC_SECRET_MSGSET 0x131
#undef MC_CMD_0x131_PRIVILEGE_CTG
#define MC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -22921,6 +24607,7 @@
* NIC for TSA binding.
*/
#define MC_CMD_TSA_CONFIG 0x64
+#define MC_CMD_TSA_CONFIG_MSGSET 0x64
#undef MC_CMD_0x64_PRIVILEGE_CTG
#define MC_CMD_0x64_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23038,6 +24725,7 @@
* to a TSA adapter.
*/
#define MC_CMD_TSA_IPADDR 0x65
+#define MC_CMD_TSA_IPADDR_MSGSET 0x65
#undef MC_CMD_0x65_PRIVILEGE_CTG
#define MC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23089,7 +24777,13 @@
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_OFST 8
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LEN 8
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_OFST 8
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_LBN 64
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_OFST 12
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_LBN 96
+#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MINNUM 1
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM 30
#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM_MCDI2 126
@@ -23119,7 +24813,13 @@
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_OFST 8
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LEN 8
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_OFST 8
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_LBN 64
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_OFST 12
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_LEN 4
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_LBN 96
+#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_WIDTH 32
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MINNUM 1
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM 30
#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM_MCDI2 126
@@ -23135,6 +24835,7 @@
* disabled.
*/
#define MC_CMD_SECURE_NIC_INFO 0x132
+#define MC_CMD_SECURE_NIC_INFO_MSGSET 0x132
#undef MC_CMD_0x132_PRIVILEGE_CTG
#define MC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23228,6 +24929,7 @@
* parameters in request or response.
*/
#define MC_CMD_TSA_TEST 0x125
+#define MC_CMD_TSA_TEST_MSGSET 0x125
#undef MC_CMD_0x125_PRIVILEGE_CTG
#define MC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23249,6 +24951,7 @@
* rule-set transitions.
*/
#define MC_CMD_TSA_RULESET_OVERRIDE 0x12a
+#define MC_CMD_TSA_RULESET_OVERRIDE_MSGSET 0x12a
#undef MC_CMD_0x12a_PRIVILEGE_CTG
#define MC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23281,6 +24984,7 @@
* Specific usage is determined by the TYPE field.
*/
#define MC_CMD_TSAC_REQUEST 0x12b
+#define MC_CMD_TSAC_REQUEST_MSGSET 0x12b
#undef MC_CMD_0x12b_PRIVILEGE_CTG
#define MC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23305,6 +25009,7 @@
* Get the version of the SUC
*/
#define MC_CMD_SUC_VERSION 0x134
+#define MC_CMD_SUC_VERSION_MSGSET 0x134
#undef MC_CMD_0x134_PRIVILEGE_CTG
#define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23350,6 +25055,7 @@
* Operations to support manftest on SUC based systems.
*/
#define MC_CMD_SUC_MANFTEST 0x135
+#define MC_CMD_SUC_MANFTEST_MSGSET 0x135
#undef MC_CMD_0x135_PRIVILEGE_CTG
#define MC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
@@ -23546,6 +25252,7 @@
* Request a certificate.
*/
#define MC_CMD_GET_CERTIFICATE 0x12c
+#define MC_CMD_GET_CERTIFICATE_MSGSET 0x12c
#undef MC_CMD_0x12c_PRIVILEGE_CTG
#define MC_CMD_0x12c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23620,6 +25327,7 @@
* Get a global value which applies to all PCI functions
*/
#define MC_CMD_GET_NIC_GLOBAL 0x12d
+#define MC_CMD_GET_NIC_GLOBAL_MSGSET 0x12d
#undef MC_CMD_0x12d_PRIVILEGE_CTG
#define MC_CMD_0x12d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23647,6 +25355,7 @@
* appropriate error otherwise (see key descriptions).
*/
#define MC_CMD_SET_NIC_GLOBAL 0x12e
+#define MC_CMD_SET_NIC_GLOBAL_MSGSET 0x12e
#undef MC_CMD_0x12e_PRIVILEGE_CTG
#define MC_CMD_0x12e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23694,6 +25403,7 @@
* firmware buffer for later extraction.
*/
#define MC_CMD_LTSSM_TRACE_POLL 0x12f
+#define MC_CMD_LTSSM_TRACE_POLL_MSGSET 0x12f
#undef MC_CMD_0x12f_PRIVILEGE_CTG
#define MC_CMD_0x12f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23731,7 +25441,13 @@
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_OFST 8
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LEN 8
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_OFST 8
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_LEN 4
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_LBN 64
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_WIDTH 32
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_OFST 12
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_LEN 4
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_LBN 96
+#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_WIDTH 32
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MINNUM 0
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM 30
#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM_MCDI2 126
@@ -23765,6 +25481,7 @@
* firmware variant.
*/
#define MC_CMD_TELEMETRY_ENABLE 0x138
+#define MC_CMD_TELEMETRY_ENABLE_MSGSET 0x138
#undef MC_CMD_0x138_PRIVILEGE_CTG
#define MC_CMD_0x138_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23856,6 +25573,7 @@
* Reference - SF-120569-SW Telemetry Firmware Design.
*/
#define MC_CMD_TELEMETRY_CONFIG 0x139
+#define MC_CMD_TELEMETRY_CONFIG_MSGSET 0x139
#undef MC_CMD_0x139_PRIVILEGE_CTG
#define MC_CMD_0x139_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -23925,6 +25643,7 @@
* due to resource constraints, returns ENOSPC.
*/
#define MC_CMD_GET_RX_PREFIX_ID 0x13b
+#define MC_CMD_GET_RX_PREFIX_ID_MSGSET 0x13b
#undef MC_CMD_0x13b_PRIVILEGE_CTG
#define MC_CMD_0x13b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -23935,7 +25654,13 @@
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LEN 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LBN 0
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_WIDTH 32
#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LEN 4
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LBN 32
+#define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_WIDTH 32
#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0
#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0
#define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1
@@ -24056,6 +25781,7 @@
* created with that prefix id
*/
#define MC_CMD_QUERY_RX_PREFIX_ID 0x13c
+#define MC_CMD_QUERY_RX_PREFIX_ID_MSGSET 0x13c
#undef MC_CMD_0x13c_PRIVILEGE_CTG
#define MC_CMD_0x13c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24092,6 +25818,7 @@
* A command to perform various bundle-related operations on insecure cards.
*/
#define MC_CMD_BUNDLE 0x13d
+#define MC_CMD_BUNDLE_MSGSET 0x13d
#undef MC_CMD_0x13d_PRIVILEGE_CTG
#define MC_CMD_0x13d_PRIVILEGE_CTG SRIOV_CTG_INSECURE
@@ -24154,6 +25881,7 @@
* Read all VPD starting from a given address
*/
#define MC_CMD_GET_VPD 0x165
+#define MC_CMD_GET_VPD_MSGSET 0x165
#undef MC_CMD_0x165_PRIVILEGE_CTG
#define MC_CMD_0x165_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24185,6 +25913,7 @@
* Provide information about the NC-SI stack
*/
#define MC_CMD_GET_NCSI_INFO 0x167
+#define MC_CMD_GET_NCSI_INFO_MSGSET 0x167
#undef MC_CMD_0x167_PRIVILEGE_CTG
#define MC_CMD_0x167_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24256,6 +25985,7 @@
* System lockdown, when enabled firmware updates are blocked.
*/
#define MC_CMD_FIRMWARE_SET_LOCKDOWN 0x16f
+#define MC_CMD_FIRMWARE_SET_LOCKDOWN_MSGSET 0x16f
#undef MC_CMD_0x16f_PRIVILEGE_CTG
#define MC_CMD_0x16f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -24278,6 +26008,7 @@
* documentation.
*/
#define MC_CMD_GET_TEST_FEATURES 0x1ac
+#define MC_CMD_GET_TEST_FEATURES_MSGSET 0x1ac
#undef MC_CMD_0x1ac_PRIVILEGE_CTG
#define MC_CMD_0x1ac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24300,6 +26031,253 @@
#define MC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM 63
#define MC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM_MCDI2 255
+
+/***********************************/
+/* MC_CMD_FPGA
+ * A command to perform various fpga-related operations on platforms that
+ * include FPGAs. Note that some platforms may only support a subset of these
+ * operations.
+ */
+#define MC_CMD_FPGA 0x1bf
+#define MC_CMD_FPGA_MSGSET 0x1bf
+#undef MC_CMD_0x1bf_PRIVILEGE_CTG
+
+#define MC_CMD_0x1bf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_FPGA_IN msgrequest */
+#define MC_CMD_FPGA_IN_LEN 4
+/* Sub-command code */
+#define MC_CMD_FPGA_IN_OP_OFST 0
+#define MC_CMD_FPGA_IN_OP_LEN 4
+/* enum: Get the FPGA version string. */
+#define MC_CMD_FPGA_IN_OP_GET_VERSION 0x0
+/* enum: Read bitmask of features supported in the FPGA image. */
+#define MC_CMD_FPGA_IN_OP_GET_CAPABILITIES 0x1
+/* enum: Perform a FPGA reset. */
+#define MC_CMD_FPGA_IN_OP_RESET 0x2
+/* enum: Set active flash device. */
+#define MC_CMD_FPGA_IN_OP_SELECT_FLASH 0x3
+/* enum: Get active flash device. */
+#define MC_CMD_FPGA_IN_OP_GET_ACTIVE_FLASH 0x4
+/* enum: Configure internal link i.e. the FPGA port facing the ASIC. */
+#define MC_CMD_FPGA_IN_OP_SET_INTERNAL_LINK 0x5
+/* enum: Read internal link configuration. */
+#define MC_CMD_FPGA_IN_OP_GET_INTERNAL_LINK 0x6
+
+/* MC_CMD_FPGA_OP_GET_VERSION_IN msgrequest: Get the FPGA version string. A
+ * free-format string is returned in response to this command. Any checks on
+ * supported FPGA operations are based on the response to
+ * MC_CMD_FPGA_OP_GET_CAPABILITIES.
+ */
+#define MC_CMD_FPGA_OP_GET_VERSION_IN_LEN 4
+/* Sub-command code. Must be OP_GET_VERSION */
+#define MC_CMD_FPGA_OP_GET_VERSION_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_VERSION_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_VERSION_OUT msgresponse: Returns the version string. */
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LENMIN 0
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LENMAX 252
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_LEN(num) (0+1*(num))
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_NUM(len) (((len)-0)/1)
+/* Null-terminated string containing version information. */
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_OFST 0
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_LEN 1
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MINNUM 0
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MAXNUM 252
+#define MC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MAXNUM_MCDI2 1020
+
+/* MC_CMD_FPGA_OP_GET_CAPABILITIES_IN msgrequest: Read bitmask of features
+ * supported in the FPGA image.
+ */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_IN_LEN 4
+/* Sub-command code. Must be OP_GET_CAPABILITIES */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT msgresponse: Returns the version string.
+ */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_LEN 4
+/* Bit-mask of supported features. */
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_CAPABILITIES_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_CAPABILITIES_LEN 4
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_LBN 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_WIDTH 1
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_OFST 0
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_LBN 1
+#define MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_WIDTH 1
+
+/* MC_CMD_FPGA_OP_RESET_IN msgrequest: Perform a FPGA reset operation where
+ * supported.
+ */
+#define MC_CMD_FPGA_OP_RESET_IN_LEN 4
+/* Sub-command code. Must be OP_RESET */
+#define MC_CMD_FPGA_OP_RESET_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_RESET_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_RESET_OUT msgresponse */
+#define MC_CMD_FPGA_OP_RESET_OUT_LEN 0
+
+/* MC_CMD_FPGA_OP_SELECT_FLASH_IN msgrequest: Set active FPGA flash device.
+ * Returns EINVAL if selected flash index does not exist on the platform under
+ * test.
+ */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_LEN 8
+/* Sub-command code. Must be OP_SELECT_FLASH */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_OP_LEN 4
+/* Flash device identifier. */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_FLASH_ID_OFST 4
+#define MC_CMD_FPGA_OP_SELECT_FLASH_IN_FLASH_ID_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_FPGA_FLASH_INDEX */
+
+/* MC_CMD_FPGA_OP_SELECT_FLASH_OUT msgresponse */
+#define MC_CMD_FPGA_OP_SELECT_FLASH_OUT_LEN 0
+
+/* MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN msgrequest: Get active FPGA flash device.
+ */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_LEN 4
+/* Sub-command code. Must be OP_GET_ACTIVE_FLASH */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT msgresponse: Returns flash identifier
+ * for current active flash.
+ */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_LEN 4
+/* Flash device identifier. */
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_FLASH_ID_OFST 0
+#define MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_FLASH_ID_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_FPGA_FLASH_INDEX */
+
+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN msgrequest: Configure FPGA internal
+ * port, facing the ASIC
+ */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LEN 12
+/* Sub-command code. Must be OP_SET_INTERNAL_LINK */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_OP_LEN 4
+/* Flags */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLAGS_OFST 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLAGS_LEN 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_OFST 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_LBN 0
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_WIDTH 2
+/* enum: Unmodified, same as last state set by firmware */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_AUTO 0x0
+/* enum: Configure link-up */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_UP 0x1
+/* enum: Configure link-down */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_DOWN 0x2
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_OFST 4
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_LBN 2
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_WIDTH 1
+/* Link speed to be applied on FPGA internal port MAC. */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_SPEED_OFST 8
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_SPEED_LEN 4
+
+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_OUT msgresponse */
+#define MC_CMD_FPGA_OP_SET_INTERNAL_LINK_OUT_LEN 0
+
+/* MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN msgrequest: Read FPGA internal port
+ * configuration and status
+ */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_LEN 4
+/* Sub-command code. Must be OP_GET_INTERNAL_LINK */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_OP_OFST 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_OP_LEN 4
+
+/* MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT msgresponse: Response format for read
+ * FPGA internal port configuration and status
+ */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LEN 8
+/* Flags */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_FLAGS_OFST 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_FLAGS_LEN 4
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_OFST 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_LBN 0
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_WIDTH 2
+/* Enum values, see field(s): */
+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN/FLAGS */
+/* Link speed set on FPGA internal port MAC. */
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_SPEED_OFST 4
+#define MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_SPEED_LEN 4
+
+
+/***********************************/
+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE
+ * This command is expected to be used on a U25 board with an MAE in the FPGA.
+ * It does not modify the operational state of the NIC. The modes are described
+ * in XN-200039-TC - U25 OVS packet formats.
+ */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE 0x1c0
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_MSGSET 0x1c0
+#undef MC_CMD_0x1c0_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_IN msgrequest */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_IN_LEN 0
+
+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT msgresponse */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_LEN 4
+/* The current link mode */
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_MODE_OFST 0
+#define MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_MODE_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_EXTERNAL_MAE_LINK_MODE */
+
+
+/***********************************/
+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE
+ * This command is expected to be used on a U25 board with an MAE in the FPGA.
+ * The modes are described in XN-200039-TC - U25 OVS packet formats. This
+ * command will set the link between the FPGA and the X2 to the specified new
+ * mode. It will first enter bootstrap mode, make sure there are no packets in
+ * flight and then enter the requested mode. In order to make sure there are no
+ * packets in flight, it will flush the X2 TX path, the FPGA RX path from the
+ * X2, the FPGA TX path to the X2 and the X2 RX path. The driver is responsible
+ * for making sure there are no TX or RX descriptors posted on any TXQ or RXQ
+ * associated with the affected port before invoking this command. This command
+ * is run implicitly with MODE set to LEGACY when MC_CMD_DRV_ATTACH is
+ * executed.
+ */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE 0x1c1
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_MSGSET 0x1c1
+#undef MC_CMD_0x1c1_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN msgrequest */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_LEN 4
+/* The new link mode. */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_MODE_OFST 0
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_MODE_LEN 4
+/* Enum values, see field(s): */
+/* MC_CMD_EXTERNAL_MAE_LINK_MODE */
+
+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_OUT msgresponse */
+#define MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_OUT_LEN 0
+
+/* CLIENT_HANDLE structuredef: A client is an abstract entity that can make
+ * requests of the device and that can own resources managed by the device.
+ * Examples of clients include PCIe functions and dynamic clients. A client
+ * handle is a 32b opaque value used to refer to a client. Further details can
+ * be found within XN-200418-TC.
+ */
+#define CLIENT_HANDLE_LEN 4
+#define CLIENT_HANDLE_OPAQUE_OFST 0
+#define CLIENT_HANDLE_OPAQUE_LEN 4
+/* enum: A client handle guaranteed never to refer to a real client. */
+#define CLIENT_HANDLE_NULL 0xffffffff
+/* enum: Used to refer to the calling client. */
+#define CLIENT_HANDLE_SELF 0xfffffffe
+#define CLIENT_HANDLE_OPAQUE_LBN 0
+#define CLIENT_HANDLE_OPAQUE_WIDTH 32
+
/* CLOCK_INFO structuredef: Information about a single hardware clock */
#define CLOCK_INFO_LEN 28
/* Enumeration that uniquely identifies the clock */
@@ -24333,7 +26311,13 @@
#define CLOCK_INFO_FREQUENCY_OFST 4
#define CLOCK_INFO_FREQUENCY_LEN 8
#define CLOCK_INFO_FREQUENCY_LO_OFST 4
+#define CLOCK_INFO_FREQUENCY_LO_LEN 4
+#define CLOCK_INFO_FREQUENCY_LO_LBN 32
+#define CLOCK_INFO_FREQUENCY_LO_WIDTH 32
#define CLOCK_INFO_FREQUENCY_HI_OFST 8
+#define CLOCK_INFO_FREQUENCY_HI_LEN 4
+#define CLOCK_INFO_FREQUENCY_HI_LBN 64
+#define CLOCK_INFO_FREQUENCY_HI_WIDTH 32
#define CLOCK_INFO_FREQUENCY_LBN 32
#define CLOCK_INFO_FREQUENCY_WIDTH 64
/* Human-readable ASCII name for clock, with NUL termination */
@@ -24343,12 +26327,62 @@
#define CLOCK_INFO_NAME_LBN 96
#define CLOCK_INFO_NAME_WIDTH 8
+/* SCHED_CREDIT_CHECK_RESULT structuredef */
+#define SCHED_CREDIT_CHECK_RESULT_LEN 16
+/* The instance of the scheduler. Refer to XN-200389-AW for the location of
+ * these schedulers in the hardware.
+ */
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LEN 1
+#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_A 0x0 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_A 0x1 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_B 0x2 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_C 0x3 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_TX 0x4 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_D 0x5 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_HUB_REPLAY 0x6 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0
+#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_WIDTH 8
+/* The type of node that this result refers to. */
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_OFST 1
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LEN 1
+/* enum: Destination node */
+#define SCHED_CREDIT_CHECK_RESULT_DEST 0x0
+/* enum: Source node */
+#define SCHED_CREDIT_CHECK_RESULT_SOURCE 0x1
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LBN 8
+#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_WIDTH 8
+/* Level of node in scheduler hierarchy (level 0 is the bottom of the
+ * hierarchy, increasing towards the root node).
+ */
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_OFST 2
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LEN 2
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LBN 16
+#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_WIDTH 16
+/* Node index */
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_OFST 4
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LEN 4
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LBN 32
+#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_WIDTH 32
+/* The number of credits the node is expected to have. */
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_OFST 8
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LEN 4
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LBN 64
+#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_WIDTH 32
+/* The number of credits the node actually had. */
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_OFST 12
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LBN 96
+#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_WIDTH 32
+
/***********************************/
/* MC_CMD_GET_CLOCKS_INFO
* Get information about the device clocks
*/
#define MC_CMD_GET_CLOCKS_INFO 0x166
+#define MC_CMD_GET_CLOCKS_INFO_MSGSET 0x166
#undef MC_CMD_0x166_PRIVILEGE_CTG
#define MC_CMD_0x166_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24387,6 +26421,7 @@
* returns ENOSPC if the caller's table is full.
*/
#define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d
+#define MC_CMD_VNIC_ENCAP_RULE_ADD_MSGSET 0x16d
#undef MC_CMD_0x16d_PRIVILEGE_CTG
#define MC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24469,6 +26504,7 @@
* if the input HANDLE doesn't correspond to an existing rule.
*/
#define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e
+#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_MSGSET 0x16e
#undef MC_CMD_0x16e_PRIVILEGE_CTG
#define MC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24508,303 +26544,568 @@
#define UUID_NODE_LBN 80
#define UUID_NODE_WIDTH 48
-/* MC_CMD_DEVEL_DUMP_VI_ENTRY structuredef */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_LEN 28
-/* Type of entry */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_C2H 0x0 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_H2C 0x1 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_C2H 0x2 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_H2C 0x3 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_C2H 0x4 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_H2C 0x5 /* enum */
-/* enum: First QDMA writeback/completion queue. Used for ef100, C2H VDPA and
- * plain virtio.
- */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_WRB 0x6
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_PFTCH 0x7 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_QTBL 0x100 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_C2H_QTBL 0x101 /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_VIO 0x10a /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LBN 0
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_WIDTH 32
-/* Internal QDMA/dmac queue number for this entry */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_OFST 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LBN 32
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_WIDTH 32
-/* Size of entry data */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_OFST 8
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LBN 64
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_WIDTH 32
-/* Offset of entry data from start of MCDI message response payload */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_OFST 12
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LBN 96
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_WIDTH 32
-/* Absolute VI of the entry, or 0xffffffff if not available/applicable */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_OFST 16
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_NO_ABS_VI 0xffffffff /* enum */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LBN 128
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_WIDTH 32
-/* Reserved */
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_OFST 20
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LEN 8
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LO_OFST 20
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_HI_OFST 24
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LBN 160
-#define MC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_WIDTH 64
-
-
-/***********************************/
-/* MC_CMD_DEVEL_DUMP_VI
- * Dump various parts of the hardware's state for a VI.
- */
-#define MC_CMD_DEVEL_DUMP_VI 0x1b5
-#undef MC_CMD_0x1b5_PRIVILEGE_CTG
-
-#define MC_CMD_0x1b5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
-
-/* MC_CMD_DEVEL_DUMP_VI_IN msgrequest */
-#define MC_CMD_DEVEL_DUMP_VI_IN_LEN 4
-/* Absolute queue id of queue to dump state for */
-#define MC_CMD_DEVEL_DUMP_VI_IN_QID_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_IN_QID_LEN 4
-
-/* MC_CMD_DEVEL_DUMP_VI_IN_V2 msgrequest */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_LEN 20
-/* Which queue to dump. The meaning of this field dependes on ADDRESS_MODE. */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ID_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ID_LEN 4
-/* Method of referring to the queue to dump */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_OFST 4
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_LEN 4
-/* enum: First field refers to queue number as understood by QDMA/DMAC hardware
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_QUEUE_NUMBER 0x0
-/* enum: First field refers to absolute VI number */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_ABS_VI 0x1
-/* enum: First field refers to function-relative VI number on the command's
- * function
+/* PLUGIN_EXTENSION structuredef: Used within MC_CMD_PLUGIN_GET_ALL to describe
+ * an individual extension.
+ */
+#define PLUGIN_EXTENSION_LEN 20
+#define PLUGIN_EXTENSION_UUID_OFST 0
+#define PLUGIN_EXTENSION_UUID_LEN 16
+#define PLUGIN_EXTENSION_UUID_LBN 0
+#define PLUGIN_EXTENSION_UUID_WIDTH 128
+#define PLUGIN_EXTENSION_ADMIN_GROUP_OFST 16
+#define PLUGIN_EXTENSION_ADMIN_GROUP_LEN 1
+#define PLUGIN_EXTENSION_ADMIN_GROUP_LBN 128
+#define PLUGIN_EXTENSION_ADMIN_GROUP_WIDTH 8
+#define PLUGIN_EXTENSION_FLAG_ENABLED_LBN 136
+#define PLUGIN_EXTENSION_FLAG_ENABLED_WIDTH 1
+#define PLUGIN_EXTENSION_RESERVED_LBN 137
+#define PLUGIN_EXTENSION_RESERVED_WIDTH 23
+
+/* DESC_ADDR_REGION structuredef: Describes a contiguous region of DESC_ADDR
+ * space that maps to a contiguous region of TRGT_ADDR space. Addresses
+ * DESC_ADDR in the range [DESC_ADDR_BASE:DESC_ADDR_BASE + 1 <<
+ * WINDOW_SIZE_LOG2) map to TRGT_ADDR = DESC_ADDR - DESC_ADDR_BASE +
+ * TRGT_ADDR_BASE.
+ */
+#define DESC_ADDR_REGION_LEN 32
+/* The start of the region in DESC_ADDR space. */
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_OFST 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LEN 8
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_OFST 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LEN 4
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LBN 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_WIDTH 32
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_OFST 4
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LEN 4
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LBN 32
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_WIDTH 32
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_LBN 0
+#define DESC_ADDR_REGION_DESC_ADDR_BASE_WIDTH 64
+/* The start of the region in TRGT_ADDR space. Drivers can set this via
+ * MC_CMD_SET_DESC_ADDR_REGIONS.
+ */
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_OFST 8
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LEN 8
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_OFST 8
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LEN 4
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LBN 64
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_WIDTH 32
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_OFST 12
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LEN 4
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LBN 96
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_WIDTH 32
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_LBN 64
+#define DESC_ADDR_REGION_TRGT_ADDR_BASE_WIDTH 64
+/* The size of the region. */
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_OFST 16
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LEN 4
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LBN 128
+#define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_WIDTH 32
+/* The alignment restriction on TRGT_ADDR. TRGT_ADDR values set by the driver
+ * must be a multiple of 1 << TRGT_ADDR_ALIGN_LOG2.
+ */
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_OFST 20
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LEN 4
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LBN 160
+#define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_WIDTH 32
+#define DESC_ADDR_REGION_RSVD_OFST 24
+#define DESC_ADDR_REGION_RSVD_LEN 8
+#define DESC_ADDR_REGION_RSVD_LO_OFST 24
+#define DESC_ADDR_REGION_RSVD_LO_LEN 4
+#define DESC_ADDR_REGION_RSVD_LO_LBN 192
+#define DESC_ADDR_REGION_RSVD_LO_WIDTH 32
+#define DESC_ADDR_REGION_RSVD_HI_OFST 28
+#define DESC_ADDR_REGION_RSVD_HI_LEN 4
+#define DESC_ADDR_REGION_RSVD_HI_LBN 224
+#define DESC_ADDR_REGION_RSVD_HI_WIDTH 32
+#define DESC_ADDR_REGION_RSVD_LBN 192
+#define DESC_ADDR_REGION_RSVD_WIDTH 64
+
+
+/***********************************/
+/* MC_CMD_GET_DESC_ADDR_INFO
+ * Returns a description of the mapping from DESC_ADDR to TRGT_ADDR for the calling function's address space.
+ */
+#define MC_CMD_GET_DESC_ADDR_INFO 0x1b7
+#define MC_CMD_GET_DESC_ADDR_INFO_MSGSET 0x1b7
+#undef MC_CMD_0x1b7_PRIVILEGE_CTG
+
+#define MC_CMD_0x1b7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_DESC_ADDR_INFO_IN msgrequest */
+#define MC_CMD_GET_DESC_ADDR_INFO_IN_LEN 0
+
+/* MC_CMD_GET_DESC_ADDR_INFO_OUT msgresponse */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_LEN 4
+/* The type of mapping; see SF-nnnnnn-xx (EF100 driver writer's guide, once
+ * written) for details of each type.
+ */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_OFST 0
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_LEN 4
+/* enum: TRGT_ADDR = DESC_ADDR */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT 0x0
+/* enum: DESC_ADDR has one or more regions that map into TRGT_ADDR. The base
+ * TRGT_ADDR for each region is programmable via MCDI.
+ */
+#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED 0x1
+
+
+/***********************************/
+/* MC_CMD_GET_DESC_ADDR_REGIONS
+ * Returns a list of the DESC_ADDR regions for the calling function's address space. Only valid if that function's address space has the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
+ */
+#define MC_CMD_GET_DESC_ADDR_REGIONS 0x1b8
+#define MC_CMD_GET_DESC_ADDR_REGIONS_MSGSET 0x1b8
+#undef MC_CMD_0x1b8_PRIVILEGE_CTG
+
+#define MC_CMD_0x1b8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_DESC_ADDR_REGIONS_IN msgrequest */
+#define MC_CMD_GET_DESC_ADDR_REGIONS_IN_LEN 0
+
+/* MC_CMD_GET_DESC_ADDR_REGIONS_OUT msgresponse */
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMIN 32
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX 224
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX_MCDI2 992
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LEN(num) (0+32*(num))
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)
+/* An array of DESC_ADDR_REGION strutures. The number of entries in the array
+ * indicates the number of available regions.
+ */
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_OFST 0
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_LEN 32
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MINNUM 1
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM 7
+#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM_MCDI2 31
+
+
+/***********************************/
+/* MC_CMD_SET_DESC_ADDR_REGIONS
+ * Set the base TRGT_ADDR for a set of DESC_ADDR regions for the calling function's address space. Only valid if that function's address space had the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
+ */
+#define MC_CMD_SET_DESC_ADDR_REGIONS 0x1b9
+#define MC_CMD_SET_DESC_ADDR_REGIONS_MSGSET 0x1b9
+#undef MC_CMD_0x1b9_PRIVILEGE_CTG
+
+#define MC_CMD_0x1b9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_DESC_ADDR_REGIONS_IN msgrequest */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMIN 16
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX 248
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX_MCDI2 1016
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LEN(num) (8+8*(num))
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_NUM(len) (((len)-8)/8)
+/* A bitmask indicating which regions should have their base TRGT_ADDR updated.
+ * To update the base TRGR_ADDR for a DESC_ADDR region, the corresponding bit
+ * should be set to 1.
+ */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_OFST 0
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_LEN 4
+/* Reserved field; must be set to zero. */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_OFST 4
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_LEN 4
+/* An array of values used to updated the base TRGT_ADDR for DESC_ADDR regions.
+ * Array indices corresponding to region numbers (i.e. the array is sparse, and
+ * included entries for regions even if the corresponding SET_REGION_MASK bit
+ * is zero).
*/
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI 0x2
-/* enum: First field refers to function-relative VI number on a specified
- * function
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI_PROXY 0x3
-/* Type of VI. Not needed if ADDRESS_MODE is QUEUE_NUMBER. */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_OFST 8
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_LEN 4
-/* enum: Return only entries used for ef100 queues (a single hardware queue) */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_EF100 0x0
-/* enum: Return entries used for virtio (Potentially two hardware queues,
- * depending on hardware implementation)
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VIRTIO 0x1
-/* Only if ADDRESS_MODE is REL_VI_PROXY. Interface of function the queue is on.
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_OFST 8
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LEN 8
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_OFST 8
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LEN 4
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LBN 64
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_WIDTH 32
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_OFST 12
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LEN 4
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LBN 96
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_WIDTH 32
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MINNUM 1
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM 30
+#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM_MCDI2 126
+
+/* MC_CMD_SET_DESC_ADDR_REGIONS_OUT msgresponse */
+#define MC_CMD_SET_DESC_ADDR_REGIONS_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_CLIENT_CMD
+ * Execute an arbitrary MCDI command on behalf of a different client. The
+ * consequences of the command (e.g. ownership of any resources created) apply
+ * to the indicated client rather than the function client which actually sent
+ * this command. All inherent permission checks are also performed on the
+ * indicated client. The given client must be a descendant of the requestor.
+ * The command to be proxied follows immediately afterward in the host buffer
+ * (or on the UART). Chaining multiple MC_CMD_CLIENT_CMD is unnecessary and not
+ * supported. New dynamic clients may be created with MC_CMD_CLIENT_ALLOC.
*/
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_OFST 12
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_LEN 4
-/* Enum values, see field(s): */
-/* DEVEL_PCIE_INTERFACE */
-/* Only if ADDRESS_MODE is REL_VI_PROXY. PF number of the function the queue is
- * on.
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PF_OFST 16
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_PF_LEN 2
-/* Only if ADDRESS_MODE is REL_VI_PROXY. VF number of the function the queue is
- * on.
- */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VF_OFST 18
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VF_LEN 2
-/* enum: The function is on a PF, not a VF. */
-#define MC_CMD_DEVEL_DUMP_VI_IN_V2_VF_NULL 0xffff
-
-/* MC_CMD_DEVEL_DUMP_VI_OUT msgresponse */
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LENMIN 4
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LENMAX 252
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LENMAX_MCDI2 1012
-#define MC_CMD_DEVEL_DUMP_VI_OUT_LEN(num) (0+1*(num))
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_NUM(len) (((len)-0)/1)
-/* Number of dump entries returned */
-#define MC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_LEN 4
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_OFST 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_LBN 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_WIDTH 8
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_MINNUM 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM 252
-#define MC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM_MCDI2 1020
-/* Array of MC_CMD_DEVEL_DUMP_VI_ENTRY structures of length NUM_ENTRIES */
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_OFST 4
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_LEN 28
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MINNUM 0
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM 8
-#define MC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM_MCDI2 36
-
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structuredef */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_LEN 16
-/* What register this is */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_OFST 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LEN 4
-/* enum: Catchall for registers that aren't in this enum. Nothing should be in
- * this long-term
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_UNKNOWN 0xffffffff
-/* enum: S2IC Converter Debug Packet Counter register. Informs number of
- * packets passed through Converter.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_H2C_S2IC_DBG_PKT_CNT 0x0
-/* enum: IC2S Converter Debug Packet Counter register. Informs number of
- * packets passed through Converter.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_C2H_IC2S_DBG_PKT_CNT 0x1
-/* enum: Event Controller Tx path Debug register. Count of Moderator Tx events,
- * not incl D2C, VirtIO, Dproxy.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DEBUG 0x2
-/* enum: Event Controller Rx path Debug register. Count of Moderator Rx events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_DEBUG 0x3
-/* enum: Event Controller Debug register. Count of Total EVC events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TOTAL_DEBUG 0x4
-/* enum: Same info as EVC_RX_DEBUG; collected at different location in design
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EF100_DEBUG 0x5
-/* enum: Same info as EVC_TX_DEBUG; collected at different location in design
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_EF100_DEBUG 0x6
-/* enum: Event Controller Debug register. Count of Tx VirtIO events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTIO_DEBUG 0x7
-/* enum: Event Controller Debug register. Count of Tx Descriptor Proxy events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DPRXY_DEBUG 0x8
-/* enum: Event Controller Debug register. Count of Tx VirtQ Descriptor Proxy
- * events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_DPRXY_DEBUG 0x9
-/* enum: Event Controller Debug register. Count of Tx Descriptor-to-Completion
- * events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_D2C_DEBUG 0xa
-/* enum: Event Controller Debug register. Count of Tx VirtIO Descriptor-to-
- * Completion events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_D2C_DEBUG 0xb
-/* enum: Event Controller Debug register. Count of Tx Timestamp events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_TSTAMP_DEBUG 0xc
-/* enum: Event Controller Debug register. Count of Rx EvQ Timeout events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EVQ_TIMEOUT_DEBUG 0xd
-/* enum: Event Controller Debug register. Count of MC events. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_MC_DEBUG 0xe
-/* enum: Event Controller Debug register. Count of EQDMA VirtIO Control events.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_EQDMA_VIO_CTL_DEBUG 0xf
-/* enum: Counter of QDMA Dropped C2H packets. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_DMAC_C2H_DROP_CTR_REG 0x10
-/* enum: Number of packets received by c host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_IN_TBL 0x11
-/* enum: Number of packets sent by c host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_OUT_TBL 0x12
-/* enum: Number of packets received by c plugin fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_P_PACKETS_IN_TBL 0x13
-/* enum: Number of packets received by b host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_H_PACKETS_IN_TBL 0x14
-/* enum: Number of packets received by b net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_N_PACKETS_IN_TBL 0x15
-/* enum: Number of packets received by b host fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PH_PACKETS_IN_TBL 0x16
-/* enum: Number of packets received by b net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PN_PACKETS_IN_TBL 0x17
-/* enum: Number of packets sent by b net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PACKETS_OUT_TBL 0x18
-/* enum: Number of packets received by c net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_IN_TBL 0x19
-/* enum: Number of packets sent by c net fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_OUT_TBL 0x1a
-/* enum: Number of packets received by ha fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_IN_TBL 0x1b
-/* enum: Number of packets received by ha host shadow fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PH_PACKETS_IN_TBL 0x1c
-/* enum: Number of packets received by ha fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_OUT_TBL 0x1d
-/* enum: Number of packets received by d hub fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_IN_TBL 0x1e
-/* enum: Number of packets received by d hub plugin fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_P_PACKETS_IN_TBL 0x1f
-/* enum: Number of packets received by d hub plugin fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_O_PACKETS_IN_TBL 0x20
-/* enum: Number of packets sent to dmac. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_OUT_TBL 0x21
-/* enum: Number of packets received by na fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_IN_TBL 0x22
-/* enum: Number of packets dropped by na fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_DROPPED_TBL 0x23
-/* enum: Number of packets sent by na fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_OUT_TBL 0x24
-/* enum: Number of packets received by rp hub fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_IN_TBL 0x25
-/* enum: Number of packets removed from fifo. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_OUT_TBL 0x26
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LBN 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_WIDTH 32
-/* If REG is a table, the table row. */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_OFST 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LEN 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LBN 32
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_WIDTH 32
-/* Address of the register (as seen by the MC) */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_OFST 8
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LEN 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LBN 64
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_WIDTH 32
-/* Value of the register */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_OFST 12
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LEN 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LBN 96
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_WIDTH 32
-
-
-/***********************************/
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS
- * Dump an assortment of hopefully useful riverhead debug registers
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS 0x1b6
-#undef MC_CMD_0x1b6_PRIVILEGE_CTG
-
-#define MC_CMD_0x1b6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
-
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN msgrequest */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_LEN 4
-/* Which page of registers to retrieve. Page 0 always exists, later pages may
- * also exist if there are too many registers to fit in a single mcdi response.
- * NUM_PAGES in the response will tell you how many there are.
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_OFST 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_LEN 4
-
-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT msgresponse */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMIN 8
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX 248
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX_MCDI2 1016
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LEN(num) (8+16*(num))
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_NUM(len) (((len)-8)/16)
-/* Number of registers dumped in this response */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_OFST 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_LEN 4
-/* How many pages of registers are available to extract */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_OFST 4
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_LEN 4
-/* Array of MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structs, one for each register
- */
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_OFST 8
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_LEN 16
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MINNUM 0
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM 15
-#define MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM_MCDI2 63
+#define MC_CMD_CLIENT_CMD 0x1ba
+#define MC_CMD_CLIENT_CMD_MSGSET 0x1ba
+#undef MC_CMD_0x1ba_PRIVILEGE_CTG
+
+#define MC_CMD_0x1ba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CLIENT_CMD_IN msgrequest */
+#define MC_CMD_CLIENT_CMD_IN_LEN 4
+/* The client as which to execute the following command. */
+#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_OFST 0
+#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_LEN 4
+
+/* MC_CMD_CLIENT_CMD_OUT msgresponse */
+#define MC_CMD_CLIENT_CMD_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_CLIENT_ALLOC
+ * Create a new client object. Clients are a system for delineating NIC
+ * resource ownership, such that groups of resources may be torn down as a
+ * unit. See also MC_CMD_CLIENT_CMD. See XN-200265-TC for background, concepts
+ * and a glossary. Clients created by this command are known as "dynamic
+ * clients". The newly-created client is a child of the client which sent this
+ * command. The caller must have the GRP_ALLOC_CLIENT privilege. The new client
+ * initially has no permission to do anything; see
+ * MC_CMD_DEVEL_CLIENT_PRIVILEGE_MODIFY.
+ */
+#define MC_CMD_CLIENT_ALLOC 0x1bb
+#define MC_CMD_CLIENT_ALLOC_MSGSET 0x1bb
+#undef MC_CMD_0x1bb_PRIVILEGE_CTG
+
+#define MC_CMD_0x1bb_PRIVILEGE_CTG SRIOV_CTG_ALLOC_CLIENT
+
+/* MC_CMD_CLIENT_ALLOC_IN msgrequest */
+#define MC_CMD_CLIENT_ALLOC_IN_LEN 0
+
+/* MC_CMD_CLIENT_ALLOC_OUT msgresponse */
+#define MC_CMD_CLIENT_ALLOC_OUT_LEN 4
+/* The ID of the new client object which has been created. */
+#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_OFST 0
+#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_LEN 4
+
+
+/***********************************/
+/* MC_CMD_CLIENT_FREE
+ * Destroy and release an existing client object. All resources owned by that
+ * client (including its child clients, and thus all resources owned by the
+ * entire family tree) are freed.
+ */
+#define MC_CMD_CLIENT_FREE 0x1bc
+#define MC_CMD_CLIENT_FREE_MSGSET 0x1bc
+#undef MC_CMD_0x1bc_PRIVILEGE_CTG
+
+#define MC_CMD_0x1bc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_CLIENT_FREE_IN msgrequest */
+#define MC_CMD_CLIENT_FREE_IN_LEN 4
+/* The ID of the client to be freed. This client must be a descendant of the
+ * requestor. A client cannot free itself.
+ */
+#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_OFST 0
+#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_LEN 4
+
+/* MC_CMD_CLIENT_FREE_OUT msgresponse */
+#define MC_CMD_CLIENT_FREE_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_SET_VI_USER
+ * Assign partial rights over this VI to another client. VIs have an 'owner'
+ * and a 'user'. The owner is the client which allocated the VI
+ * (MC_CMD_ALLOC_VIS) and cannot be changed. The user is the client which has
+ * permission to create queues and other resources on that VI. Initially
+ * user==owner, but the user can be changed by this command; the resources thus
+ * created are then owned by the user-client. Only the VI owner can call this
+ * command, and the request will fail if there are any outstanding child
+ * resources (e.g. queues) currently allocated from this VI.
+ */
+#define MC_CMD_SET_VI_USER 0x1be
+#define MC_CMD_SET_VI_USER_MSGSET 0x1be
+#undef MC_CMD_0x1be_PRIVILEGE_CTG
+
+#define MC_CMD_0x1be_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_VI_USER_IN msgrequest */
+#define MC_CMD_SET_VI_USER_IN_LEN 8
+/* Function-relative VI number to modify. */
+#define MC_CMD_SET_VI_USER_IN_INSTANCE_OFST 0
+#define MC_CMD_SET_VI_USER_IN_INSTANCE_LEN 4
+/* Client ID to become the new user. This must be a descendant of the owning
+ * client, the owning client itself, or the special value MC_CMD_CLIENT_ID_SELF
+ * which is synonymous with the owning client.
+ */
+#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_OFST 4
+#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_LEN 4
+
+/* MC_CMD_SET_VI_USER_OUT msgresponse */
+#define MC_CMD_SET_VI_USER_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES
+ * A device reports a set of MAC addresses for each client to use, known as the
+ * "permanent MAC addresses". Those MAC addresses are provided by the client's
+ * administrator, e.g. via MC_CMD_SET_CLIENT_MAC_ADDRESSES, and are intended as
+ * a hint to that client which MAC address its administrator would like to use
+ * to identity itself. This API exists solely to allow communication of MAC
+ * address from administrator to adminstree, and has no inherent interaction
+ * with switching within the device. There is no guarantee that a client will
+ * be able to send traffic with a source MAC address taken from the list of MAC
+ * address reported, nor is there a guarantee that a client will be able to
+ * resource traffic with a destination MAC taken from the list of MAC
+ * addresses. Likewise, there is no guarantee that a client will not be able to
+ * use a MAC address not present in the list. Restrictions on switching are
+ * controlled either through the EVB API if operating in EVB mode, or via MAE
+ * rules if host software is directly managing the MAE. In order to allow
+ * tenants to use this API whilst a provider is using the EVB API, the MAC
+ * addresses reported by MC_CMD_GET_CLIENT_MAC_ADDRESSES will be augmented with
+ * any MAC addresses associated with the vPort assigned to the caller. In order
+ * to allow tenants to use the EVB API whilst a provider is using this API, if
+ * a client queries the MAC addresses for a vPort using the host_evb_port_id
+ * EVB_PORT_ASSIGNED, that list of MAC addresses will be augmented with the MAC
+ * addresses assigned to the calling client. This query can either be explicit
+ * (i.e. MC_CMD_VPORT_GET_MAC_ADDRESSES) or implicit (e.g. creation of a
+ * vAdaptor with a NULL/automatic MAC address). Changing the MAC address on a
+ * vAdaptor only affects VNIC steering filters; it has no effect on the MAC
+ * addresses assigned to the vAdaptor's owner. VirtIO clients behave as EVB
+ * clients. On VirtIO device reset, a vAdaptor is created with an automatic MAC
+ * address. Querying the VirtIO device's MAC address queries the underlying
+ * vAdaptor's MAC address. Setting the VirtIO device's MAC address sets the
+ * underlying vAdaptor's MAC addresses.
+ */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES 0x1c4
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_MSGSET 0x1c4
+#undef MC_CMD_0x1c4_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN msgrequest */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN 4
+/* A handle for the client for whom MAC address should be obtained. Use
+ * CLIENT_HANDLE_SELF to obtain the MAC addresses assigned to the calling
+ * client.
+ */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
+
+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMIN 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX 252
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(num) (0+6*(num))
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)
+/* An array of MAC addresses assigned to the client. */
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_OFST 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_LEN 6
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MINNUM 0
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM 42
+#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM_MCDI2 170
+
+
+/***********************************/
+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES
+ * Set the permanent MAC addresses for a client. The caller must by an
+ * administrator of the target client. See MC_CMD_GET_CLIENT_MAC_ADDRESSES for
+ * additional detail.
+ */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES 0x1c5
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_MSGSET 0x1c5
+#undef MC_CMD_0x1c5_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN msgrequest */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMIN 4
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX 250
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX_MCDI2 1018
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LEN(num) (4+6*(num))
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_NUM(len) (((len)-4)/6)
+/* A handle for the client for whom MAC addresses should be set */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
+/* An array of MAC addresses to assign to the client. */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_OFST 4
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_LEN 6
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MINNUM 0
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM 41
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM_MCDI2 169
+
+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
+#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT_LEN 0
+
+
+/***********************************/
+/* MC_CMD_GET_BOARD_ATTR
+ * Retrieve physical build-level board attributes as configured at
+ * manufacturing stage. Fields originate from EEPROM and per-platform constants
+ * in firmware. Fields are used in development to identify/ differentiate
+ * boards based on build levels/parameters, and also in manufacturing to cross
+ * check "what was programmed in manufacturing" is same as "what firmware
+ * thinks has been programmed" as there are two layers to translation within
+ * firmware before the attributes reach this MCDI handler. Some parameters are
+ * retrieved as part of other commands and therefore not replicated here. See
+ * GET_VERSION_OUT.
+ */
+#define MC_CMD_GET_BOARD_ATTR 0x1c6
+#define MC_CMD_GET_BOARD_ATTR_MSGSET 0x1c6
+#undef MC_CMD_0x1c6_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_BOARD_ATTR_IN msgrequest */
+#define MC_CMD_GET_BOARD_ATTR_IN_LEN 0
+
+/* MC_CMD_GET_BOARD_ATTR_OUT msgresponse */
+#define MC_CMD_GET_BOARD_ATTR_OUT_LEN 16
+/* Defines board capabilities and validity of attributes returned in this
+ * response-message.
+ */
+#define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_LBN 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_LBN 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_OFST 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_LBN 2
+#define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_LEN 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_LBN 0
+#define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_LBN 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_WIDTH 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_LBN 16
+#define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_WIDTH 8
+/* enum: The FPGA voltage on the adapter can be set to low */
+#define MC_CMD_FPGA_VOLTAGE_LOW 0x0
+/* enum: The FPGA voltage on the adapter can be set to regular */
+#define MC_CMD_FPGA_VOLTAGE_REG 0x1
+/* enum: The FPGA voltage on the adapter can be set to high */
+#define MC_CMD_FPGA_VOLTAGE_HIGH 0x2
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_OFST 4
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_LBN 24
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_WIDTH 8
+/* An array of cage types on the board */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_OFST 8
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_LEN 1
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_NUM 8
+/* enum: The cages are not known */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_UNKNOWN 0x0
+/* enum: The cages are SFP/SFP+ */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_SFP 0x1
+/* enum: The cages are QSFP/QSFP+ */
+#define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_QSFP 0x2
+
+
+/***********************************/
+/* MC_CMD_GET_SOC_STATE
+ * Retrieve current state of the System-on-Chip. This command is valid when
+ * MC_CMD_GET_BOARD_ATTR:HAS_SOC is set.
+ */
+#define MC_CMD_GET_SOC_STATE 0x1c7
+#define MC_CMD_GET_SOC_STATE_MSGSET 0x1c7
+#undef MC_CMD_0x1c7_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_SOC_STATE_IN msgrequest */
+#define MC_CMD_GET_SOC_STATE_IN_LEN 0
+
+/* MC_CMD_GET_SOC_STATE_OUT msgresponse */
+#define MC_CMD_GET_SOC_STATE_OUT_LEN 12
+/* Status flags for the SoC */
+#define MC_CMD_GET_SOC_STATE_OUT_FLAGS_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_FLAGS_LEN 4
+#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_LBN 0
+#define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_WIDTH 1
+#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_LBN 1
+#define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_WIDTH 1
+#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_OFST 0
+#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_LBN 2
+#define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_WIDTH 1
+/* Status fields for the SoC */
+#define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_OFST 4
+#define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_LEN 4
+#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_OFST 4
+#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_LBN 0
+#define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_WIDTH 8
+/* enum: Power on (set by SUC on power up) */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOT 0x0
+/* enum: Running bootloader */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOTLOADER 0x1
+/* enum: Bootloader has started OS. OS is booting */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_START 0x2
+/* enum: OS is running */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_RUNNING 0x3
+/* enum: Maintenance OS is running */
+#define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_MAINTENANCE 0x4
+/* Number of SoC resets since power on */
+#define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_OFST 8
+#define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_LEN 4
+
+
+/***********************************/
+/* MC_CMD_CHECK_SCHEDULER_CREDITS
+ * For debugging purposes. For each source and destination node in the hardware
+ * schedulers, check whether the number of credits is as it should be. This
+ * should only be used when the NIC is idle, because collection is not atomic
+ * and because the expected credit counts are only meaningful when no traffic
+ * is flowing.
+ */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS 0x1c8
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_MSGSET 0x1c8
+#undef MC_CMD_0x1c8_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
+
+/* MC_CMD_CHECK_SCHEDULER_CREDITS_IN msgrequest */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_LEN 8
+/* Flags for the request */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_OFST 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_LEN 4
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_OFST 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_LBN 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_WIDTH 1
+/* If there are too many results to fit into an MCDI response, they're split
+ * into pages. This field specifies which (0-indexed) page to request. A
+ * request with PAGE=0 will snapshot the results, and subsequent requests with
+ * PAGE>0 will return data from the most recent snapshot. The GENERATION field
+ * in the response allows callers to verify that all responses correspond to
+ * the same snapshot.
+ */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_OFST 4
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_LEN 4
+
+/* MC_CMD_CHECK_SCHEDULER_CREDITS_OUT msgresponse */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMIN 16
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX 240
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX_MCDI2 1008
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LEN(num) (16+16*(num))
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_NUM(len) (((len)-16)/16)
+/* The total number of results (across all pages). */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_OFST 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_LEN 4
+/* The number of pages that the response is split across. */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_OFST 4
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_LEN 4
+/* The number of results in this response. */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_OFST 8
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_LEN 4
+/* Result generation count. Incremented any time a request is made with PAGE=0.
+ */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_OFST 12
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_LEN 4
+/* The results, as an array of SCHED_CREDIT_CHECK_RESULT structures. */
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_OFST 16
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_LEN 16
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM 14
+#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM_MCDI2 62
/* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are
* defined in SF-120734-TC with more information in SF-122717-TC.
@@ -24839,6 +27140,7 @@
* Get a list of the virtio features supported by the device.
*/
#define MC_CMD_VIRTIO_GET_FEATURES 0x168
+#define MC_CMD_VIRTIO_GET_FEATURES_MSGSET 0x168
#undef MC_CMD_0x168_PRIVILEGE_CTG
#define MC_CMD_0x168_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24867,7 +27169,13 @@
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LEN 8
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LEN 4
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LBN 0
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_WIDTH 32
#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LEN 4
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LBN 32
+#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_WIDTH 32
/***********************************/
@@ -24877,6 +27185,7 @@
* the driver fails to request a feature which the device requires.
*/
#define MC_CMD_VIRTIO_TEST_FEATURES 0x169
+#define MC_CMD_VIRTIO_TEST_FEATURES_MSGSET 0x169
#undef MC_CMD_0x169_PRIVILEGE_CTG
#define MC_CMD_0x169_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24898,7 +27207,13 @@
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_OFST 8
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LEN 8
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_OFST 8
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LEN 4
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LBN 64
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_WIDTH 32
#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_OFST 12
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LEN 4
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LBN 96
+#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_WIDTH 32
/* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */
#define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0
@@ -24912,6 +27227,7 @@
* invalid.
*/
#define MC_CMD_VIRTIO_INIT_QUEUE 0x16a
+#define MC_CMD_VIRTIO_INIT_QUEUE_MSGSET 0x16a
#undef MC_CMD_0x16a_PRIVILEGE_CTG
#define MC_CMD_0x16a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -24956,17 +27272,35 @@
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_OFST 16
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_OFST 16
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LBN 128
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_OFST 20
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LBN 160
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_WIDTH 32
/* Address of the available ring in the virtqueue. */
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_OFST 24
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_OFST 24
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LBN 192
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_OFST 28
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LBN 224
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_WIDTH 32
/* Address of the used ring in the virtqueue. */
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_OFST 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_OFST 32
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LBN 256
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_OFST 36
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LBN 288
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_WIDTH 32
/* PASID to use on PCIe transactions involving this queue. Ignored if the
* USE_PASID flag is not set.
*/
@@ -24990,7 +27324,13 @@
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_OFST 48
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LEN 8
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_OFST 48
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LBN 384
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_WIDTH 32
#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_OFST 52
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LEN 4
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LBN 416
+#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_WIDTH 32
/* Enum values, see field(s): */
/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_OUT/FEATURES */
/* The initial producer index for this queue's used ring. If this queue is
@@ -25023,6 +27363,7 @@
* Destroy a virtio virtqueue
*/
#define MC_CMD_VIRTIO_FINI_QUEUE 0x16b
+#define MC_CMD_VIRTIO_FINI_QUEUE_MSGSET 0x16b
#undef MC_CMD_0x16b_PRIVILEGE_CTG
#define MC_CMD_0x16b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -25063,6 +27404,7 @@
* queue(s) to be allocated.
*/
#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c
+#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_MSGSET 0x16c
#undef MC_CMD_0x16c_PRIVILEGE_CTG
#define MC_CMD_0x16c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -25132,12 +27474,18 @@
#define PCIE_FUNCTION_VF_NULL 0xffff
#define PCIE_FUNCTION_VF_LBN 16
#define PCIE_FUNCTION_VF_WIDTH 16
-/* PCIe interface of the function */
+/* PCIe interface of the function. Values should be taken from the
+ * PCIE_INTERFACE enum
+ */
#define PCIE_FUNCTION_INTF_OFST 4
#define PCIE_FUNCTION_INTF_LEN 4
-/* enum: Host PCIe interface */
+/* enum: Host PCIe interface. (Alias for HOST_PRIMARY, provided for backwards
+ * compatibility)
+ */
#define PCIE_FUNCTION_INTF_HOST 0x0
-/* enum: Application Processor interface */
+/* enum: Application Processor interface (alias for NIC_EMBEDDED, provided for
+ * backwards compatibility)
+ */
#define PCIE_FUNCTION_INTF_AP 0x1
#define PCIE_FUNCTION_INTF_LBN 32
#define PCIE_FUNCTION_INTF_WIDTH 32
@@ -25157,6 +27505,7 @@
* MC_CMD_DESC_PROXY_FUNC_COMMIT_IN.
*/
#define MC_CMD_DESC_PROXY_FUNC_CREATE 0x172
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_MSGSET 0x172
#undef MC_CMD_0x172_PRIVILEGE_CTG
#define MC_CMD_0x172_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25170,7 +27519,19 @@
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LEN 8
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LBN 0
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_WIDTH 32
#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LBN 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_WIDTH 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_OFST 0
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_OFST 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_LEN 4
/* The personality to set. The meanings of the personalities are defined in
* SF-120734-TC with more information in SF-122717-TC. At present, we only
* support proxying for VIRTIO_BLK
@@ -25194,7 +27555,19 @@
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LEN 8
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LBN 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_WIDTH 32
#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LBN 64
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_WIDTH 32
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_OFST 6
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_LEN 4
/***********************************/
@@ -25205,6 +27578,7 @@
* ownership is released.
*/
#define MC_CMD_DESC_PROXY_FUNC_DESTROY 0x173
+#define MC_CMD_DESC_PROXY_FUNC_DESTROY_MSGSET 0x173
#undef MC_CMD_0x173_PRIVILEGE_CTG
#define MC_CMD_0x173_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25235,7 +27609,13 @@
#define VIRTIO_BLK_CONFIG_FEATURES_OFST 0
#define VIRTIO_BLK_CONFIG_FEATURES_LEN 8
#define VIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0
+#define VIRTIO_BLK_CONFIG_FEATURES_LO_LEN 4
+#define VIRTIO_BLK_CONFIG_FEATURES_LO_LBN 0
+#define VIRTIO_BLK_CONFIG_FEATURES_LO_WIDTH 32
#define VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4
+#define VIRTIO_BLK_CONFIG_FEATURES_HI_LEN 4
+#define VIRTIO_BLK_CONFIG_FEATURES_HI_LBN 32
+#define VIRTIO_BLK_CONFIG_FEATURES_HI_WIDTH 32
#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0
#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0
#define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1
@@ -25308,7 +27688,13 @@
#define VIRTIO_BLK_CONFIG_CAPACITY_OFST 8
#define VIRTIO_BLK_CONFIG_CAPACITY_LEN 8
#define VIRTIO_BLK_CONFIG_CAPACITY_LO_OFST 8
+#define VIRTIO_BLK_CONFIG_CAPACITY_LO_LEN 4
+#define VIRTIO_BLK_CONFIG_CAPACITY_LO_LBN 64
+#define VIRTIO_BLK_CONFIG_CAPACITY_LO_WIDTH 32
#define VIRTIO_BLK_CONFIG_CAPACITY_HI_OFST 12
+#define VIRTIO_BLK_CONFIG_CAPACITY_HI_LEN 4
+#define VIRTIO_BLK_CONFIG_CAPACITY_HI_LBN 96
+#define VIRTIO_BLK_CONFIG_CAPACITY_HI_WIDTH 32
#define VIRTIO_BLK_CONFIG_CAPACITY_LBN 64
#define VIRTIO_BLK_CONFIG_CAPACITY_WIDTH 64
/* Maximum size of any single segment. Only valid when VIRTIO_BLK_F_SIZE_MAX is
@@ -25445,6 +27831,7 @@
* not persisted until the caller commits with MC_CMD_DESC_PROXY_FUNC_COMMIT_IN
*/
#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174
+#define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_MSGSET 0x174
#undef MC_CMD_0x174_PRIVILEGE_CTG
#define MC_CMD_0x174_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25485,6 +27872,7 @@
* delivered to callers MCDI event queue.
*/
#define MC_CMD_DESC_PROXY_FUNC_COMMIT 0x175
+#define MC_CMD_DESC_PROXY_FUNC_COMMIT_MSGSET 0x175
#undef MC_CMD_0x175_PRIVILEGE_CTG
#define MC_CMD_0x175_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25518,6 +27906,7 @@
* cycle. Returns ENODEV if no function with given label exists.
*/
#define MC_CMD_DESC_PROXY_FUNC_OPEN 0x176
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_MSGSET 0x176
#undef MC_CMD_0x176_PRIVILEGE_CTG
#define MC_CMD_0x176_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25543,7 +27932,19 @@
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LEN 8
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LBN 32
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_WIDTH 32
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LEN 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LBN 64
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_WIDTH 32
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_OFST 4
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_OFST 6
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_LEN 2
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_OFST 8
+#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_LEN 4
/* Function personality */
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_OFST 12
#define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4
@@ -25588,6 +27989,7 @@
* error (for virtio, DEVICE_NEEDS_RESET flag would be set on the host side)
*/
#define MC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1
+#define MC_CMD_DESC_PROXY_FUNC_CLOSE_MSGSET 0x1a1
#undef MC_CMD_0x1a1_PRIVILEGE_CTG
#define MC_CMD_0x1a1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25607,9 +28009,27 @@
#define DESC_PROXY_FUNC_MAP_FUNC_OFST 0
#define DESC_PROXY_FUNC_MAP_FUNC_LEN 8
#define DESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0
+#define DESC_PROXY_FUNC_MAP_FUNC_LO_LEN 4
+#define DESC_PROXY_FUNC_MAP_FUNC_LO_LBN 0
+#define DESC_PROXY_FUNC_MAP_FUNC_LO_WIDTH 32
#define DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4
+#define DESC_PROXY_FUNC_MAP_FUNC_HI_LEN 4
+#define DESC_PROXY_FUNC_MAP_FUNC_HI_LBN 32
+#define DESC_PROXY_FUNC_MAP_FUNC_HI_WIDTH 32
#define DESC_PROXY_FUNC_MAP_FUNC_LBN 0
#define DESC_PROXY_FUNC_MAP_FUNC_WIDTH 64
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_OFST 0
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_LEN 2
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_LBN 0
+#define DESC_PROXY_FUNC_MAP_FUNC_PF_WIDTH 16
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_OFST 2
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_LEN 2
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_LBN 16
+#define DESC_PROXY_FUNC_MAP_FUNC_VF_WIDTH 16
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_OFST 4
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_LEN 4
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_LBN 32
+#define DESC_PROXY_FUNC_MAP_FUNC_INTF_WIDTH 32
/* Function personality */
#define DESC_PROXY_FUNC_MAP_PERSONALITY_OFST 8
#define DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4
@@ -25631,6 +28051,7 @@
* Enumerate existing descriptor proxy functions
*/
#define MC_CMD_DESC_PROXY_FUNC_ENUM 0x177
+#define MC_CMD_DESC_PROXY_FUNC_ENUM_MSGSET 0x177
#undef MC_CMD_0x177_PRIVILEGE_CTG
#define MC_CMD_0x177_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25670,6 +28091,7 @@
* function.
*/
#define MC_CMD_DESC_PROXY_FUNC_ENABLE 0x178
+#define MC_CMD_DESC_PROXY_FUNC_ENABLE_MSGSET 0x178
#undef MC_CMD_0x178_PRIVILEGE_CTG
#define MC_CMD_0x178_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25702,6 +28124,7 @@
* Disable descriptor proxying for function
*/
#define MC_CMD_DESC_PROXY_FUNC_DISABLE 0x179
+#define MC_CMD_DESC_PROXY_FUNC_DISABLE_MSGSET 0x179
#undef MC_CMD_0x179_PRIVILEGE_CTG
#define MC_CMD_0x179_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25725,6 +28148,7 @@
* descriptors.
*/
#define MC_CMD_GET_ADDR_SPC_ID 0x1a0
+#define MC_CMD_GET_ADDR_SPC_ID_MSGSET 0x1a0
#undef MC_CMD_0x1a0_PRIVILEGE_CTG
#define MC_CMD_0x1a0_PRIVILEGE_CTG SRIOV_CTG_ADMIN
@@ -25769,7 +28193,19 @@
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LEN 8
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LBN 32
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_WIDTH 32
#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_OFST 8
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LBN 64
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_WIDTH 32
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_OFST 4
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_LEN 2
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_OFST 6
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_LEN 2
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_OFST 8
+#define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_LEN 4
/* PASID value. Only valid if TYPE is PCI_FUNC_PASID. */
#define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_OFST 12
#define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4
@@ -25789,7 +28225,72 @@
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LEN 8
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LBN 0
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_WIDTH 32
#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LEN 4
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LBN 32
+#define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_WIDTH 32
+
+
+/***********************************/
+/* MC_CMD_GET_CLIENT_HANDLE
+ * Obtain a handle for a client given a description of that client. N.B. this
+ * command is subject to change given the open discussion about how PCIe
+ * functions should be referenced on an iEP (integrated endpoint: functions
+ * span multiple buses) and multihost (multiple PCIe interfaces) system.
+ */
+#define MC_CMD_GET_CLIENT_HANDLE 0x1c3
+#define MC_CMD_GET_CLIENT_HANDLE_MSGSET 0x1c3
+#undef MC_CMD_0x1c3_PRIVILEGE_CTG
+
+#define MC_CMD_0x1c3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+
+/* MC_CMD_GET_CLIENT_HANDLE_IN msgrequest */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_LEN 12
+/* Type of client to get a client handle for */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_OFST 0
+#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_LEN 4
+/* enum: Obtain a client handle for a PCIe function-type client. */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC 0x0
+/* PCIe Function ID (as struct PCIE_FUNCTION). Valid when TYPE==FUNC. Use: -
+ * INTF=CALLER, PF=PF_NULL, VF=VF_NULL to refer to the calling function -
+ * INTF=CALLER, PF=PF_NULL, VF=... to refer to a VF child of the calling PF or
+ * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
+ * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
+ * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF
+ * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
+ * interface where ... refers to a small integer for the VF/PF fields, and to
+ * values from the PCIE_INTERFACE enum for for the INTF field. It's only
+ * meaningful to use INTF=CALLER within a structure that's an argument to
+ * MC_CMD_DEVEL_GET_CLIENT_HANDLE.
+ */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_OFST 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LEN 8
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_OFST 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LEN 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LBN 32
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_WIDTH 32
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_OFST 8
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LEN 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LBN 64
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_WIDTH 32
+/* enum: NULL value for the INTF field of struct PCIE_FUNCTION. Provided for
+ * backwards compatibility only, callers should use PCIE_INTERFACE_CALLER.
+ */
+#define MC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_LEN 2
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_OFST 6
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_LEN 2
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_OFST 8
+#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_LEN 4
+
+/* MC_CMD_GET_CLIENT_HANDLE_OUT msgresponse */
+#define MC_CMD_GET_CLIENT_HANDLE_OUT_LEN 4
+#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_OFST 0
+#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_LEN 4
/* MAE_FIELD_FLAGS structuredef */
#define MAE_FIELD_FLAGS_LEN 4
@@ -25937,6 +28438,40 @@
#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LEN 1
#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LBN 1096
#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_LBN 0
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_LBN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_LBN 2
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LBN 1104
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_OFST 138
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LBN 1104
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_LBN 0
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_LBN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_LBN 2
+#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_WIDTH 1
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LBN 1112
+#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_WIDTH 8
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_OFST 139
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LEN 1
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LBN 1112
+#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_WIDTH 8
#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_OFST 140
#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4
#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LBN 1120
@@ -26623,9 +29158,24 @@
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_OFST 344
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_LBN 3
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_WIDTH 1
-#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_OFST 344
-#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_LBN 4
-#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_WIDTH 28
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_LBN 4
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_LBN 5
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_LBN 6
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_LBN 7
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_LBN 8
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_WIDTH 1
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_OFST 344
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_LBN 9
+#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_WIDTH 1
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LBN 2752
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_WIDTH 32
#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST 348
@@ -26707,16 +29257,34 @@
#define MAE_MPORT_SELECTOR_TYPE_WIDTH 8
/* enum: The MPORT connected to a given physical port */
#define MAE_MPORT_SELECTOR_TYPE_PPORT 0x2
-/* enum: The MPORT assigned to a given PCIe function */
+/* enum: The MPORT assigned to a given PCIe function. Deprecated in favour of
+ * MH_FUNC.
+ */
#define MAE_MPORT_SELECTOR_TYPE_FUNC 0x3
/* enum: An mport_id */
#define MAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4
+/* enum: The MPORT assigned to a given PCIe function (see also FWRIVERHD-1108)
+ */
+#define MAE_MPORT_SELECTOR_TYPE_MH_FUNC 0x5
+/* enum: This is guaranteed never to be a valid selector type */
+#define MAE_MPORT_SELECTOR_TYPE_INVALID 0xff
#define MAE_MPORT_SELECTOR_MPORT_ID_OFST 0
#define MAE_MPORT_SELECTOR_MPORT_ID_LBN 0
#define MAE_MPORT_SELECTOR_MPORT_ID_WIDTH 24
#define MAE_MPORT_SELECTOR_PPORT_ID_OFST 0
#define MAE_MPORT_SELECTOR_PPORT_ID_LBN 0
#define MAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4
+#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_OFST 0
+#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
+#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
+#define MAE_MPORT_SELECTOR_HOST_PRIMARY 0x1 /* enum */
+#define MAE_MPORT_SELECTOR_NIC_EMBEDDED 0x2 /* enum */
+/* enum: Deprecated, use CALLER_INTF instead. */
+#define MAE_MPORT_SELECTOR_CALLER 0xf
+#define MAE_MPORT_SELECTOR_CALLER_INTF 0xf /* enum */
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_OFST 0
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_LBN 16
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_WIDTH 8
@@ -26737,15 +29305,56 @@
* function.
*/
#define MAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff
+/* enum: Same as PF_ID_CALLER, but for use in the smaller MH_PF_ID field. Only
+ * valid if FUNC_INTF_ID is CALLER.
+ */
+#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_CALLER 0xf
#define MAE_MPORT_SELECTOR_FLAT_LBN 0
#define MAE_MPORT_SELECTOR_FLAT_WIDTH 32
+/* MAE_LINK_ENDPOINT_SELECTOR structuredef: Structure that identifies a real or
+ * virtual network port by MAE port and link end
+ */
+#define MAE_LINK_ENDPOINT_SELECTOR_LEN 8
+/* The MAE MPORT of interest */
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0
+#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_WIDTH 32
+/* Which end of the link identified by MPORT to consider */
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_OFST 4
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LEN 4
+/* Enum values, see field(s): */
+/* MAE_MPORT_END */
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LBN 32
+#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_WIDTH 32
+/* A field for accessing the endpoint selector as a collection of bits */
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_OFST 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LEN 8
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_OFST 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LEN 4
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LBN 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_WIDTH 32
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_OFST 4
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LEN 4
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LBN 32
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_WIDTH 32
+/* enum: Set FLAT to this value to obtain backward-compatible behaviour in
+ * commands that have been extended to take a MAE_LINK_ENDPOINT_SELECTOR
+ * argument. New commands that are designed to take such an argument from the
+ * start will not support this.
+ */
+#define MAE_LINK_ENDPOINT_SELECTOR_MAE_LINK_ENDPOINT_COMPAT 0x0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LBN 0
+#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_WIDTH 64
+
/***********************************/
/* MC_CMD_MAE_GET_CAPS
* Describes capabilities of the MAE (Match-Action Engine)
*/
#define MC_CMD_MAE_GET_CAPS 0x140
+#define MC_CMD_MAE_GET_CAPS_MSGSET 0x140
#undef MC_CMD_0x140_PRIVILEGE_CTG
#define MC_CMD_0x140_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -26772,6 +29381,9 @@
#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4
#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_LBN 2
#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
+#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_OFST 4
+#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_LBN 3
+#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
/* The total number of counters available to allocate. */
#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_OFST 8
#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4
@@ -26823,6 +29435,7 @@
* Get a level of support for match fields when used in match-action rules
*/
#define MC_CMD_MAE_GET_AR_CAPS 0x141
+#define MC_CMD_MAE_GET_AR_CAPS_MSGSET 0x141
#undef MC_CMD_0x141_PRIVILEGE_CTG
#define MC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26855,6 +29468,7 @@
* Get a level of support for fields used in outer rule keys.
*/
#define MC_CMD_MAE_GET_OR_CAPS 0x142
+#define MC_CMD_MAE_GET_OR_CAPS_MSGSET 0x142
#undef MC_CMD_0x142_PRIVILEGE_CTG
#define MC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26885,6 +29499,7 @@
* Rules.
*/
#define MC_CMD_MAE_COUNTER_ALLOC 0x143
+#define MC_CMD_MAE_COUNTER_ALLOC_MSGSET 0x143
#undef MC_CMD_0x143_PRIVILEGE_CTG
#define MC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26928,6 +29543,7 @@
* Free match-action-engine counters
*/
#define MC_CMD_MAE_COUNTER_FREE 0x144
+#define MC_CMD_MAE_COUNTER_FREE_MSGSET 0x144
#undef MC_CMD_0x144_PRIVILEGE_CTG
#define MC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -26995,6 +29611,7 @@
* delivering packets to the current queue first.
*/
#define MC_CMD_MAE_COUNTERS_STREAM_START 0x151
+#define MC_CMD_MAE_COUNTERS_STREAM_START_MSGSET 0x151
#undef MC_CMD_0x151_PRIVILEGE_CTG
#define MC_CMD_0x151_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27031,6 +29648,7 @@
* Stop streaming counter values to the specified RxQ.
*/
#define MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152
+#define MC_CMD_MAE_COUNTERS_STREAM_STOP_MSGSET 0x152
#undef MC_CMD_0x152_PRIVILEGE_CTG
#define MC_CMD_0x152_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27060,6 +29678,7 @@
* MAE_COUNTERS_PACKETISER_STREAM_START/PACKET_SIZE and rung the doorbell.
*/
#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153
+#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_MSGSET 0x153
#undef MC_CMD_0x153_PRIVILEGE_CTG
#define MC_CMD_0x153_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27076,9 +29695,15 @@
/***********************************/
/* MC_CMD_MAE_ENCAP_HEADER_ALLOC
- * Allocate encap action metadata
+ * Allocate an encapsulation header to be used in an Action Rule response. The
+ * header must be constructed as a valid packet with 0-length payload.
+ * Specifically, the L3/L4 lengths & checksums will only be incrementally fixed
+ * by the NIC, rather than recomputed entirely. Currently only IPv4, IPv6 and
+ * UDP are supported. If the maximum number of headers have already been
+ * allocated then the command will fail with MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148
+#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_MSGSET 0x148
#undef MC_CMD_0x148_PRIVILEGE_CTG
#define MC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27109,9 +29734,10 @@
/***********************************/
/* MC_CMD_MAE_ENCAP_HEADER_UPDATE
- * Update encap action metadata
+ * Update encap action metadata. See comments for MAE_ENCAP_HEADER_ALLOC.
*/
#define MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149
+#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_MSGSET 0x149
#undef MC_CMD_0x149_PRIVILEGE_CTG
#define MC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27141,6 +29767,7 @@
* Free encap action metadata
*/
#define MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a
+#define MC_CMD_MAE_ENCAP_HEADER_FREE_MSGSET 0x14a
#undef MC_CMD_0x14a_PRIVILEGE_CTG
#define MC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27176,9 +29803,12 @@
/* MC_CMD_MAE_MAC_ADDR_ALLOC
* Allocate MAC address. Hardware implementations have MAC addresses programmed
* into an indirection table, and clients should take care not to allocate the
- * same MAC address twice (but instead reuse its ID).
+ * same MAC address twice (but instead reuse its ID). If the maximum number of
+ * MAC addresses have already been allocated then the command will fail with
+ * MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e
+#define MC_CMD_MAE_MAC_ADDR_ALLOC_MSGSET 0x15e
#undef MC_CMD_0x15e_PRIVILEGE_CTG
#define MC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27204,6 +29834,7 @@
* Free MAC address.
*/
#define MC_CMD_MAE_MAC_ADDR_FREE 0x15f
+#define MC_CMD_MAE_MAC_ADDR_FREE_MSGSET 0x15f
#undef MC_CMD_0x15f_PRIVILEGE_CTG
#define MC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27238,9 +29869,12 @@
/***********************************/
/* MC_CMD_MAE_ACTION_SET_ALLOC
* Allocate an action set, which can be referenced either in response to an
- * Action Rule, or as part of an Action Set List.
+ * Action Rule, or as part of an Action Set List. If the maxmimum number of
+ * action sets have already been allocated then the command will fail with
+ * MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ACTION_SET_ALLOC 0x14d
+#define MC_CMD_MAE_ACTION_SET_ALLOC_MSGSET 0x14d
#undef MC_CMD_0x14d_PRIVILEGE_CTG
#define MC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27267,6 +29901,15 @@
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_LBN 11
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_LBN 12
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_LBN 13
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_LBN 14
+#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_LEN 2
@@ -27313,8 +29956,135 @@
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_OFST 40
#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4
+/* MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN msgrequest: Only supported if
+ * MAE_ACTION_SET_ALLOC_V2_SUPPORTED is advertised in
+ * MC_CMD_GET_CAPABILITIES_V7_OUT.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LEN 51
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_LEN 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_LBN 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_WIDTH 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_LBN 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_WIDTH 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_LBN 8
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_LBN 9
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_LBN 10
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_LBN 11
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_LBN 12
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_LBN 13
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_LBN 14
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
+/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_LEN 2
+/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_OFST 6
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_LEN 2
+/* If VLAN_PUSH == 2, inner TCI value to be inserted. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_OFST 8
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_LEN 2
+/* If VLAN_PUSH == 2, inner TPID value to be inserted. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_OFST 10
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_LEN 2
+/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_OFST 12
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_LEN 4
+/* Set to ENCAP_HEADER_ID_NULL to request no encap action */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_OFST 16
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_LEN 4
+/* An m-port selector identifying the m-port that the modified packet should be
+ * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the
+ * packet.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_OFST 20
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4
+/* Allows an action set to trigger several counter updates. Set to
+ * COUNTER_LIST_ID_NULL to request no counter action.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_OFST 24
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4
+/* If a driver only wished to update one counter within this action set, then
+ * it can supply a COUNTER_ID instead of allocating a single-element counter
+ * list. This field should be set to COUNTER_ID_NULL if this behaviour is not
+ * required. It is not valid to supply a non-NULL value for both
+ * COUNTER_LIST_ID and COUNTER_ID.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_OFST 28
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_OFST 32
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4
+/* Set to MAC_ID_NULL to request no source MAC replacement. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_OFST 36
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_LEN 4
+/* Set to MAC_ID_NULL to request no destination MAC replacement. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_OFST 40
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_LEN 4
+/* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_OFST 44
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_LEN 4
+/* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
+ * within IPv4 and IPv6 headers.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_LEN 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_LBN 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_LBN 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_LBN 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_OFST 48
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_LBN 3
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_WIDTH 6
+/* Actions for modifying the Explicit Congestion Notification (ECN) bits within
+ * IPv4 and IPv6 headers.
+ */
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_LEN 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_LBN 0
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_LBN 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_LBN 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_LBN 3
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_WIDTH 2
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_LBN 5
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_WIDTH 1
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_OFST 50
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_LBN 6
+#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_WIDTH 1
+
/* MC_CMD_MAE_ACTION_SET_ALLOC_OUT msgresponse */
#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4
+/* The MSB of the AS_ID is guaranteed to be clear if the ID is not
+ * ACTION_SET_ID_NULL. This allows an AS_ID to be distinguished from an ASL_ID
+ * returned from MC_CMD_MAE_ACTION_SET_LIST_ALLOC.
+ */
#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0
#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4
/* enum: An action set ID that is guaranteed never to represent an action set
@@ -27326,6 +30096,7 @@
/* MC_CMD_MAE_ACTION_SET_FREE
*/
#define MC_CMD_MAE_ACTION_SET_FREE 0x14e
+#define MC_CMD_MAE_ACTION_SET_FREE_MSGSET 0x14e
#undef MC_CMD_0x14e_PRIVILEGE_CTG
#define MC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27361,9 +30132,12 @@
/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC
* Allocate an action set list (ASL) that can be referenced by an ID. The ASL
* ID can be used when inserting an action rule, so that for each packet
- * matching the rule every action set in the list is applied.
+ * matching the rule every action set in the list is applied. If the maximum
+ * number of ASLs have already been allocated then the command will fail with
+ * MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f
+#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_MSGSET 0x14f
#undef MC_CMD_0x14f_PRIVILEGE_CTG
#define MC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27394,6 +30168,9 @@
/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT msgresponse */
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4
+/* The MSB of the ASL_ID is guaranteed to be set. This allows an ASL_ID to be
+ * distinguished from an AS_ID returned from MC_CMD_MAE_ACTION_SET_ALLOC.
+ */
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0
#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4
/* enum: An action set list ID that is guaranteed never to represent an action
@@ -27407,6 +30184,7 @@
* Free match-action-engine redirect_lists
*/
#define MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150
+#define MC_CMD_MAE_ACTION_SET_LIST_FREE_MSGSET 0x150
#undef MC_CMD_0x150_PRIVILEGE_CTG
#define MC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27441,9 +30219,11 @@
/***********************************/
/* MC_CMD_MAE_OUTER_RULE_INSERT
* Inserts an Outer Rule, which controls encapsulation parsing, and may
- * influence the Lookup Sequence.
+ * influence the Lookup Sequence. If the maximum number of rules have already
+ * been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_OUTER_RULE_INSERT 0x15a
+#define MC_CMD_MAE_OUTER_RULE_INSERT_MSGSET 0x15a
#undef MC_CMD_0x15a_PRIVILEGE_CTG
#define MC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27504,6 +30284,7 @@
/* MC_CMD_MAE_OUTER_RULE_REMOVE
*/
#define MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b
+#define MC_CMD_MAE_OUTER_RULE_REMOVE_MSGSET 0x15b
#undef MC_CMD_0x15b_PRIVILEGE_CTG
#define MC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27583,9 +30364,11 @@
/* MC_CMD_MAE_ACTION_RULE_INSERT
* Insert a rule specify that packets matching a filter be processed according
* to a previous allocated action. Masks can be set as indicated by
- * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES.
+ * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES. If the maximum number of rules have
+ * already been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
*/
#define MC_CMD_MAE_ACTION_RULE_INSERT 0x15c
+#define MC_CMD_MAE_ACTION_RULE_INSERT_MSGSET 0x15c
#undef MC_CMD_0x15c_PRIVILEGE_CTG
#define MC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27627,6 +30410,7 @@
* ENOTSUP, in which case the driver should DELETE/INSERT.
*/
#define MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d
+#define MC_CMD_MAE_ACTION_RULE_UPDATE_MSGSET 0x15d
#undef MC_CMD_0x15d_PRIVILEGE_CTG
#define MC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27648,6 +30432,7 @@
/* MC_CMD_MAE_ACTION_RULE_DELETE
*/
#define MC_CMD_MAE_ACTION_RULE_DELETE 0x155
+#define MC_CMD_MAE_ACTION_RULE_DELETE_MSGSET 0x155
#undef MC_CMD_0x155_PRIVILEGE_CTG
#define MC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27684,6 +30469,7 @@
* Return the m-port corresponding to a selector.
*/
#define MC_CMD_MAE_MPORT_LOOKUP 0x160
+#define MC_CMD_MAE_MPORT_LOOKUP_MSGSET 0x160
#undef MC_CMD_0x160_PRIVILEGE_CTG
#define MC_CMD_0x160_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -27705,6 +30491,7 @@
* match or delivery argument.
*/
#define MC_CMD_MAE_MPORT_ALLOC 0x163
+#define MC_CMD_MAE_MPORT_ALLOC_MSGSET 0x163
#undef MC_CMD_0x163_PRIVILEGE_CTG
#define MC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27812,6 +30599,7 @@
* Free a m-port which was previously allocated by the driver.
*/
#define MC_CMD_MAE_MPORT_FREE 0x164
+#define MC_CMD_MAE_MPORT_FREE_MSGSET 0x164
#undef MC_CMD_0x164_PRIVILEGE_CTG
#define MC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_MAE
@@ -27847,6 +30635,9 @@
#define MAE_MPORT_DESC_CAN_DELETE_OFST 8
#define MAE_MPORT_DESC_CAN_DELETE_LBN 2
#define MAE_MPORT_DESC_CAN_DELETE_WIDTH 1
+#define MAE_MPORT_DESC_IS_ZOMBIE_OFST 8
+#define MAE_MPORT_DESC_IS_ZOMBIE_LBN 3
+#define MAE_MPORT_DESC_IS_ZOMBIE_WIDTH 1
#define MAE_MPORT_DESC_CALLER_FLAGS_LBN 64
#define MAE_MPORT_DESC_CALLER_FLAGS_WIDTH 32
/* Not the ideal name; it's really the type of thing connected to the m-port */
@@ -27869,7 +30660,13 @@
#define MAE_MPORT_DESC_RESERVED_OFST 32
#define MAE_MPORT_DESC_RESERVED_LEN 8
#define MAE_MPORT_DESC_RESERVED_LO_OFST 32
+#define MAE_MPORT_DESC_RESERVED_LO_LEN 4
+#define MAE_MPORT_DESC_RESERVED_LO_LBN 256
+#define MAE_MPORT_DESC_RESERVED_LO_WIDTH 32
#define MAE_MPORT_DESC_RESERVED_HI_OFST 36
+#define MAE_MPORT_DESC_RESERVED_HI_LEN 4
+#define MAE_MPORT_DESC_RESERVED_HI_LBN 288
+#define MAE_MPORT_DESC_RESERVED_HI_WIDTH 32
#define MAE_MPORT_DESC_RESERVED_LBN 256
#define MAE_MPORT_DESC_RESERVED_WIDTH 64
/* Logical port index. Only valid when type NET Port. */
@@ -27916,8 +30713,11 @@
/***********************************/
/* MC_CMD_MAE_MPORT_ENUMERATE
+ * Deprecated in favour of MAE_MPORT_READ_JOURNAL. Support for this command
+ * will be removed at some future point.
*/
#define MC_CMD_MAE_MPORT_ENUMERATE 0x17c
+#define MC_CMD_MAE_MPORT_ENUMERATE_MSGSET 0x17c
#undef MC_CMD_0x17c_PRIVILEGE_CTG
#define MC_CMD_0x17c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
@@ -27945,4 +30745,50 @@
#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM 244
#define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1012
+
+/***********************************/
+/* MC_CMD_MAE_MPORT_READ_JOURNAL
+ * Firmware maintains a per-client journal of mport creations and deletions.
+ * This journal is clear-on-read, i.e. repeated calls of this command will
+ * drain the buffer. Whenever the caller resets its function via FLR or
+ * MC_CMD_ENTITY_RESET, the journal is regenerated from a blank start.
+ */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL 0x147
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_MSGSET 0x147
+#undef MC_CMD_0x147_PRIVILEGE_CTG
+
+#define MC_CMD_0x147_PRIVILEGE_CTG SRIOV_CTG_MAE
+
+/* MC_CMD_MAE_MPORT_READ_JOURNAL_IN msgrequest */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_LEN 4
+/* Any unused flags are reserved and must be set to zero. */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_OFST 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_LEN 4
+
+/* MC_CMD_MAE_MPORT_READ_JOURNAL_OUT msgresponse */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMIN 12
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX 252
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX_MCDI2 1020
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LEN(num) (12+1*(num))
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_NUM(len) (((len)-12)/1)
+/* Any unused flags are reserved and must be ignored. */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_OFST 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_LEN 4
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_OFST 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_LBN 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_WIDTH 1
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_OFST 4
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_LEN 4
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_OFST 8
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_LEN 4
+/* Any array of MAE_MPORT_DESC structures. The MAE_MPORT_DESC structure may
+ * grow in future version of this command. Drivers should use a stride of
+ * SIZEOF_MPORT_DESC. Fields beyond SIZEOF_MPORT_DESC are not present.
+ */
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_OFST 12
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_LEN 1
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MINNUM 0
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM 240
+#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1008
+
#endif /* _SIENA_MC_DRIVER_PCOL_H */
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h
index f7c89fabc..c45f678c2 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h
@@ -6,7 +6,7 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
* rebuild this file with "make mcdi_headers_v5".
*/
@@ -20,6 +20,7 @@
* Perform an FC operation
*/
#define MC_CMD_FC 0x9
+#define MC_CMD_FC_MSGSET 0x9
/* MC_CMD_FC_IN msgrequest */
#define MC_CMD_FC_IN_LEN 4
@@ -212,7 +213,13 @@
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LEN 4
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LBN 128
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_WIDTH 32
#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LEN 4
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LBN 160
+#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_WIDTH 32
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4
#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_OFST 24
@@ -784,12 +791,24 @@
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LBN 96
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LBN 128
+#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_WIDTH 32
/* AOE address from which to transfer data */
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LBN 160
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LBN 192
+#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_WIDTH 32
/* Length of AOE transfer (total) */
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28
#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4
@@ -916,7 +935,13 @@
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LEN 4
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LBN 96
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_WIDTH 32
#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LEN 4
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LBN 128
+#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_WIDTH 32
#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4
@@ -1016,7 +1041,13 @@
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LEN 4
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LBN 96
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_WIDTH 32
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LEN 4
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LBN 128
+#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_WIDTH 32
/* Port number of PTP packet for which timestamp required */
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20
#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4
@@ -1320,7 +1351,13 @@
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LEN 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LBN 32
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_WIDTH 32
#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LEN 4
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LBN 64
+#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_WIDTH 32
/* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */
#define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8
@@ -1347,7 +1384,13 @@
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS
#define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */
#define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */
@@ -1382,7 +1425,13 @@
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS
#define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */
#define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */
@@ -1415,7 +1464,13 @@
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LBN 0
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LEN 4
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LBN 32
+#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_WIDTH 32
#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK
/* MC_CMD_FC_OUT_MAC msgresponse */
@@ -1636,7 +1691,13 @@
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LBN 128
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_WIDTH 32
#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LEN 4
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LBN 160
+#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_WIDTH 32
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4
#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28
@@ -1976,12 +2037,24 @@
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LBN 64
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LBN 96
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_WIDTH 32
/* Length of address map */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LBN 128
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LBN 160
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_WIDTH 32
/* Component information field */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24
#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4
@@ -1989,7 +2062,13 @@
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LBN 224
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_WIDTH 32
#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LEN 4
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LBN 256
+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_WIDTH 32
/* Name of the component */
#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36
#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1
@@ -2132,7 +2211,13 @@
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LBN 96
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LBN 128
+#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_WIDTH 32
/* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */
#define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)
@@ -2153,7 +2238,13 @@
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LBN 32
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LEN 4
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LBN 64
+#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_WIDTH 32
#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK
/* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */
@@ -2222,12 +2313,24 @@
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LBN 32
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LBN 64
+#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_WIDTH 32
/* AOE address from which to transfer data */
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LBN 96
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LBN 128
+#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_WIDTH 32
/* Length of AOE transfer (total) */
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20
#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4
@@ -2243,12 +2346,24 @@
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LBN 288
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LBN 320
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_WIDTH 32
/* When active, end read time */
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LBN 352
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LBN 384
+#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_WIDTH 32
/* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */
#define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0
@@ -2263,7 +2378,13 @@
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LEN 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LBN 32
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_WIDTH 32
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LEN 4
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LBN 64
+#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_WIDTH 32
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4
#define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16
@@ -2311,7 +2432,13 @@
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LEN 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LBN 0
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_WIDTH 32
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LEN 4
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LBN 32
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_WIDTH 32
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127
@@ -2391,6 +2518,7 @@
* AOE operations on MC
*/
#define MC_CMD_AOE 0xa
+#define MC_CMD_AOE_MSGSET 0xa
/* MC_CMD_AOE_IN msgrequest */
#define MC_CMD_AOE_IN_LEN 4
@@ -2580,7 +2708,13 @@
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LEN 4
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LBN 64
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_WIDTH 32
#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LEN 4
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LBN 96
+#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_WIDTH 32
#define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16
#define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4
#define MC_CMD_AOE_IN_MAC_STATS_DMA_OFST 16
@@ -3024,7 +3158,13 @@
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LEN 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LBN 0
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_WIDTH 32
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LEN 4
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LBN 32
+#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_WIDTH 32
#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
/* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */
diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h
index be570bc0a..e8fbb6f94 100644
--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h
+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h
@@ -6,7 +6,7 @@
/*
* This file is automatically generated. DO NOT EDIT IT.
- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and
* rebuild this file with "make mcdi_headers_v5".
*
* The version of this file has MCDI strings really used in the libefx.
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v4 2/3] common/sfc_efx/base: add MAE VLAN presence match bits
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
@ 2021-05-24 11:48 ` Ivan Malov
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 3/3] net/sfc: support matching on VLAN presence in transfer rules Ivan Malov
2021-07-07 10:00 ` [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows David Marchand
3 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-24 11:48 UTC (permalink / raw)
To: dev
Cc: Ray Kinsella, Ferruh Yigit, Andrew Rybchenko, Andy Moreton, Neil Horman
Introduce necessary infrastructure for these fields to
be set, validated and compared during class comparison.
Enumeration and mappings envisaged are MCDI-compatible.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
---
drivers/common/sfc_efx/base/efx.h | 18 ++
drivers/common/sfc_efx/base/efx_impl.h | 3 +-
drivers/common/sfc_efx/base/efx_mae.c | 235 ++++++++++++++++++++++++-
drivers/common/sfc_efx/version.map | 1 +
4 files changed, 254 insertions(+), 3 deletions(-)
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 771fe5a17..8e13075b0 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -4103,6 +4103,10 @@ efx_mae_match_spec_fini(
__in efx_mae_match_spec_t *spec);
typedef enum efx_mae_field_id_e {
+ /*
+ * Fields which can be set by efx_mae_match_spec_field_set()
+ * or by using dedicated field-specific helper APIs.
+ */
EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
EFX_MAE_FIELD_ETHER_TYPE_BE,
EFX_MAE_FIELD_ETH_SADDR_BE,
@@ -4140,6 +4144,12 @@ typedef enum efx_mae_field_id_e {
EFX_MAE_FIELD_ENC_VNET_ID_BE,
EFX_MAE_FIELD_OUTER_RULE_ID,
+ /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
+ EFX_MAE_FIELD_HAS_OVLAN,
+ EFX_MAE_FIELD_HAS_IVLAN,
+ EFX_MAE_FIELD_ENC_HAS_OVLAN,
+ EFX_MAE_FIELD_ENC_HAS_IVLAN,
+
EFX_MAE_FIELD_NIDS
} efx_mae_field_id_t;
@@ -4198,6 +4208,14 @@ efx_mae_match_spec_field_set(
__in size_t mask_size,
__in_bcount(mask_size) const uint8_t *mask);
+/* The corresponding mask will be set to B_TRUE. */
+LIBEFX_API
+extern __checkReturn efx_rc_t
+efx_mae_match_spec_bit_set(
+ __in efx_mae_match_spec_t *spec,
+ __in efx_mae_field_id_t field_id,
+ __in boolean_t value);
+
/* If the mask argument is NULL, the API will use full mask by default. */
LIBEFX_API
extern __checkReturn efx_rc_t
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index 4a513171a..8b63cfb37 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1720,7 +1720,8 @@ struct efx_mae_match_spec_s {
efx_mae_rule_type_t emms_type;
uint32_t emms_prio;
union emms_mask_value_pairs {
- uint8_t action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
+ uint8_t action[
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN];
uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN];
} emms_mask_value_pairs;
};
diff --git a/drivers/common/sfc_efx/base/efx_mae.c b/drivers/common/sfc_efx/base/efx_mae.c
index c1784211e..569748804 100644
--- a/drivers/common/sfc_efx/base/efx_mae.c
+++ b/drivers/common/sfc_efx/base/efx_mae.c
@@ -465,6 +465,10 @@ typedef enum efx_mae_field_cap_id_e {
EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
+ EFX_MAE_FIELD_ID_HAS_OVLAN = MAE_FIELD_HAS_OVLAN,
+ EFX_MAE_FIELD_ID_HAS_IVLAN = MAE_FIELD_HAS_IVLAN,
+ EFX_MAE_FIELD_ID_ENC_HAS_OVLAN = MAE_FIELD_ENC_HAS_OVLAN,
+ EFX_MAE_FIELD_ID_ENC_HAS_IVLAN = MAE_FIELD_ENC_HAS_IVLAN,
EFX_MAE_FIELD_CAP_NIDS
} efx_mae_field_cap_id_t;
@@ -591,6 +595,65 @@ static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
#undef EFX_MAE_MV_DESC_ALT
#undef EFX_MAE_MV_DESC
+};
+
+/*
+ * The following structure is a means to describe an MAE bit.
+ * The information in it is meant to be used internally by
+ * APIs for addressing a given flag in a mask-value pairs
+ * structure and for validation purposes.
+ */
+typedef struct efx_mae_mv_bit_desc_s {
+ /*
+ * Arrays using this struct are indexed by field IDs.
+ * Fields which aren't meant to be referenced by these
+ * arrays comprise gaps (invalid entries). Below field
+ * helps to identify such entries.
+ */
+ boolean_t emmbd_entry_is_valid;
+ efx_mae_field_cap_id_t emmbd_bit_cap_id;
+ size_t emmbd_value_ofst;
+ unsigned int emmbd_value_lbn;
+ size_t emmbd_mask_ofst;
+ unsigned int emmbd_mask_lbn;
+} efx_mae_mv_bit_desc_t;
+
+static const efx_mae_mv_bit_desc_t __efx_mae_outer_rule_mv_bit_desc_set[] = {
+#define EFX_MAE_MV_BIT_DESC(_name) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ B_TRUE, \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_LBN, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
+ MAE_ENC_FIELD_PAIRS_##_name##_MASK_LBN, \
+ }
+
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
+
+#undef EFX_MAE_MV_BIT_DESC
+};
+
+static const efx_mae_mv_bit_desc_t __efx_mae_action_rule_mv_bit_desc_set[] = {
+#define EFX_MAE_MV_BIT_DESC(_name) \
+ [EFX_MAE_FIELD_##_name] = \
+ { \
+ B_TRUE, \
+ EFX_MAE_FIELD_ID_##_name, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST, \
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN, \
+ }
+
+ EFX_MAE_MV_BIT_DESC(HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(HAS_IVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
+ EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
+
+#undef EFX_MAE_MV_BIT_DESC
};
__checkReturn efx_rc_t
@@ -789,6 +852,70 @@ efx_mae_match_spec_field_set(
EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
+fail3:
+ EFSYS_PROBE(fail3);
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_mae_match_spec_bit_set(
+ __in efx_mae_match_spec_t *spec,
+ __in efx_mae_field_id_t field_id,
+ __in boolean_t value)
+{
+ const efx_mae_mv_bit_desc_t *bit_descp;
+ unsigned int bit_desc_set_nentries;
+ unsigned int byte_idx;
+ unsigned int bit_idx;
+ uint8_t *mvp;
+ efx_rc_t rc;
+
+ switch (spec->emms_type) {
+ case EFX_MAE_RULE_OUTER:
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
+ bit_descp = &__efx_mae_outer_rule_mv_bit_desc_set[field_id];
+ mvp = spec->emms_mask_value_pairs.outer;
+ break;
+ case EFX_MAE_RULE_ACTION:
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
+ bit_descp = &__efx_mae_action_rule_mv_bit_desc_set[field_id];
+ mvp = spec->emms_mask_value_pairs.action;
+ break;
+ default:
+ rc = ENOTSUP;
+ goto fail1;
+ }
+
+ if ((unsigned int)field_id >= bit_desc_set_nentries) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE) {
+ rc = EINVAL;
+ goto fail3;
+ }
+
+ byte_idx = bit_descp->emmbd_value_ofst + bit_descp->emmbd_value_lbn / 8;
+ bit_idx = bit_descp->emmbd_value_lbn % 8;
+
+ if (value != B_FALSE)
+ mvp[byte_idx] |= (1U << bit_idx);
+ else
+ mvp[byte_idx] &= ~(1U << bit_idx);
+
+ byte_idx = bit_descp->emmbd_mask_ofst + bit_descp->emmbd_mask_lbn / 8;
+ bit_idx = bit_descp->emmbd_mask_lbn % 8;
+ mvp[byte_idx] |= (1U << bit_idx);
+
+ return (0);
+
fail3:
EFSYS_PROBE(fail3);
fail2:
@@ -905,6 +1032,8 @@ efx_mae_match_spec_is_valid(
const efx_mae_field_cap_t *field_caps;
const efx_mae_mv_desc_t *desc_setp;
unsigned int desc_set_nentries;
+ const efx_mae_mv_bit_desc_t *bit_desc_setp;
+ unsigned int bit_desc_set_nentries;
boolean_t is_valid = B_TRUE;
efx_mae_field_id_t field_id;
const uint8_t *mvp;
@@ -915,6 +1044,9 @@ efx_mae_match_spec_is_valid(
desc_setp = __efx_mae_outer_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
mvp = spec->emms_mask_value_pairs.outer;
break;
case EFX_MAE_RULE_ACTION:
@@ -922,6 +1054,9 @@ efx_mae_match_spec_is_valid(
desc_setp = __efx_mae_action_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
mvp = spec->emms_mask_value_pairs.action;
break;
default:
@@ -989,6 +1124,48 @@ efx_mae_match_spec_is_valid(
break;
}
+ if (is_valid == B_FALSE)
+ return (B_FALSE);
+ }
+
+ for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
+ ++field_id) {
+ const efx_mae_mv_bit_desc_t *bit_descp =
+ &bit_desc_setp[field_id];
+ unsigned int byte_idx =
+ bit_descp->emmbd_mask_ofst +
+ bit_descp->emmbd_mask_lbn / 8;
+ unsigned int bit_idx =
+ bit_descp->emmbd_mask_lbn % 8;
+ efx_mae_field_cap_id_t bit_cap_id =
+ bit_descp->emmbd_bit_cap_id;
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE)
+ continue; /* Skip array gap */
+
+ if ((unsigned int)bit_cap_id >= field_ncaps) {
+ /* No capability for this bit = unsupported. */
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
+ if (is_valid == B_FALSE)
+ break;
+ else
+ continue;
+ }
+
+ switch (field_caps[bit_cap_id].emfc_support) {
+ case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
+ is_valid = B_TRUE;
+ break;
+ case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) != 0);
+ break;
+ case MAE_FIELD_SUPPORTED_MATCH_NEVER:
+ case MAE_FIELD_UNSUPPORTED:
+ default:
+ is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
+ break;
+ }
+
if (is_valid == B_FALSE)
break;
}
@@ -1542,6 +1719,8 @@ efx_mae_match_specs_class_cmp(
const efx_mae_field_cap_t *field_caps;
const efx_mae_mv_desc_t *desc_setp;
unsigned int desc_set_nentries;
+ const efx_mae_mv_bit_desc_t *bit_desc_setp;
+ unsigned int bit_desc_set_nentries;
boolean_t have_same_class = B_TRUE;
efx_mae_field_id_t field_id;
const uint8_t *mvpl;
@@ -1554,6 +1733,9 @@ efx_mae_match_specs_class_cmp(
desc_setp = __efx_mae_outer_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
mvpl = left->emms_mask_value_pairs.outer;
mvpr = right->emms_mask_value_pairs.outer;
break;
@@ -1562,6 +1744,9 @@ efx_mae_match_specs_class_cmp(
desc_setp = __efx_mae_action_rule_mv_desc_set;
desc_set_nentries =
EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
+ bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
+ bit_desc_set_nentries =
+ EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
mvpl = left->emms_mask_value_pairs.action;
mvpr = right->emms_mask_value_pairs.action;
break;
@@ -1634,6 +1819,52 @@ efx_mae_match_specs_class_cmp(
}
}
+ if (have_same_class == B_FALSE)
+ goto done;
+
+ for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
+ ++field_id) {
+ const efx_mae_mv_bit_desc_t *bit_descp =
+ &bit_desc_setp[field_id];
+ efx_mae_field_cap_id_t bit_cap_id =
+ bit_descp->emmbd_bit_cap_id;
+ unsigned int byte_idx;
+ unsigned int bit_idx;
+
+ if (bit_descp->emmbd_entry_is_valid == B_FALSE)
+ continue; /* Skip array gap */
+
+ if ((unsigned int)bit_cap_id >= field_ncaps)
+ break;
+
+ byte_idx =
+ bit_descp->emmbd_mask_ofst +
+ bit_descp->emmbd_mask_lbn / 8;
+ bit_idx =
+ bit_descp->emmbd_mask_lbn % 8;
+
+ if (field_caps[bit_cap_id].emfc_mask_affects_class &&
+ (mvpl[byte_idx] & (1U << bit_idx)) !=
+ (mvpr[byte_idx] & (1U << bit_idx))) {
+ have_same_class = B_FALSE;
+ break;
+ }
+
+ byte_idx =
+ bit_descp->emmbd_value_ofst +
+ bit_descp->emmbd_value_lbn / 8;
+ bit_idx =
+ bit_descp->emmbd_value_lbn % 8;
+
+ if (field_caps[bit_cap_id].emfc_match_affects_class &&
+ (mvpl[byte_idx] & (1U << bit_idx)) !=
+ (mvpr[byte_idx] & (1U << bit_idx))) {
+ have_same_class = B_FALSE;
+ break;
+ }
+ }
+
+done:
*have_same_classp = have_same_class;
return (0);
@@ -2282,10 +2513,10 @@ efx_mae_action_rule_insert(
* MCDI request and are thus safe to be copied directly to the buffer.
*/
EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
- MAE_FIELD_MASK_VALUE_PAIRS_LEN);
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
memcpy(payload + offset, spec->emms_mask_value_pairs.action,
- MAE_FIELD_MASK_VALUE_PAIRS_LEN);
+ MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
efx_mcdi_execute(enp, &req);
diff --git a/drivers/common/sfc_efx/version.map b/drivers/common/sfc_efx/version.map
index 5e724fd10..75da5aa5c 100644
--- a/drivers/common/sfc_efx/version.map
+++ b/drivers/common/sfc_efx/version.map
@@ -106,6 +106,7 @@ INTERNAL {
efx_mae_fini;
efx_mae_get_limits;
efx_mae_init;
+ efx_mae_match_spec_bit_set;
efx_mae_match_spec_field_set;
efx_mae_match_spec_fini;
efx_mae_match_spec_init;
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [dpdk-dev] [PATCH v4 3/3] net/sfc: support matching on VLAN presence in transfer rules
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 1/3] common/sfc_efx/base: update MCDI headers Ivan Malov
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 2/3] common/sfc_efx/base: add MAE VLAN presence match bits Ivan Malov
@ 2021-05-24 11:48 ` Ivan Malov
2021-07-07 10:00 ` [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows David Marchand
3 siblings, 0 replies; 23+ messages in thread
From: Ivan Malov @ 2021-05-24 11:48 UTC (permalink / raw)
To: dev; +Cc: Ray Kinsella, Ferruh Yigit, Andrew Rybchenko, Andy Moreton
Take into account VLAN presence fields in items ETH and VLAN.
Provided that the item ETH does not match on the EtherType,
the pattern behaviour will be as follows:
- ETH (mask->has_vlan = 0) | IPv4 = match both tagged and untagged;
- ETH (mask->has_vlan = 1) | IPv4 = match as per spec->has_vlan;
- ETH (mask->has_vlan = 0) | VLAN | IPv4 = match only tagged.
Similar logic applies to double tagging.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
---
drivers/net/sfc/sfc_mae.c | 124 ++++++++++++++++++++++++++++++++------
drivers/net/sfc/sfc_mae.h | 19 +++++-
2 files changed, 123 insertions(+), 20 deletions(-)
diff --git a/drivers/net/sfc/sfc_mae.c b/drivers/net/sfc/sfc_mae.c
index a2c0aa143..33bff275c 100644
--- a/drivers/net/sfc/sfc_mae.c
+++ b/drivers/net/sfc/sfc_mae.c
@@ -728,6 +728,7 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
RTE_BE16(RTE_ETHER_TYPE_QINQ2),
RTE_BE16(RTE_ETHER_TYPE_QINQ3),
};
+ bool enforce_tag_presence[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {0};
unsigned int nb_supported_tpids = RTE_DIM(supported_tpids);
unsigned int ethertype_idx;
const uint8_t *valuep;
@@ -753,6 +754,22 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
ethertype_idx < pdata->nb_vlan_tags; ++ethertype_idx) {
unsigned int tpid_idx;
+ /*
+ * This loop can have only two iterations. On the second one,
+ * drop outer tag presence enforcement bit because the inner
+ * tag presence automatically assumes that for the outer tag.
+ */
+ enforce_tag_presence[0] = B_FALSE;
+
+ if (ethertypes[ethertype_idx].mask == RTE_BE16(0)) {
+ if (pdata->tci_masks[ethertype_idx] == RTE_BE16(0))
+ enforce_tag_presence[ethertype_idx] = B_TRUE;
+
+ /* No match on this field, and no value check. */
+ nb_supported_tpids = 1;
+ continue;
+ }
+
/* Exact match is supported only. */
if (ethertypes[ethertype_idx].mask != RTE_BE16(0xffff)) {
rc = EINVAL;
@@ -812,6 +829,24 @@ sfc_mae_rule_process_pattern_data(struct sfc_mae_parse_ctx *ctx,
}
}
+ if (enforce_tag_presence[0] || pdata->has_ovlan_mask) {
+ rc = efx_mae_match_spec_bit_set(ctx->match_spec,
+ fremap[EFX_MAE_FIELD_HAS_OVLAN],
+ enforce_tag_presence[0] ||
+ pdata->has_ovlan_value);
+ if (rc != 0)
+ goto fail;
+ }
+
+ if (enforce_tag_presence[1] || pdata->has_ivlan_mask) {
+ rc = efx_mae_match_spec_bit_set(ctx->match_spec,
+ fremap[EFX_MAE_FIELD_HAS_IVLAN],
+ enforce_tag_presence[1] ||
+ pdata->has_ivlan_value);
+ if (rc != 0)
+ goto fail;
+ }
+
valuep = (const uint8_t *)&pdata->l3_next_proto_value;
maskp = (const uint8_t *)&pdata->l3_next_proto_mask;
rc = efx_mae_match_spec_field_set(ctx->match_spec,
@@ -1154,6 +1189,7 @@ sfc_mae_rule_parse_item_eth(const struct rte_flow_item *item,
sfc_mae_item_build_supp_mask(flocs_eth, RTE_DIM(flocs_eth),
&supp_mask, sizeof(supp_mask));
+ supp_mask.has_vlan = 1;
rc = sfc_flow_parse_init(item,
(const void **)&spec, (const void **)&mask,
@@ -1172,14 +1208,23 @@ sfc_mae_rule_parse_item_eth(const struct rte_flow_item *item,
item_spec = (const struct rte_flow_item_eth *)spec;
item_mask = (const struct rte_flow_item_eth *)mask;
+ /*
+ * Remember various match criteria in the parsing context.
+ * sfc_mae_rule_process_pattern_data() will consider them
+ * altogether when the rest of the items have been parsed.
+ */
ethertypes[0].value = item_spec->type;
ethertypes[0].mask = item_mask->type;
+ if (item_mask->has_vlan) {
+ pdata->has_ovlan_mask = B_TRUE;
+ if (item_spec->has_vlan)
+ pdata->has_ovlan_value = B_TRUE;
+ }
} else {
/*
- * The specification is empty. This is wrong in the case
- * when there are more network patterns in line. Other
- * than that, any Ethernet can match. All of that is
- * checked at the end of parsing.
+ * The specification is empty. The overall pattern
+ * validity will be enforced at the end of parsing.
+ * See sfc_mae_rule_process_pattern_data().
*/
return 0;
}
@@ -1229,6 +1274,16 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
{
struct sfc_mae_parse_ctx *ctx_mae = ctx->mae;
struct sfc_mae_pattern_data *pdata = &ctx_mae->pattern_data;
+ boolean_t *has_vlan_mp_by_nb_tags[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {
+ &pdata->has_ovlan_mask,
+ &pdata->has_ivlan_mask,
+ };
+ boolean_t *has_vlan_vp_by_nb_tags[SFC_MAE_MATCH_VLAN_MAX_NTAGS] = {
+ &pdata->has_ovlan_value,
+ &pdata->has_ivlan_value,
+ };
+ boolean_t *cur_tag_presence_bit_mp;
+ boolean_t *cur_tag_presence_bit_vp;
const struct sfc_mae_field_locator *flocs;
struct rte_flow_item_vlan supp_mask;
const uint8_t *spec = NULL;
@@ -1244,14 +1299,27 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
"Can't match that many VLAN tags");
}
+ cur_tag_presence_bit_mp = has_vlan_mp_by_nb_tags[pdata->nb_vlan_tags];
+ cur_tag_presence_bit_vp = has_vlan_vp_by_nb_tags[pdata->nb_vlan_tags];
+
+ if (*cur_tag_presence_bit_mp == B_TRUE &&
+ *cur_tag_presence_bit_vp == B_FALSE) {
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "The previous item enforces no (more) VLAN, "
+ "so the current item (VLAN) must not exist");
+ }
+
nb_flocs = RTE_DIM(flocs_vlan) / SFC_MAE_MATCH_VLAN_MAX_NTAGS;
flocs = flocs_vlan + pdata->nb_vlan_tags * nb_flocs;
- /* If parsing fails, this can remain incremented. */
- ++pdata->nb_vlan_tags;
-
sfc_mae_item_build_supp_mask(flocs, nb_flocs,
&supp_mask, sizeof(supp_mask));
+ /*
+ * This only means that the field is supported by the driver and libefx.
+ * Support on NIC level will be checked when all items have been parsed.
+ */
+ supp_mask.has_more_vlan = 1;
rc = sfc_flow_parse_init(item,
(const void **)&spec, (const void **)&mask,
@@ -1262,26 +1330,44 @@ sfc_mae_rule_parse_item_vlan(const struct rte_flow_item *item,
return rc;
if (spec != NULL) {
- struct sfc_mae_ethertype *ethertypes = pdata->ethertypes;
+ struct sfc_mae_ethertype *et = pdata->ethertypes;
const struct rte_flow_item_vlan *item_spec;
const struct rte_flow_item_vlan *item_mask;
item_spec = (const struct rte_flow_item_vlan *)spec;
item_mask = (const struct rte_flow_item_vlan *)mask;
- ethertypes[pdata->nb_vlan_tags].value = item_spec->inner_type;
- ethertypes[pdata->nb_vlan_tags].mask = item_mask->inner_type;
- } else {
/*
- * The specification is empty. This is wrong in the case
- * when there are more network patterns in line. Other
- * than that, any Ethernet can match. All of that is
- * checked at the end of parsing.
+ * Remember various match criteria in the parsing context.
+ * sfc_mae_rule_process_pattern_data() will consider them
+ * altogether when the rest of the items have been parsed.
*/
- return 0;
+ et[pdata->nb_vlan_tags + 1].value = item_spec->inner_type;
+ et[pdata->nb_vlan_tags + 1].mask = item_mask->inner_type;
+ pdata->tci_masks[pdata->nb_vlan_tags] = item_mask->tci;
+ if (item_mask->has_more_vlan) {
+ if (pdata->nb_vlan_tags ==
+ SFC_MAE_MATCH_VLAN_MAX_NTAGS) {
+ return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "Can't use 'has_more_vlan' in "
+ "the second item VLAN");
+ }
+ pdata->has_ivlan_mask = B_TRUE;
+ if (item_spec->has_more_vlan)
+ pdata->has_ivlan_value = B_TRUE;
+ }
+
+ /* Convert TCI to MAE representation right now. */
+ rc = sfc_mae_parse_item(flocs, nb_flocs, spec, mask,
+ ctx_mae, error);
+ if (rc != 0)
+ return rc;
}
- return sfc_mae_parse_item(flocs, nb_flocs, spec, mask, ctx_mae, error);
+ ++(pdata->nb_vlan_tags);
+
+ return 0;
}
static const struct sfc_mae_field_locator flocs_ipv4[] = {
@@ -1612,6 +1698,8 @@ static const efx_mae_field_id_t field_ids_no_remap[] = {
FIELD_ID_NO_REMAP(L4_SPORT_BE),
FIELD_ID_NO_REMAP(L4_DPORT_BE),
FIELD_ID_NO_REMAP(TCP_FLAGS_BE),
+ FIELD_ID_NO_REMAP(HAS_OVLAN),
+ FIELD_ID_NO_REMAP(HAS_IVLAN),
#undef FIELD_ID_NO_REMAP
};
@@ -1642,6 +1730,8 @@ static const efx_mae_field_id_t field_ids_remap_to_encap[] = {
FIELD_ID_REMAP_TO_ENCAP(DST_IP6_BE),
FIELD_ID_REMAP_TO_ENCAP(L4_SPORT_BE),
FIELD_ID_REMAP_TO_ENCAP(L4_DPORT_BE),
+ FIELD_ID_REMAP_TO_ENCAP(HAS_OVLAN),
+ FIELD_ID_REMAP_TO_ENCAP(HAS_IVLAN),
#undef FIELD_ID_REMAP_TO_ENCAP
};
diff --git a/drivers/net/sfc/sfc_mae.h b/drivers/net/sfc/sfc_mae.h
index 9740e54e4..0241fe33c 100644
--- a/drivers/net/sfc/sfc_mae.h
+++ b/drivers/net/sfc/sfc_mae.h
@@ -130,12 +130,14 @@ struct sfc_mae_pattern_data {
*
* - If an item ETH is followed by a single item VLAN,
* the former must have "type" set to one of supported
- * TPID values (0x8100, 0x88a8, 0x9100, 0x9200, 0x9300).
+ * TPID values (0x8100, 0x88a8, 0x9100, 0x9200, 0x9300),
+ * or 0x0000/0x0000.
*
* - If an item ETH is followed by two items VLAN, the
* item ETH must have "type" set to one of supported TPID
- * values (0x88a8, 0x9100, 0x9200, 0x9300), and the outermost
- * VLAN item must have "inner_type" set to TPID value 0x8100.
+ * values (0x88a8, 0x9100, 0x9200, 0x9300), or 0x0000/0x0000,
+ * and the outermost VLAN item must have "inner_type" set
+ * to TPID value 0x8100, or 0x0000/0x0000
*
* - If a L2 item is followed by a L3 one, the former must
* indicate "type" ("inner_type") which corresponds to
@@ -156,6 +158,9 @@ struct sfc_mae_pattern_data {
* VLAN (L3 EtherType) --> ETHER_TYPE_BE
*/
struct sfc_mae_ethertype ethertypes[SFC_MAE_L2_MAX_NITEMS];
+
+ rte_be16_t tci_masks[SFC_MAE_MATCH_VLAN_MAX_NTAGS];
+
unsigned int nb_vlan_tags;
/**
@@ -191,6 +196,14 @@ struct sfc_mae_pattern_data {
*/
uint8_t l3_next_proto_restriction_value;
uint8_t l3_next_proto_restriction_mask;
+
+ /* Projected state of EFX_MAE_FIELD_HAS_OVLAN match bit */
+ bool has_ovlan_value;
+ bool has_ovlan_mask;
+
+ /* Projected state of EFX_MAE_FIELD_HAS_IVLAN match bit */
+ bool has_ivlan_value;
+ bool has_ivlan_mask;
};
struct sfc_mae_parse_ctx {
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 0/3] Match On VLAN Presence In Transfer Flows Ivan Malov
` (2 preceding siblings ...)
2021-05-24 11:48 ` [dpdk-dev] [PATCH v4 3/3] net/sfc: support matching on VLAN presence in transfer rules Ivan Malov
@ 2021-07-07 10:00 ` David Marchand
3 siblings, 0 replies; 23+ messages in thread
From: David Marchand @ 2021-07-07 10:00 UTC (permalink / raw)
To: Ivan Malov; +Cc: dev, Ray Kinsella, Ferruh Yigit
On Mon, May 24, 2021 at 1:49 PM Ivan Malov <ivan.malov@oktetlabs.ru> wrote:
>
> Changes in v2:
> * [1/3] no longer triggers spelling warnings
>
> Changes in v3:
> * Attempt to correct mailing order of the patches
>
> Changes in v4:
> * Yet another attempt to correct mailing order of the patches
>
> Andrew Rybchenko (1):
> common/sfc_efx/base: update MCDI headers
>
> Ivan Malov (2):
> common/sfc_efx/base: add MAE VLAN presence match bits
> net/sfc: support matching on VLAN presence in transfer rules
Series applied, thanks.
--
David Marchand
^ permalink raw reply [flat|nested] 23+ messages in thread