From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B97CBA0524; Mon, 31 May 2021 23:43:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0260241121; Mon, 31 May 2021 23:42:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4ED7641121 for ; Mon, 31 May 2021 23:42:30 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLf2vK003782; Mon, 31 May 2021 14:42:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=MkF7Nw33wFR9Lpks8S6fa/TBJkG7De5geZ+Ft0GQDzo=; b=g9hr/mbIB5WZqF5c8hh36a7/xlGjJsWP8aWB6iGmPWu3qvmJBlCS7t/Z2xAzX8RE/+Qa sbT/ZX+uLWd6zcZ96/I1PfKPx/iJEwn0be8HENcnYufTyR9309trDBUhyMK8q50IH8jR SqF8uXXi9orQ9Z6g9DjliPxCZ34kpGJF02Ry9iRfGV6+toWoETtUL9FYBSpa5jCi4JeD aiGrsN1P9IppFkL6km7YXhGM5Nf8ekHM44ih8IinI2FchIoZNerSEy3X3hiBLVBIMuxH qo5UejlQr0FEBV5nA0gt3QEjOlpMU3lG6CCX1HsFtSGM+th52PCjIGY+Aa7lqXUUzPdC 6A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja130-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:28 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:26 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:25 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id B46453F7043; Mon, 31 May 2021 14:42:23 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:29 +0200 Message-ID: <20210531214142.30167-16-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: LY7Y3flDWc4YSRWFWiVbgcYwGf6Tce3V X-Proofpoint-ORIG-GUID: LY7Y3flDWc4YSRWFWiVbgcYwGf6Tce3V X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 15/28] common/cnxk: add support for device init and fini X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for device init and fini. It merely saves baseband phy state container in a globally accessible resource chest. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_api.h | 4 +++ drivers/common/cnxk/roc_bphy.c | 40 +++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy.h | 17 ++++++++++++ drivers/common/cnxk/roc_idev.c | 1 + drivers/common/cnxk/roc_idev_priv.h | 2 ++ drivers/common/cnxk/version.map | 2 ++ 7 files changed, 67 insertions(+) create mode 100644 drivers/common/cnxk/roc_bphy.c create mode 100644 drivers/common/cnxk/roc_bphy.h diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 59975fd34..946b98f46 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -11,6 +11,7 @@ endif config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON' deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( + 'roc_bphy.c', 'roc_bphy_cgx.c', 'roc_dev.c', 'roc_idev.c', diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 256d8c68d..dd0047873 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -50,6 +50,7 @@ #define PCI_DEVID_CNXK_EP_VF 0xB203 #define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6 #define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7 +#define PCI_DEVID_CNXK_BPHY 0xA089 #define PCI_DEVID_CN9K_CGX 0xA059 #define PCI_DEVID_CN10K_RPM 0xA060 @@ -103,4 +104,7 @@ /* Baseband phy cgx */ #include "roc_bphy_cgx.h" +/* Baseband phy */ +#include "roc_bphy.h" + #endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_bphy.c b/drivers/common/cnxk/roc_bphy.c new file mode 100644 index 000000000..77606d646 --- /dev/null +++ b/drivers/common/cnxk/roc_bphy.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +int +roc_bphy_dev_init(struct roc_bphy *roc_bphy) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (!idev) + return -ENODEV; + + if (!roc_bphy || !roc_bphy->pci_dev) + return -EINVAL; + + idev->bphy = roc_bphy; + + return 0; +} + +int +roc_bphy_dev_fini(struct roc_bphy *roc_bphy) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (!idev) + return -ENODEV; + + if (!roc_bphy) + return -EINVAL; + + idev->bphy = NULL; + + return 0; +} diff --git a/drivers/common/cnxk/roc_bphy.h b/drivers/common/cnxk/roc_bphy.h new file mode 100644 index 000000000..0579c6c44 --- /dev/null +++ b/drivers/common/cnxk/roc_bphy.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2020 Marvell. + */ + +#ifndef _ROC_BPHY_ +#define _ROC_BPHY_ + +#include "roc_api.h" + +struct roc_bphy { + struct plt_pci_device *pci_dev; +} __plt_cache_aligned; + +int __roc_api roc_bphy_dev_init(struct roc_bphy *roc_bphy); +int __roc_api roc_bphy_dev_fini(struct roc_bphy *roc_bphy); + +#endif /* _ROC_BPHY_ */ diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index 63cc04044..4d7b53422 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev) idev->lmt_pf_func = 0; idev->lmt_base_addr = 0; idev->num_lmtlines = 0; + idev->bphy = NULL; __atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE); } diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index ff10a905c..384f667ea 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -7,6 +7,7 @@ /* Intra device related functions */ struct npa_lf; +struct roc_bphy; struct idev_cfg { uint16_t sso_pf_func; uint16_t npa_pf_func; @@ -16,6 +17,7 @@ struct idev_cfg { uint16_t lmt_pf_func; uint16_t num_lmtlines; uint64_t lmt_base_addr; + struct roc_bphy *bphy; }; /* Generic */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 0ad805dba..25083d9d4 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -20,6 +20,8 @@ INTERNAL { roc_bphy_cgx_set_link_state; roc_bphy_cgx_start_rxtx; roc_bphy_cgx_stop_rxtx; + roc_bphy_dev_fini; + roc_bphy_dev_init; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; -- 2.25.1