From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56339A0524; Mon, 31 May 2021 23:42:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5B36C410E2; Mon, 31 May 2021 23:42:05 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BD3BE410D7 for ; Mon, 31 May 2021 23:42:03 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeJBF002825; Mon, 31 May 2021 14:42:01 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=M1s4SIMWI1PSoSUatIQPj2YV3K0RjAIlp+pugI9LUqQ=; b=NTAU1PCSM5QY8OjFkqmzPN9NcSh/apg19A7tAcNNV6D86iJCvH80G57eWSeC3VqSBqOS kz7N+ybt2Rcki++UYluN8H2TnCpl2E/ZGxXYy/1+l1UFDwLW6dPm/KM0zwdc6f8mlWuW fhD5FHTJlXmJagtrWEsXNMIgIL3j8FO8iAyTfDqleU8918gcqFX5MMPxJCHAab2CTG/7 qndgIosKCCbd19da/E770krqOQzF+p+AS1tPZ9RZM2amvMH7CP2LElGH+1MPUdM6FzaK qxVpSNjfFZT/842tsYsKFf6MA7PhTs0+7815pjTHZaSveF8Z7TAxrXaVqr+pdn7oe+BJ nA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja11w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:01 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:41:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:41:59 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 44FDC3F7041; Mon, 31 May 2021 14:41:57 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:17 +0200 Message-ID: <20210531214142.30167-4-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: qt32av-jSSHnSPrsmYcoTSlJPUNtpG4H X-Proofpoint-ORIG-GUID: qt32av-jSSHnSPrsmYcoTSlJPUNtpG4H X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 03/28] common/cnxk: add support for getting link information X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for retrieving link information. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/roc_bphy_cgx.c | 38 ++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 70 +++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 9 ++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 118 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 5048a90de..c7ba53ede 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -205,3 +205,41 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx) return 0; } + +static bool +roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + return (lmac < MAX_LMACS_PER_CGX) && + (roc_cgx->lmac_bmap & BIT_ULL(lmac)); +} + +int +roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_link_info *info) +{ + uint64_t scr1, scr0; + int ret; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -EINVAL; + + if (!info) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS); + ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); + if (ret) + return ret; + + info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0); + info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0); + info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0); + info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0); + info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0); + info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0); + + return 0; +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 37b5c2742..bb1d903eb 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -9,6 +9,8 @@ #include "roc_api.h" +#define MAX_LMACS_PER_CGX 4 + struct roc_bphy_cgx { uint64_t bar0_pa; void *bar0_va; @@ -18,7 +20,75 @@ struct roc_bphy_cgx { pthread_mutex_t lock; } __plt_cache_aligned; +enum roc_bphy_cgx_eth_link_speed { + ROC_BPHY_CGX_ETH_LINK_SPEED_NONE, + ROC_BPHY_CGX_ETH_LINK_SPEED_10M, + ROC_BPHY_CGX_ETH_LINK_SPEED_100M, + ROC_BPHY_CGX_ETH_LINK_SPEED_1G, + ROC_BPHY_CGX_ETH_LINK_SPEED_2HG, + ROC_BPHY_CGX_ETH_LINK_SPEED_5G, + ROC_BPHY_CGX_ETH_LINK_SPEED_10G, + ROC_BPHY_CGX_ETH_LINK_SPEED_20G, + ROC_BPHY_CGX_ETH_LINK_SPEED_25G, + ROC_BPHY_CGX_ETH_LINK_SPEED_40G, + ROC_BPHY_CGX_ETH_LINK_SPEED_50G, + ROC_BPHY_CGX_ETH_LINK_SPEED_80G, + ROC_BPHY_CGX_ETH_LINK_SPEED_100G, + __MAX_ROC_BPHY_CGX_ETH_LINK_SPEED +}; + +enum roc_bphy_cgx_eth_link_fec { + ROC_BPHY_CGX_ETH_LINK_FEC_NONE, + ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R, + ROC_BPHY_CGX_ETH_LINK_FEC_RS, + __MAX_ROC_BPHY_CGX_ETH_LINK_FEC +}; + +enum roc_bphy_cgx_eth_link_mode { + ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, + __MAX_ROC_BPHY_CGX_ETH_LINK_MODE +}; + +struct roc_bphy_cgx_link_info { + bool link_up; + bool full_duplex; + enum roc_bphy_cgx_eth_link_speed speed; + bool an; + enum roc_bphy_cgx_eth_link_fec fec; + enum roc_bphy_cgx_eth_link_mode mode; +}; + __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); +__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac, + struct roc_bphy_cgx_link_info *info); + #endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index 42d0bce7a..c0550ae87 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -7,6 +7,7 @@ /* REQUEST ID types. Input to firmware */ enum eth_cmd_id { + ETH_CMD_GET_LINK_STS = 4, ETH_CMD_INTF_SHUTDOWN = 12, }; @@ -41,6 +42,14 @@ enum eth_cmd_own { /* struct eth_lnk_sts_s */ #define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15) +#define SCR0_ETH_LNK_STS_S_LINK_UP BIT_ULL(9) +#define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10) +#define SCR0_ETH_LNK_STS_S_SPEED GENMASK_ULL(14, 11) +#define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15) +#define SCR0_ETH_LNK_STS_S_AN BIT_ULL(25) +#define SCR0_ETH_LNK_STS_S_FEC GENMASK_ULL(27, 26) +#define SCR0_ETH_LNK_STS_S_LMAC_TYPE GENMASK_ULL(35, 28) +#define SCR0_ETH_LNK_STS_S_MODE GENMASK_ULL(43, 36) /* scratchx(1) CSR used for non-secure SW->ATF communication * This CSR acts as a command register diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 1db4d104a..466207f9d 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -11,6 +11,7 @@ INTERNAL { cnxk_logtype_tm; roc_bphy_cgx_dev_fini; roc_bphy_cgx_dev_init; + roc_bphy_cgx_get_linkinfo; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; -- 2.25.1