From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 504F4A034F; Mon, 7 Jun 2021 20:03:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5CE19410F9; Mon, 7 Jun 2021 20:03:09 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4337E410F8 for ; Mon, 7 Jun 2021 20:03:08 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 157I1bEM017524 for ; Mon, 7 Jun 2021 11:03:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=9uNdFlO2rM0Y7LQH0Jm3/+GmOqO3grJE2XsCL2JQ3PQ=; b=T26ey9hiTp8oNRrNuZqB/pydPXvxteVLlZ+5XVXOmpaUxH7w0EIVlOc+SidRXf5qUmC1 mzpkCxdni0DSXtjiHPMrKAjg3/z+kKHe9bGMZgk4xpvN42c+Jsn0TKASVbR9mhem8thX JTjyBIPfRpLDI+ps1+NmxeQ8+v7tE2pBq3o0ltZ2NxgRzqIfRWGshgE0P+30LMAViywD rQ4UPO+D1nrSqdpiikK9uZM4G3tSdi3+zoZIO4qcw7Z3iwfS2krqVuYi5xcTEfnIk2Q7 QB9ylxSgGuUyJ7GV6BHeCXjPSkt5byjK2X6TQVQOtPBUFRVxPV6fveADw6puBxW8MndE 9g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 391ecv2e84-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 07 Jun 2021 11:03:07 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Jun 2021 11:03:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 7 Jun 2021 11:03:05 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 633283F7040; Mon, 7 Jun 2021 11:03:03 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , Date: Mon, 7 Jun 2021 23:28:44 +0530 Message-ID: <20210607175943.31690-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210607175943.31690-1-ndabilpuram@marvell.com> References: <20210306153404.10781-1-ndabilpuram@marvell.com> <20210607175943.31690-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: Crkp9w763DtHxVTFWHVSBfNQS6-4gxxt X-Proofpoint-ORIG-GUID: Crkp9w763DtHxVTFWHVSBfNQS6-4gxxt X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-07_14:2021-06-04, 2021-06-07 signatures=0 Subject: [dpdk-dev] [PATCH v2 03/62] common/cnxk: fix batch alloc completion poll logic X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob The instruction generation was not correct due to fact that volatile suppose to use with ccode variable as well. Change the logic to use gcc atomic builtin to simplify and avoid explicit volatile from the code. Fixes: 81af26789316 ("common/cnxk: support NPA batch alloc/free") Signed-off-by: Jerin Jacob Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_npa.c | 2 +- drivers/common/cnxk/roc_npa.h | 30 +++++++++++++++--------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index f1e03b7..5ba6e81 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -236,7 +236,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Block size should be cache line aligned and in range of 128B-128KB */ if (block_size % ROC_ALIGN || block_size < 128 || - block_size > 128 * 1024) + block_size > ROC_NPA_MAX_BLOCK_SZ) return NPA_ERR_INVALID_BLOCK_SZ; pos = 0; diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 89f5c6f..59d6223 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -8,6 +8,7 @@ #define ROC_AURA_ID_MASK (BIT_ULL(16) - 1) #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1) +#define ROC_NPA_MAX_BLOCK_SZ (128 * 1024) #define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512 #define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS 15 @@ -219,6 +220,17 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf, return 0; } +static inline void +roc_npa_batch_alloc_wait(uint64_t *cache_line) +{ + /* Batch alloc status code is updated in bits [5:6] of the first word + * of the 128 byte cache line. + */ + while (((__atomic_load_n(cache_line, __ATOMIC_RELAXED) >> 5) & 0x3) == + ALLOC_CCODE_INVAL) + ; +} + static inline unsigned int roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num) { @@ -231,17 +243,10 @@ roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num) /* Check each ROC cache line one by one */ for (i = 0; i < num; i += (ROC_ALIGN >> 3)) { struct npa_batch_alloc_status_s *status; - int ccode; status = (struct npa_batch_alloc_status_s *)&aligned_buf[i]; - /* Status is updated in first 7 bits of each 128 byte cache - * line. Wait until the status gets updated. - */ - do { - ccode = (volatile int)status->ccode; - } while (ccode == ALLOC_CCODE_INVAL); - + roc_npa_batch_alloc_wait(&aligned_buf[i]); count += status->count; } @@ -261,16 +266,11 @@ roc_npa_aura_batch_alloc_extract(uint64_t *buf, uint64_t *aligned_buf, /* Check each ROC cache line one by one */ for (i = 0; i < num; i += (ROC_ALIGN >> 3)) { struct npa_batch_alloc_status_s *status; - int line_count, ccode; + int line_count; status = (struct npa_batch_alloc_status_s *)&aligned_buf[i]; - /* Status is updated in first 7 bits of each 128 byte cache - * line. Wait until the status gets updated. - */ - do { - ccode = (volatile int)status->ccode; - } while (ccode == ALLOC_CCODE_INVAL); + roc_npa_batch_alloc_wait(&aligned_buf[i]); line_count = status->count; -- 2.8.4