From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
	by inbox.dpdk.org (Postfix) with ESMTP id 2E41AA034F;
	Mon,  7 Jun 2021 20:09:05 +0200 (CEST)
Received: from [217.70.189.124] (localhost [127.0.0.1])
	by mails.dpdk.org (Postfix) with ESMTP id A8A3441162;
	Mon,  7 Jun 2021 20:05:35 +0200 (CEST)
Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com
 [67.231.156.173])
 by mails.dpdk.org (Postfix) with ESMTP id B09AA4114C
 for <dev@dpdk.org>; Mon,  7 Jun 2021 20:05:34 +0200 (CEST)
Received: from pps.filterd (m0045851.ppops.net [127.0.0.1])
 by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id
 157I1bsm017517 for <dev@dpdk.org>; Mon, 7 Jun 2021 11:05:34 -0700
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;
 h=from : to : cc :
 subject : date : message-id : in-reply-to : references : mime-version :
 content-type; s=pfpt0220; bh=tVdbI+yvWRwyRwSPPKhZMlaGYB6FcqygKnJ/8+PMpTU=;
 b=XJK/Azfgr4QKj7426cIOVKZUIExC2sFf9vY1q019PuAZ6i8RB/h/y7ZMTfeys09eIvhO
 7p9k6rhVsP+CytEqm51oV03yIJzPxW0S3tHBrkteDdjB69ALShXzdDTBOCp7kWnQ0rL3
 sQYG/JyNuA6j0gMcoEv4VZq3jVbK0+04hgWtAamBXfO5MqsBNWQ7EcQJntySL8ZVBCaF
 PGz5zuzwhATBcyticBiFfKOWVbgLpqTQLL5+oGy5VghgGr8cC4DmZvkdaMpgnm98dIDg
 53U+C8pO9klU44sucAeMsOh9Qun+0QxtnGeiVf+mM2kldwyluAEYvcY+LZCy/FyhW9vd sA== 
Received: from dc5-exch02.marvell.com ([199.233.59.182])
 by mx0b-0016f401.pphosted.com with ESMTP id 391ecv2ep9-1
 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)
 for <dev@dpdk.org>; Mon, 07 Jun 2021 11:05:34 -0700
Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com
 (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;
 Mon, 7 Jun 2021 11:05:32 -0700
Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com
 (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend
 Transport; Mon, 7 Jun 2021 11:05:32 -0700
Received: from hyd1588t430.marvell.com (unknown [10.29.52.204])
 by maili.marvell.com (Postfix) with ESMTP id AABD63F703F;
 Mon,  7 Jun 2021 11:05:29 -0700 (PDT)
From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: <dev@dpdk.org>
CC: <jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,
 <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,
 <psatheesh@marvell.com>, <asekhar@marvell.com>
Date: Mon, 7 Jun 2021 23:29:29 +0530
Message-ID: <20210607175943.31690-49-ndabilpuram@marvell.com>
X-Mailer: git-send-email 2.8.4
In-Reply-To: <20210607175943.31690-1-ndabilpuram@marvell.com>
References: <20210306153404.10781-1-ndabilpuram@marvell.com>
 <20210607175943.31690-1-ndabilpuram@marvell.com>
MIME-Version: 1.0
Content-Type: text/plain
X-Proofpoint-GUID: rh_IuCXzCnrU4e4KySd_e5ojkfuOPMwR
X-Proofpoint-ORIG-GUID: rh_IuCXzCnrU4e4KySd_e5ojkfuOPMwR
X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761
 definitions=2021-06-07_14:2021-06-04,
 2021-06-07 signatures=0
Subject: [dpdk-dev] [PATCH v2 48/62] net/cnxk: add support to configure npc
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

From: Kiran Kumar K <kirankumark@marvell.com>

Adding support to configure NPC on device initialization. This involves
reading the MKEX and initializing the necessary data.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c         | 25 ++++++++++++++++++++++---
 drivers/net/cnxk/cnxk_ethdev.h         |  3 +++
 drivers/net/cnxk/cnxk_ethdev_devargs.c |  3 +++
 3 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 280ef42..b4e049b 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -8,7 +8,8 @@ nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
 {
 	uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
 
-	if (roc_nix_is_vf_or_sdp(&dev->nix))
+	if (roc_nix_is_vf_or_sdp(&dev->nix) ||
+	    dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
 		capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
 
 	return capa;
@@ -120,6 +121,7 @@ nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 
 	/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
 	if (roc_model_is_cn96_Ax() &&
+	    dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
 	    (fc_cfg.mode == RTE_FC_FULL || fc_cfg.mode == RTE_FC_RX_PAUSE)) {
 		fc_cfg.mode =
 				(fc_cfg.mode == RTE_FC_FULL ||
@@ -419,8 +421,10 @@ cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
 
 	dev->ethdev_rss_hf = ethdev_rss;
 
-	if (ethdev_rss & ETH_RSS_L2_PAYLOAD)
+	if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
+	    dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
 		flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
+	}
 
 	if (ethdev_rss & ETH_RSS_C_VLAN)
 		flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
@@ -820,11 +824,18 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 	roc_nix_err_intr_ena_dis(nix, true);
 	roc_nix_ras_intr_ena_dis(nix, true);
 
-	if (nix->rx_ptp_ena) {
+	if (nix->rx_ptp_ena &&
+	    dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
 		plt_err("Both PTP and switch header enabled");
 		goto free_nix_lf;
 	}
 
+	rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type);
+	if (rc) {
+		plt_err("Failed to enable switch type nix_lf rc=%d", rc);
+		goto free_nix_lf;
+	}
+
 	/* Setup LSO if needed */
 	rc = nix_lso_fmt_setup(dev);
 	if (rc) {
@@ -1277,6 +1288,11 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
 	dev->speed_capa = nix_get_speed_capa(dev);
 
 	/* Initialize roc npc */
+	dev->npc.roc_nix = nix;
+	rc = roc_npc_init(&dev->npc);
+	if (rc)
+		goto free_mac_addrs;
+
 	plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
 		    " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
 		    eth_dev->data->port_id, roc_nix_get_pf(nix),
@@ -1310,6 +1326,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
 
 	roc_nix_npc_rx_ena_dis(nix, false);
 
+	/* Disable and free rte_flow entries */
+	roc_npc_fini(&dev->npc);
+
 	/* Disable link status events */
 	roc_nix_mac_link_event_start_stop(nix, false);
 
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 1ca52bc..e3b0bc1 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -133,6 +133,9 @@ struct cnxk_eth_dev {
 	/* ROC NIX */
 	struct roc_nix nix;
 
+	/* ROC NPC */
+	struct roc_npc npc;
+
 	/* ROC RQs, SQs and CQs */
 	struct roc_nix_rq *rqs;
 	struct roc_nix_sq *sqs;
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index 4af2803..7fd06eb 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -150,6 +150,9 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	dev->nix.rss_tag_as_xor = !!rss_tag_as_xor;
 	dev->nix.max_sqb_count = sqb_count;
 	dev->nix.reta_sz = reta_sz;
+	dev->npc.flow_prealloc_size = flow_prealloc_size;
+	dev->npc.flow_max_priority = flow_max_priority;
+	dev->npc.switch_header_type = switch_header_type;
 	return 0;
 
 exit:
-- 
2.8.4