From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83426A0C46; Fri, 18 Jun 2021 12:39:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AC1F4410F4; Fri, 18 Jun 2021 12:39:28 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id AF448410F3 for ; Fri, 18 Jun 2021 12:39:27 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15IAZPg9032282 for ; Fri, 18 Jun 2021 03:39:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=9uNdFlO2rM0Y7LQH0Jm3/+GmOqO3grJE2XsCL2JQ3PQ=; b=Wi3o/xfHhHVJ5Rg/d2MCoc5JpHMfuYl3cxGBD2T19V6d0Q/q/URcjmVWsQw+KhCe6qzO tfoAo8ZGSI7XNdgaLAbQ5KfRKiheVPR7fHM/anp5bUYcWHulWBamE6lD3us4j9lrVztI ikKcaWlayw3XZAAWkB03IsLy/0UUnuLFNc5SVP9BXo86G6HMFsQpsHHfa7/nhjaAMBq6 AVnhBIcM35iUayGrWJvscBW82aGzjvhKmrO2f4SQSetuITUzZ4StDur/VeK296kFGSrr oILoiZONN5tOd1pwrG7QJMA1WQU+rLflpeKYYWvW8MnR3CgoiLgvsC2vJe0mYIEvpAH2 jw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 398r750cxn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 18 Jun 2021 03:39:26 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 18 Jun 2021 03:39:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 18 Jun 2021 03:39:25 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 9720B5B6A19; Fri, 18 Jun 2021 03:38:34 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , , Date: Fri, 18 Jun 2021 16:06:41 +0530 Message-ID: <20210618103741.26526-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210618103741.26526-1-ndabilpuram@marvell.com> References: <20210306153404.10781-1-ndabilpuram@marvell.com> <20210618103741.26526-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: JQ-IYBHgn25c4Yz0YkEhzAJFTMckyNOE X-Proofpoint-GUID: JQ-IYBHgn25c4Yz0YkEhzAJFTMckyNOE X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-18_04:2021-06-18, 2021-06-18 signatures=0 Subject: [dpdk-dev] [PATCH v3 02/62] common/cnxk: fix batch alloc completion poll logic X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob The instruction generation was not correct due to fact that volatile suppose to use with ccode variable as well. Change the logic to use gcc atomic builtin to simplify and avoid explicit volatile from the code. Fixes: 81af26789316 ("common/cnxk: support NPA batch alloc/free") Signed-off-by: Jerin Jacob Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_npa.c | 2 +- drivers/common/cnxk/roc_npa.h | 30 +++++++++++++++--------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index f1e03b7..5ba6e81 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -236,7 +236,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, /* Block size should be cache line aligned and in range of 128B-128KB */ if (block_size % ROC_ALIGN || block_size < 128 || - block_size > 128 * 1024) + block_size > ROC_NPA_MAX_BLOCK_SZ) return NPA_ERR_INVALID_BLOCK_SZ; pos = 0; diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 89f5c6f..59d6223 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -8,6 +8,7 @@ #define ROC_AURA_ID_MASK (BIT_ULL(16) - 1) #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1) +#define ROC_NPA_MAX_BLOCK_SZ (128 * 1024) #define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512 #define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS 15 @@ -219,6 +220,17 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf, return 0; } +static inline void +roc_npa_batch_alloc_wait(uint64_t *cache_line) +{ + /* Batch alloc status code is updated in bits [5:6] of the first word + * of the 128 byte cache line. + */ + while (((__atomic_load_n(cache_line, __ATOMIC_RELAXED) >> 5) & 0x3) == + ALLOC_CCODE_INVAL) + ; +} + static inline unsigned int roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num) { @@ -231,17 +243,10 @@ roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num) /* Check each ROC cache line one by one */ for (i = 0; i < num; i += (ROC_ALIGN >> 3)) { struct npa_batch_alloc_status_s *status; - int ccode; status = (struct npa_batch_alloc_status_s *)&aligned_buf[i]; - /* Status is updated in first 7 bits of each 128 byte cache - * line. Wait until the status gets updated. - */ - do { - ccode = (volatile int)status->ccode; - } while (ccode == ALLOC_CCODE_INVAL); - + roc_npa_batch_alloc_wait(&aligned_buf[i]); count += status->count; } @@ -261,16 +266,11 @@ roc_npa_aura_batch_alloc_extract(uint64_t *buf, uint64_t *aligned_buf, /* Check each ROC cache line one by one */ for (i = 0; i < num; i += (ROC_ALIGN >> 3)) { struct npa_batch_alloc_status_s *status; - int line_count, ccode; + int line_count; status = (struct npa_batch_alloc_status_s *)&aligned_buf[i]; - /* Status is updated in first 7 bits of each 128 byte cache - * line. Wait until the status gets updated. - */ - do { - ccode = (volatile int)status->ccode; - } while (ccode == ALLOC_CCODE_INVAL); + roc_npa_batch_alloc_wait(&aligned_buf[i]); line_count = status->count; -- 2.8.4