From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 44894A0C46; Fri, 18 Jun 2021 12:46:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 09F4D41155; Fri, 18 Jun 2021 12:42:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id F102D4116C for ; Fri, 18 Jun 2021 12:42:04 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15IAZPhu003485 for ; Fri, 18 Jun 2021 03:42:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=duzUeAP2t4xrYKKdj/XAtDCNBGiUyHRv6DM6xhyrN84=; b=chLuoh4HE7wVKXwmKzg7iSOzOdK6YGhUnoWSZgiGo3QOlkkcIYmnYtiXYeyTgu/lQkZj +YrUAEMRFbJtHMnjIlRkP8tRpZZR+3lVrSm05MmRGQo0LVw3V2cVPSEs5OS33Xwx4DR6 mO3q6fWmV+/Osw/mJCEqDgGVjAjsM4N8eZEZNbBn4c2iF2wXEVs88ZP2hJdRM1Hf2zQA EPGuJM8re9q2+CSUuvgh8vH/5brXLTUfT6sGJHf/bl2eJHu9UiqzlyoXqAZE7M+C/p/h e+QtVjpzeCopE48/m3tPwaL7jtcMFNtX/LomVOMUI4X6DnSw0htH4KUDK8pAUTuFODbQ OA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 397udry7q3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 18 Jun 2021 03:42:04 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 18 Jun 2021 03:42:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 18 Jun 2021 03:42:02 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id EFB015B6A3A; Fri, 18 Jun 2021 03:41:36 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , , Date: Fri, 18 Jun 2021 16:07:38 +0530 Message-ID: <20210618103741.26526-60-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210618103741.26526-1-ndabilpuram@marvell.com> References: <20210306153404.10781-1-ndabilpuram@marvell.com> <20210618103741.26526-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: kbHrtqYGjT-7PCOR59oEwKR0mSOD-jfC X-Proofpoint-GUID: kbHrtqYGjT-7PCOR59oEwKR0mSOD-jfC X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-18_04:2021-06-18, 2021-06-18 signatures=0 Subject: [dpdk-dev] [PATCH v3 59/62] net/cnxk: add read clock operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Patch implements read raw clock operation for cn9k and cn10k. Signed-off-by: Sunil Kumar Kori --- doc/guides/nics/features/cnxk.ini | 2 ++ drivers/net/cnxk/cnxk_ethdev.c | 1 + drivers/net/cnxk/cnxk_ethdev.h | 1 + drivers/net/cnxk/cnxk_ptp.c | 17 +++++++++++++++++ 4 files changed, 21 insertions(+) diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index eba4107..5874531 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -32,6 +32,8 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Timesync = Y +Timestamp offload = Y Basic stats = Y Stats per queue = Y Extended stats = Y diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index cac8ddf..e1373cf 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1253,6 +1253,7 @@ struct eth_dev_ops cnxk_eth_dev_ops = { .timesync_read_time = cnxk_nix_timesync_read_time, .timesync_write_time = cnxk_nix_timesync_write_time, .timesync_adjust_time = cnxk_nix_timesync_adjust_time, + .read_clock = cnxk_nix_read_clock, }; static int diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 4214365..fa6f16f 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -323,6 +323,7 @@ int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev, const struct timespec *ts); int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta); int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev); +int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock); uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev); diff --git a/drivers/net/cnxk/cnxk_ptp.c b/drivers/net/cnxk/cnxk_ptp.c index 52f6eb1..449489f 100644 --- a/drivers/net/cnxk/cnxk_ptp.c +++ b/drivers/net/cnxk/cnxk_ptp.c @@ -4,6 +4,23 @@ #include "cnxk_ethdev.h" +int +cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + + /* This API returns the raw PTP HI clock value. Since LFs do not + * have direct access to PTP registers and it requires mbox msg + * to AF for this value. In fastpath reading this value for every + * packet (which involes mbox call) becomes very expensive, hence + * we should be able to derive PTP HI clock value from tsc by + * using freq_mult and clk_delta calculated during configure stage. + */ + *clock = (rte_get_tsc_cycles() + dev->clk_delta) * dev->clk_freq_mult; + + return 0; +} + /* This function calculates two parameters "clk_freq_mult" and * "clk_delta" which is useful in deriving PTP HI clock from * timestamp counter (tsc) value. -- 2.8.4