From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 24B5DA0547; Mon, 21 Jun 2021 17:07:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D18CF41215; Mon, 21 Jun 2021 17:05:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C56D3411B9 for ; Mon, 21 Jun 2021 17:05:47 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15LF5EUi008501; Mon, 21 Jun 2021 08:05:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=dPLTINyO74HBOj3233+HmvUS6gLP7USD24NUpujgArw=; b=NcF3ycXbCH1Wq5Uhf+tEB6qRByO9339Zmnz/C9CbcszYp3rlzxJqIlAUjMO7zjl9UpPY naMMkLzX9rNAzs3K8BxyHa9xjGheyBNKe4Y467oool3U5FHdD8qkxCWAU7PPIrm/14jt nw2rJE4yGwNOVFUbMRkaf0fgtl0RVYQ6A8/bcQCS0NRblcvjzbOKkdpKCJfwjUBQrS+Z wuP/8fxGvP+J/EC+syQKKXD9gJQ1e9Nx9OesGzdy+rI5h+J6gbNP/JON3YOvko/AqFwU 9Y07ALNhusb0ScyPmISH+eZpm+sLQ6xwoK2NrYWoJqurw9nfWNIz5qMji2EFO4bubycX 7w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 39aj2xja1t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 21 Jun 2021 08:05:44 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 21 Jun 2021 08:05:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 21 Jun 2021 08:05:43 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id B262B3F705B; Mon, 21 Jun 2021 08:05:40 -0700 (PDT) From: Tomasz Duszynski To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman CC: , , Tomasz Duszynski , Jakub Palider , Jerin Jacob Date: Mon, 21 Jun 2021 17:04:33 +0200 Message-ID: <20210621150449.19070-17-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210621150449.19070-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> <20210621150449.19070-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: hHPlJl-SSrGHrsD7nla_GQQQ3EEVjht7 X-Proofpoint-ORIG-GUID: hHPlJl-SSrGHrsD7nla_GQQQ3EEVjht7 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-21_06:2021-06-21, 2021-06-21 signatures=0 Subject: [dpdk-dev] [PATCH v3 16/32] common/cnxk: support for baseband PHY irq setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for initializing baseband phy irqs. While at it also add support for reverting back to the default state. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski Reviewed-by: Jerin Jacob --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_bphy_irq.c | 96 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 27 +++++++++ drivers/common/cnxk/version.map | 2 + 4 files changed, 126 insertions(+) create mode 100644 drivers/common/cnxk/roc_bphy_irq.c create mode 100644 drivers/common/cnxk/roc_bphy_irq.h diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 946b98f46..c0ec54932 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -13,6 +13,7 @@ deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( 'roc_bphy.c', 'roc_bphy_cgx.c', + 'roc_bphy_irq.c', 'roc_dev.c', 'roc_idev.c', 'roc_irq.c', diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c new file mode 100644 index 000000000..c57506542 --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +#include +#include +#include + +#include "roc_api.h" +#include "roc_bphy_irq.h" + +#define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz" +#define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr" + +#define ROC_BPHY_IOC_MAGIC 0xF3 +#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t) +#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t) + +struct roc_bphy_irq_chip * +roc_bphy_intr_init(void) +{ + struct roc_bphy_irq_chip *irq_chip; + uint64_t max_irq, i, avail_irqs; + int fd, ret; + + fd = open(ROC_BPHY_CTR_DEV_PATH, O_RDWR | O_SYNC); + if (fd < 0) { + plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH); + return NULL; + } + + ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_MAX_IRQ, &max_irq); + if (ret < 0) { + plt_err("Failed to get max irq number via ioctl"); + goto err_ioctl; + } + + ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ, &avail_irqs); + if (ret < 0) { + plt_err("Failed to get available irqs bitmask via ioctl"); + goto err_ioctl; + } + + irq_chip = plt_zmalloc(sizeof(*irq_chip), 0); + if (irq_chip == NULL) { + plt_err("Failed to alloc irq_chip"); + goto err_alloc_chip; + } + + irq_chip->intfd = fd; + irq_chip->max_irq = max_irq; + irq_chip->avail_irq_bmask = avail_irqs; + irq_chip->irq_vecs = + plt_zmalloc(irq_chip->max_irq * sizeof(*irq_chip->irq_vecs), 0); + if (irq_chip->irq_vecs == NULL) { + plt_err("Failed to alloc irq_chip irq_vecs"); + goto err_alloc_irq; + } + + irq_chip->mz_name = plt_zmalloc(strlen(ROC_BPHY_MEMZONE_NAME) + 1, 0); + if (irq_chip->mz_name == NULL) { + plt_err("Failed to alloc irq_chip name"); + goto err_alloc_name; + } + plt_strlcpy(irq_chip->mz_name, ROC_BPHY_MEMZONE_NAME, + strlen(ROC_BPHY_MEMZONE_NAME) + 1); + + for (i = 0; i < irq_chip->max_irq; i++) { + irq_chip->irq_vecs[i].fd = -1; + irq_chip->irq_vecs[i].handler_cpu = -1; + } + + return irq_chip; + +err_alloc_name: + plt_free(irq_chip->irq_vecs); + +err_alloc_irq: + plt_free(irq_chip); + +err_ioctl: +err_alloc_chip: + close(fd); + return NULL; +} + +void +roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip) +{ + if (irq_chip == NULL) + return; + + close(irq_chip->intfd); + plt_free(irq_chip->mz_name); + plt_free(irq_chip->irq_vecs); + plt_free(irq_chip); +} diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h new file mode 100644 index 000000000..b5200786b --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_BPHY_IRQ_ +#define _ROC_BPHY_IRQ_ + +struct roc_bphy_irq_vec { + int fd; + int handler_cpu; + void (*handler)(int irq_num, void *isr_data); + void *isr_data; +}; + +struct roc_bphy_irq_chip { + struct roc_bphy_irq_vec *irq_vecs; + uint64_t max_irq; + uint64_t avail_irq_bmask; + int intfd; + int n_handlers; + char *mz_name; +}; + +__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void); +__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip); + +#endif /* _ROC_BPHY_IRQ_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 25083d9d4..483e52018 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -22,6 +22,8 @@ INTERNAL { roc_bphy_cgx_stop_rxtx; roc_bphy_dev_fini; roc_bphy_dev_init; + roc_bphy_intr_fini; + roc_bphy_intr_init; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; -- 2.25.1