From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 02F7CA0C41; Wed, 23 Jun 2021 06:52:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 27CCE411B9; Wed, 23 Jun 2021 06:49:38 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 762594113E for ; Wed, 23 Jun 2021 06:49:37 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15N4k7nd025556 for ; Tue, 22 Jun 2021 21:49:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=fLK6P1BRPtzMuBf62lcpxvHvnU6A0UPi5JpRTIrJyi0=; b=U5VLryeHYnvO6bX+/tNPa5vyTUk8N6H2VZ9Y6Cto31PNmsgk7ezv1bfEJIeWMdjro+ze zBJ51RPWjB/Sg0Z0WuJf/pdNfROLvhpc8UNc4NzbEbePz3KzjeYoF+B/wPu/GOqi4wT3 dknxgluSKX4XVV9Gju8YuhMA4XXIFIPfJnmZcYCKKuZDpUHyqYAjqAO6iRGxpzQOmszi 4sYKCeX4YyGku6AT16zuvh4QnN5fjx96amwTT6r5rC7mKYYJG9FTq7DE6w8MlJmOhKXo rOnkhBaxJn1ErlAq6g4evTvhunJ0VBBhlPIDz7yRZbRsvfGOKBNshsQwWc1/8q4pt0Z3 OA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gsj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jun 2021 21:49:36 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 22 Jun 2021 21:49:34 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 22 Jun 2021 21:49:34 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 407ED5B6936; Tue, 22 Jun 2021 21:49:32 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , , Date: Wed, 23 Jun 2021 10:16:42 +0530 Message-ID: <20210623044702.4240-43-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210623044702.4240-1-ndabilpuram@marvell.com> References: <20210306153404.10781-1-ndabilpuram@marvell.com> <20210623044702.4240-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: yilihKrkZsae6xZJC__29VsfMNzuGCVy X-Proofpoint-GUID: yilihKrkZsae6xZJC__29VsfMNzuGCVy X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-23_01:2021-06-22, 2021-06-23 signatures=0 Subject: [dpdk-dev] [PATCH v4 42/62] net/cnxk: add validation API for mempool ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori cn9k and cn10k supports platform specific mempool ops. This patch implements API to validate whether given mempool ops is supported or not. Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_ethdev.c | 1 + drivers/net/cnxk/cnxk_ethdev.h | 1 + drivers/net/cnxk/cnxk_ethdev_ops.c | 11 +++++++++++ 3 files changed, 13 insertions(+) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 1ff3afa..77bbab6 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1195,6 +1195,7 @@ struct eth_dev_ops cnxk_eth_dev_ops = { .get_module_eeprom = cnxk_nix_get_module_eeprom, .rx_queue_intr_enable = cnxk_nix_rx_queue_intr_enable, .rx_queue_intr_disable = cnxk_nix_rx_queue_intr_disable, + .pool_ops_supported = cnxk_nix_pool_ops_supported, }; static int diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index a01b72a..e6dac95 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -261,6 +261,7 @@ int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id); int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id); +int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool); int cnxk_nix_configure(struct rte_eth_dev *eth_dev); int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index 45683dd..7f46551 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -617,3 +617,14 @@ cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, roc_nix_rx_queue_intr_disable(&dev->nix, rx_queue_id); return 0; } + +int +cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool) +{ + RTE_SET_USED(eth_dev); + + if (!strcmp(pool, rte_mbuf_platform_mempool_ops())) + return 0; + + return -ENOTSUP; +} -- 2.8.4