From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A126A0A0C; Mon, 28 Jun 2021 18:35:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BED734115F; Mon, 28 Jun 2021 18:34:51 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 8109641151 for ; Mon, 28 Jun 2021 18:34:50 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10029"; a="206165914" X-IronPort-AV: E=Sophos;i="5.83,306,1616482800"; d="scan'208";a="206165914" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2021 09:34:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,306,1616482800"; d="scan'208";a="456395628" Received: from silpixa00399302.ir.intel.com ([10.237.214.136]) by fmsmga008.fm.intel.com with ESMTP; 28 Jun 2021 09:34:47 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, fiona.trahe@intel.com, roy.fan.zhang@intel.com, Arek Kusztal Date: Mon, 28 Jun 2021 17:34:26 +0100 Message-Id: <20210628163434.77741-9-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20210628163434.77741-1-arkadiuszx.kusztal@intel.com> References: <20210628163434.77741-1-arkadiuszx.kusztal@intel.com> Subject: [dpdk-dev] [PATCH v2 08/16] crypto/qat: add aes gcm in ucs spc mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds AES-GCM algorithm that works in UCS (Unified crypto slice) SPC(Single-Pass) mode. Signed-off-by: Arek Kusztal --- drivers/crypto/qat/qat_sym.c | 32 ++++++++++++++++++++-------- drivers/crypto/qat/qat_sym_session.c | 9 ++++---- 2 files changed, 27 insertions(+), 14 deletions(-) diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index eef4a886c5..00fc4d6b1a 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -217,6 +217,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, int ret = 0; struct qat_sym_session *ctx = NULL; struct icp_qat_fw_la_cipher_req_params *cipher_param; + struct icp_qat_fw_la_cipher_20_req_params *cipher_param20; struct icp_qat_fw_la_auth_req_params *auth_param; register struct icp_qat_fw_la_bulk_req *qat_req; uint8_t do_auth = 0, do_cipher = 0, do_aead = 0; @@ -286,6 +287,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req)); qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op; cipher_param = (void *)&qat_req->serv_specif_rqpars; + cipher_param20 = (void *)&qat_req->serv_specif_rqpars; auth_param = (void *)((uint8_t *)cipher_param + ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET); @@ -563,13 +565,17 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, cipher_param->cipher_length = 0; } - if (do_auth || do_aead) { - auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset( + if (!ctx->is_single_pass) { + /* Do not let to owerwrite spc_aad len */ + if (do_auth || do_aead) { + auth_param->auth_off = + (uint32_t)rte_pktmbuf_iova_offset( op->sym->m_src, auth_ofs) - src_buf_start; - auth_param->auth_len = auth_len; - } else { - auth_param->auth_off = 0; - auth_param->auth_len = 0; + auth_param->auth_len = auth_len; + } else { + auth_param->auth_off = 0; + auth_param->auth_len = 0; + } } qat_req->comn_mid.dst_length = @@ -675,10 +681,18 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, } if (ctx->is_single_pass) { - /* Handle Single-Pass GCM */ - cipher_param->spc_aad_addr = op->sym->aead.aad.phys_addr; - cipher_param->spc_auth_res_addr = + if (ctx->is_ucs) { + /* GEN 4 */ + cipher_param20->spc_aad_addr = + op->sym->aead.aad.phys_addr; + cipher_param20->spc_auth_res_addr = op->sym->aead.digest.phys_addr; + } else { + cipher_param->spc_aad_addr = + op->sym->aead.aad.phys_addr; + cipher_param->spc_auth_res_addr = + op->sym->aead.digest.phys_addr; + } } else if (ctx->is_single_pass_gmac && op->sym->auth.data.length <= QAT_AES_GMAC_SPC_MAX_SIZE) { /* Handle Single-Pass AES-GMAC */ diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index fd6fe4423d..019c9f4f02 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -898,16 +898,15 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, if (qat_dev_gen == QAT_GEN4) session->is_ucs = 1; - if (session->cipher_iv.length == 0) { session->cipher_iv.length = AES_GCM_J0_LEN; break; } session->is_iv12B = 1; - if (qat_dev_gen == QAT_GEN3) { - qat_sym_session_handle_single_pass(session, - aead_xform); - } + if (qat_dev_gen < QAT_GEN3) + break; + qat_sym_session_handle_single_pass(session, + aead_xform); break; case RTE_CRYPTO_AEAD_AES_CCM: if (qat_sym_validate_aes_key(aead_xform->key.length, -- 2.30.2