From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93A48A0A0C; Fri, 2 Jul 2021 11:15:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D81D44138E; Fri, 2 Jul 2021 11:15:21 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2064.outbound.protection.outlook.com [40.107.237.64]) by mails.dpdk.org (Postfix) with ESMTP id 8E8DB41381; Fri, 2 Jul 2021 11:15:19 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dMeo6gY2Ls3VzS1G1gQwVTbCHuoQmIL6L3u2FbRnNQMDwwcpTQpvXhjaNdJ+pvc83JB+WceFjvTslO3YyQmBfccVWP48A1T7EYuPzjRznB5lwchymeqjBb/Un4Bz4YOqheaxqN3ZoeKG6J9lHnkLdd8ZvzsG8gnK2vcbP4eSQPSfkSiQz7o9u4AZBUqUNZo0TApv/eA/TTLKAPn/jr9Krl3Cce7mAgg3QRkirCa/WeVTFqJpwI0raEXY/K8DBvvGdwcCNCTIJDJjq6PMjQuMNH3UwXacYrn0XWcyDGPoEnQVbblGtdeEKrhGJfznt2UM6Enkog6lKJV0zpqQaAeRMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Fo+XtsiRGR3dSaMu5oQt9+Y64SGUJzhtNopCjeTg7Y0=; b=GxL32lV3whjQfYpx9tz+1iOA/iO3iUM8+zFJCSspuJ/iWmYfwOno/DPPdxNvs2BXKKZ/KmsyhFzUzchYiG+IUDHQAWLwSKkkRASD4ngcyySMMdFT6lsPVGCJvG83caoiNPIu1oSMek/F0La820Lq6oapW2VdYMLLGDfnZ/pUA+1fAf4/Lom3Kwa9tpOYL075bHnukqyjLvquSGBt4WC05Lenlk860c7vBlhjpXdHvsyFdy1WzGvbtLqOjC46ydiMwcyspvJwudkbtwD8Sb+h1ZrSu0MLL6pwmpwVyV9sXB3Cbrd9BPMy8cwSpVwn00IP0UC4gWnXqr7/NxbIQrLAIg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Fo+XtsiRGR3dSaMu5oQt9+Y64SGUJzhtNopCjeTg7Y0=; b=ZeamzY1F5OQ+TbUG55pq2n0Pw4CdxbachWmPnlMLoqpPmL5PdC2Vb26EWu3IAHAIR4ROWGV7VTTVowDfb6qeXt+cfWo52vVWW3icpRnWcLmtp/4N+DIlI/rZ+ns3TRULSq+QhWwEDzkskOY/7QuyjDYLolvq78YOGNxhTEPTiL4+0KIoETp429YWYgeNjkSwdgVM+hD8zbc86mEgIJlAIIPCw6HiwYuUquIfIHnfEBDWizN2fIRiGErPd0lzhIdyb/Vx3yQxod+9muZNVj8KGhbIkE2E6KYmJB3VydbYE4WNUjmm9dTeRhGanHLfVjW0KnZZk9QVwtYsMDyrOXXJsQ== Received: from DS7PR05CA0012.namprd05.prod.outlook.com (2603:10b6:5:3b9::17) by BN9PR12MB5366.namprd12.prod.outlook.com (2603:10b6:408:103::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.23; Fri, 2 Jul 2021 09:15:18 +0000 Received: from DM6NAM11FT048.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b9:cafe::8c) by DS7PR05CA0012.outlook.office365.com (2603:10b6:5:3b9::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4308.7 via Frontend Transport; Fri, 2 Jul 2021 09:15:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT048.mail.protection.outlook.com (10.13.173.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4287.22 via Frontend Transport; Fri, 2 Jul 2021 09:15:17 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 2 Jul 2021 09:15:14 +0000 From: Shun Hao To: , , , , Li Zhang CC: , , , , Date: Fri, 2 Jul 2021 12:14:45 +0300 Message-ID: <20210702091446.24635-4-shunh@nvidia.com> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20210702091446.24635-1-shunh@nvidia.com> References: <20210702091446.24635-1-shunh@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5b46c1bc-01b8-4d5f-0001-08d93d39e8ec X-MS-TrafficTypeDiagnostic: BN9PR12MB5366: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: w0gyPr0GfbFe3FV1C+9wLF/9z6vMUxKofYSFcMyUCTIjV5eZCEJnmDOEoDUBjaWOqELviVLAodWE84P5earoqiEvDH+FZFTgL+sT2kf+N1Akn9j4ElbGtXX+rZEGgUV9UT5LRNzPI4/6mTNHs1xjGsEb+5ID3j2yHQBbtE5gAVDY9BXcDRJnAYbExQoucA9O4r0q1bkajFuq+XkYnWbgu+wApl7j/O2cy+c3nLQYiDPno15QIbxUwn+wTbC9Qnn98+8wIj/O29TWN291qA39V4aRE2CdjxWvcRxu9e5WcLh6aeHE8w+J/97ixJGRmLRFizyehEqXfhtVfiN8OlrAulXGiABH5gOjvJAVm40PfUyGO/Q5TmvZOwZ7ld6U3Cih8/p09a6T4f7jqyhbFGhny33oyu3klIwkV7sA381Y3YtyeTvWWQ+s9iByWz1pF5Zkps763N/00HLZNWbGcckQwit6v5eG6jN81UTKd4chxQti8/S5gIHtMdPnT3382jmwqFY2jaeW/q4xBNgfVOUTOriSHCo6gIjf+LJfyrloBpYLuUluLto2/FS9zt/GW9yLJsXwY3IYfYHR3vneFZ8pSl+sGrrT9mpQyi0eIP8oC9ZdHvv2T6K5Fy/pOXgk4mRVTR5NM1bGWrgjnHfo85gW1ez6zhMy0drNQOFr1Jwfcxh6OlWjJw9orRQCb5bospHW0Aq8iQ0ICTl/+Q+UziLeDw== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(136003)(396003)(39860400002)(376002)(46966006)(36840700001)(426003)(6286002)(6636002)(2616005)(1076003)(54906003)(4326008)(55016002)(47076005)(2906002)(82310400003)(336012)(36860700001)(26005)(82740400003)(70586007)(16526019)(186003)(316002)(36906005)(6666004)(7636003)(83380400001)(8676002)(7696005)(5660300002)(8936002)(478600001)(110136005)(86362001)(356005)(70206006)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2021 09:15:17.8807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b46c1bc-01b8-4d5f-0001-08d93d39e8ec X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5366 Subject: [dpdk-dev] [PATCH v1 3/4] net/mlx5: fix meter flow direction check X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When preparing prefix flow using ASO meter, if it's tx flow, need to make meter action the first one. Currently the check of flow direction in switch domain is incorrect that it checks the flow dev port only. This adds the fix for the check that if there's port_id match item in flow, use that port_id as src port to determine flow direction. Fixes: c99b4f8bc2f1 ("net/mlx5: support ASO meter action") Cc: stable@dpdk.org Signed-off-by: Shun Hao Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow.c | 83 ++++++++++++++++++++++-------------- 1 file changed, 50 insertions(+), 33 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 3b7c94d92f..c27f6197a0 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -4740,12 +4740,12 @@ flow_meter_split_prep(struct rte_eth_dev *dev, struct mlx5_rte_flow_item_tag *tag_item_spec; struct mlx5_rte_flow_item_tag *tag_item_mask; uint32_t tag_id = 0; - bool copy_vlan = false; + struct rte_flow_item *vlan_item_dst = NULL; + const struct rte_flow_item *vlan_item_src = NULL; struct rte_flow_action *hw_mtr_action; struct rte_flow_action *action_pre_head = NULL; - bool mtr_first = priv->sh->meter_aso_en && - (attr->egress || - (attr->transfer && priv->representor_id != UINT16_MAX)); + int32_t flow_src_port = priv->representor_id; + bool mtr_first; uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0; uint8_t mtr_reg_bits = priv->mtr_reg_share ? MLX5_MTR_IDLE_BITS_IN_COLOR_REG : MLX5_REG_BITS; @@ -4754,6 +4754,42 @@ flow_meter_split_prep(struct rte_eth_dev *dev, uint8_t flow_id_bits = 0; int shift; + /* Prepare the suffix subflow items. */ + tag_item = sfx_items++; + for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { + struct mlx5_priv *port_priv; + const struct rte_flow_item_port_id *pid_v; + int item_type = items->type; + + switch (item_type) { + case RTE_FLOW_ITEM_TYPE_PORT_ID: + pid_v = items->spec; + MLX5_ASSERT(pid_v); + port_priv = mlx5_port_to_eswitch_info(pid_v->id, false); + if (!port_priv) + return rte_flow_error_set(error, + rte_errno, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + pid_v, + "Failed to get port info."); + flow_src_port = port_priv->representor_id; + memcpy(sfx_items, items, sizeof(*sfx_items)); + sfx_items++; + break; + case RTE_FLOW_ITEM_TYPE_VLAN: + /* Determine if copy vlan item below. */ + vlan_item_src = items; + vlan_item_dst = sfx_items++; + vlan_item_dst->type = RTE_FLOW_ITEM_TYPE_VOID; + break; + default: + break; + } + } + sfx_items->type = RTE_FLOW_ITEM_TYPE_END; + sfx_items++; + mtr_first = priv->sh->meter_aso_en && + (attr->egress || (attr->transfer && flow_src_port != 0xffff)); /* For ASO meter, meter must be before tag in TX direction. */ if (mtr_first) { action_pre_head = actions_pre++; @@ -4790,7 +4826,16 @@ flow_meter_split_prep(struct rte_eth_dev *dev, break; case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: - copy_vlan = true; + if (vlan_item_dst && vlan_item_src) { + memcpy(vlan_item_dst, vlan_item_src, + sizeof(*vlan_item_dst)); + /* + * Convert to internal match item, it is used + * for vlan push and set vid. + */ + vlan_item_dst->type = (enum rte_flow_item_type) + MLX5_RTE_FLOW_ITEM_TYPE_VLAN; + } break; default: break; @@ -4862,34 +4907,6 @@ flow_meter_split_prep(struct rte_eth_dev *dev, if (flow_id_bits > priv->sh->mtrmng->max_mtr_flow_bits) priv->sh->mtrmng->max_mtr_flow_bits = flow_id_bits; } - /* Prepare the suffix subflow items. */ - tag_item = sfx_items++; - for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { - int item_type = items->type; - - switch (item_type) { - case RTE_FLOW_ITEM_TYPE_PORT_ID: - memcpy(sfx_items, items, sizeof(*sfx_items)); - sfx_items++; - break; - case RTE_FLOW_ITEM_TYPE_VLAN: - if (copy_vlan) { - memcpy(sfx_items, items, sizeof(*sfx_items)); - /* - * Convert to internal match item, it is used - * for vlan push and set vid. - */ - sfx_items->type = (enum rte_flow_item_type) - MLX5_RTE_FLOW_ITEM_TYPE_VLAN; - sfx_items++; - } - break; - default: - break; - } - } - sfx_items->type = RTE_FLOW_ITEM_TYPE_END; - sfx_items++; /* Build tag actions and items for meter_id/meter flow_id. */ set_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre; tag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; -- 2.20.0