[dpdk-dev] [PATCH 5/5] examples/pipeline: add selector CLI and spec files

[dpdk-dev] [PATCH 5/5] examples/pipeline: add selector CLI and spec files

[Cristian Dumitrescu]

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
---
 examples/pipeline/examples/selector.cli  | 31 +++++++++++
 examples/pipeline/examples/selector.spec | 70 ++++++++++++++++++++++++
 examples/pipeline/examples/selector.txt  |  4 ++
 3 files changed, 105 insertions(+)
 create mode 100644 examples/pipeline/examples/selector.cli
 create mode 100644 examples/pipeline/examples/selector.spec
 create mode 100644 examples/pipeline/examples/selector.txt

diff --git a/examples/pipeline/examples/selector.cli b/examples/pipeline/examples/selector.cli
new file mode 100644
index 000000000..36f3ead54
--- /dev/null
+++ b/examples/pipeline/examples/selector.cli
@@ -0,0 +1,31 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2020 Intel Corporation
+
+mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
+
+link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK1 dev 0000:18:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK2 dev 0000:3b:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK3 dev 0000:3b:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+
+pipeline PIPELINE0 create 0
+
+pipeline PIPELINE0 port in 0 link LINK0 rxq 0 bsz 32
+pipeline PIPELINE0 port in 1 link LINK1 rxq 0 bsz 32
+pipeline PIPELINE0 port in 2 link LINK2 rxq 0 bsz 32
+pipeline PIPELINE0 port in 3 link LINK3 rxq 0 bsz 32
+
+pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
+pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
+pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
+pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
+pipeline PIPELINE0 port out 4 sink none
+
+pipeline PIPELINE0 build ./examples/pipeline/examples/selector.spec
+
+pipeline PIPELINE0 selector s group add
+pipeline PIPELINE0 selector s group member add ./examples/pipeline/examples/selector.txt
+pipeline PIPELINE0 commit
+pipeline PIPELINE0 selector s show
+
+thread 1 pipeline PIPELINE0 enable
diff --git a/examples/pipeline/examples/selector.spec b/examples/pipeline/examples/selector.spec
new file mode 100644
index 000000000..5d3a7e5a3
--- /dev/null
+++ b/examples/pipeline/examples/selector.spec
@@ -0,0 +1,70 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2020 Intel Corporation
+
+//
+// Headers
+//
+struct ethernet_h {
+	bit<48> dst_addr
+	bit<48> src_addr
+	bit<16> ethertype
+}
+
+struct ipv4_h {
+	bit<8> ver_ihl
+	bit<8> diffserv
+	bit<16> total_len
+	bit<16> identification
+	bit<16> flags_offset
+	bit<8> ttl
+	bit<8> protocol
+	bit<16> hdr_checksum
+	bit<32> src_addr
+	bit<32> dst_addr
+}
+
+header ethernet instanceof ethernet_h
+header ipv4 instanceof ipv4_h
+
+//
+// Meta-data
+//
+struct metadata_t {
+	bit<32> port_in
+	bit<32> port_out
+	bit<32> group_id
+}
+
+metadata instanceof metadata_t
+
+//
+// Selectors.
+//
+selector s {
+	group_id m.group_id
+
+	selector {
+		h.ipv4.protocol
+		h.ipv4.src_addr
+		h.ipv4.dst_addr
+	}
+
+	member_id m.port_out
+
+	n_groups_max 64
+	n_members_per_group_max 16
+}
+
+//
+// Pipeline.
+//
+apply {
+	rx m.port_in
+	extract h.ethernet
+	extract h.ipv4
+	mov m.group_id h.ethernet.dst_addr
+	table s
+	emit h.ethernet
+	emit h.ipv4
+	tx m.port_out
+}
diff --git a/examples/pipeline/examples/selector.txt b/examples/pipeline/examples/selector.txt
new file mode 100644
index 000000000..b3c83c773
--- /dev/null
+++ b/examples/pipeline/examples/selector.txt
@@ -0,0 +1,4 @@
+group 0 member 0 weight 1
+group 0 member 1 weight 1
+group 0 member 2 weight 2
+group 0 member 3 weight 4
-- 
2.17.1