From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F411EA0C4A; Thu, 8 Jul 2021 13:47:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E06C5415E8; Thu, 8 Jul 2021 13:47:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7E91F4069C for ; Thu, 8 Jul 2021 13:47:50 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 168Bj5Eq018145 for ; Thu, 8 Jul 2021 04:47:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Bdzx+TCf1GdzK0DiaQuI1OCZr3uQZMQFKj3uunhRuS0=; b=Xj2+2Uvck62llKigV33fhxXoJsAHbbOXgSTJVsynmSUocQx4Mf2JhyAzS2CSJIp9Jfvr 31TlohnkQQ4QifQwsnoErsgCLgwhwIyYsngPZukMEsK2NWSW6XEkgpeBdZNdF2CezTzC 4TvSpliCbWv+SXikyhhTXy2BMbmA+9cRvzKjJ4nft+9X870hWwV1i26r6H1bnB99IcQ8 +Ul9/0NC4T5847RQpjHM6xDSUie9hx3aFlNRimb26G4k44l/doBX5emx3DI673Nqeh8L EMXHdkjluZOAD4yWDwXFVHgYK/zK321+4HXDhO3YKeDQolvZ1qGQFxPqcwl/Fqd6nY+q GA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 39ny0g8buy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 08 Jul 2021 04:47:49 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 8 Jul 2021 04:47:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 8 Jul 2021 04:47:47 -0700 Received: from hyd1349.t110.caveonetworks.com.com (unknown [10.29.45.13]) by maili.marvell.com (Postfix) with ESMTP id D2AA03F7064; Thu, 8 Jul 2021 04:47:45 -0700 (PDT) From: Ankur Dwivedi To: CC: , , , , Ankur Dwivedi Date: Thu, 8 Jul 2021 17:17:14 +0530 Message-ID: <20210708114714.32623-3-adwivedi@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210708114714.32623-1-adwivedi@marvell.com> References: <20210708114714.32623-1-adwivedi@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: OdEiCM-tmR-a_9yKZHHdqpW3f-O11U6n X-Proofpoint-GUID: OdEiCM-tmR-a_9yKZHHdqpW3f-O11U6n X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-08_06:2021-07-08, 2021-07-08 signatures=0 Subject: [dpdk-dev] [PATCH 2/2] crypto/cnxk: add dev start and dev stop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The instruction queue is enabled in dev start and is disabled in dev stop. Signed-off-by: Ankur Dwivedi --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 7322539a17..7d8d98e7ec 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -95,7 +95,13 @@ cnxk_cpt_dev_config(struct rte_cryptodev *dev, int cnxk_cpt_dev_start(struct rte_cryptodev *dev) { - RTE_SET_USED(dev); + struct cnxk_cpt_vf *vf = dev->data->dev_private; + struct roc_cpt *roc_cpt = &vf->cpt; + uint16_t nb_lf = roc_cpt->nb_lf; + uint16_t qp_id; + + for (qp_id = 0; qp_id < nb_lf; qp_id++) + roc_cpt_iq_enable(roc_cpt->lf[qp_id]); return 0; } @@ -103,7 +109,13 @@ cnxk_cpt_dev_start(struct rte_cryptodev *dev) void cnxk_cpt_dev_stop(struct rte_cryptodev *dev) { - RTE_SET_USED(dev); + struct cnxk_cpt_vf *vf = dev->data->dev_private; + struct roc_cpt *roc_cpt = &vf->cpt; + uint16_t nb_lf = roc_cpt->nb_lf; + uint16_t qp_id; + + for (qp_id = 0; qp_id < nb_lf; qp_id++) + roc_cpt_iq_disable(roc_cpt->lf[qp_id]); } int -- 2.28.0