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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2021 14:29:35.0866 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cfeb1ff-1df0-4eca-bfdf-08d94541791a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0050 Subject: [dpdk-dev] [PATCH] net/mlx5: fix threshold for mbuf replenishment in MPRQ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The replenishment scheme for the vectorized MPRQ Rx burst aims to improve the cache locality by allocating new mbufs only when there are almost no mbufs left: one burst gap between allocated and consumed indexes. This gap is not big enough to accommodate a corner case when we have a very aggressive CQE compression with up to 4 regular CQEs and 64 zipped CQEs at the end. Need to keep in mind this case and extend the replenishment threshold by MLX5_VPMD_DESCS_PER_LOOP (4) to avoid mbuf overflow. Fixes: 5fc2e5c27d6 ("net/mlx5: fix mbuf overflow in vectorized MPRQ") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_rxtx_vec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c index d5af2d91ff..e22ab665df 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.c +++ b/drivers/net/mlx5/mlx5_rxtx_vec.c @@ -152,7 +152,8 @@ mlx5_rx_mprq_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq) unsigned int i; if (n >= rxq->rq_repl_thresh && - rxq->elts_ci - rxq->rq_pi <= rxq->rq_repl_thresh) { + rxq->elts_ci - rxq->rq_pi <= + (uint32_t)rxq->rq_repl_thresh + MLX5_VPMD_DESCS_PER_LOOP) { MLX5_ASSERT(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(elts_n)); MLX5_ASSERT(MLX5_VPMD_RXQ_RPLNSH_THRESH(elts_n) > MLX5_VPMD_DESCS_PER_LOOP); -- 2.18.2