From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7210CA0C4F; Thu, 15 Jul 2021 08:10:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5D1AA41134; Thu, 15 Jul 2021 08:10:11 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1E2F441123 for ; Thu, 15 Jul 2021 08:10:09 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16F65Eus028596; Wed, 14 Jul 2021 23:10:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=NeUilDkyMx/R8RSH9AahgE/cHqBfLMwdlu8VgAPi2j0=; b=WqKXvasCBY8XiuDP/LgC4RiWmHJIjcmswo6XBveMIhfKM8PVPmjqLRYQtmD+ypzz1T9K RtjpjNQXKcq1kPnKD9ScKb3GkPpaECd7zWi6pXLVxBMTRHhe9Lm7GC6IO+43shgSdNtv +LA5uTmkWfUS5gvczXndoxWuAlsmd6Jd9TmNlnzse5g7+6mv1jRrDqJOTQdyBuy/fxyR 53sGKVE7dAghe/95B/i/anLUL3q3kEI6vPeMy2YvrSmv3401ptTN7kaHJ5lhdRbBOLGL Um7PV2KbdK//pVeV2k1x3wCyopCqkKKVpmWG8Lm97bJsPzWPIwknNG9CWWIsEGnpIbRi Ww== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 39swveuuqb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 14 Jul 2021 23:10:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 14 Jul 2021 23:10:07 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 14 Jul 2021 23:10:07 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 69D3D3F708A; Wed, 14 Jul 2021 23:10:00 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , , , , , , , Nithin Dabilpuram Date: Thu, 15 Jul 2021 11:39:45 +0530 Message-ID: <20210715060947.20186-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210715060947.20186-1-ndabilpuram@marvell.com> References: <20210624102848.3878788-1-gakhil@marvell.com> <20210715060947.20186-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: 08vPc4oC0Ftu_hVYV7DJcQabOOih8eKf X-Proofpoint-ORIG-GUID: 08vPc4oC0Ftu_hVYV7DJcQabOOih8eKf X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-15_02:2021-07-14, 2021-07-15 signatures=0 Subject: [dpdk-dev] [PATCH v2 1/3] security: enforce semantics for Tx inline processing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Not all net PMD's/HW can parse packet and identify L2 header and L3 header locations on Tx. This is inline with other Tx offloads requirements such as L3 checksum, L4 checksum offload, etc, where mbuf.l2_len, mbuf.l3_len etc, needs to be set for HW to be able to generate checksum. Since Inline IPSec is also such a Tx offload, some PMD's at least need mbuf.l2_len to be valid to find L3 header and perform Outbound IPSec processing. Hence, this patch updates documentation to enforce setting mbuf.l2_len while setting PKT_TX_SEC_OFFLOAD in mbuf.ol_flags for Inline IPSec Crypto / Protocol offload processing to work on Tx. Signed-off-by: Nithin Dabilpuram --- doc/guides/nics/features.rst | 2 ++ lib/mbuf/rte_mbuf_core.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst index a96e12d..4fce8cd 100644 --- a/doc/guides/nics/features.rst +++ b/doc/guides/nics/features.rst @@ -430,6 +430,7 @@ of protocol operations. See Security library and PMD documentation for more deta * **[uses] rte_eth_rxconf,rte_eth_rxmode**: ``offloads:DEV_RX_OFFLOAD_SECURITY``, * **[uses] rte_eth_txconf,rte_eth_txmode**: ``offloads:DEV_TX_OFFLOAD_SECURITY``. +* **[uses] mbuf**: ``mbuf.l2_len``. * **[implements] rte_security_ops**: ``session_create``, ``session_update``, ``session_stats_get``, ``session_destroy``, ``set_pkt_metadata``, ``capabilities_get``. * **[provides] rte_eth_dev_info**: ``rx_offload_capa,rx_queue_offload_capa:DEV_RX_OFFLOAD_SECURITY``, @@ -451,6 +452,7 @@ protocol operations. See security library and PMD documentation for more details * **[uses] rte_eth_rxconf,rte_eth_rxmode**: ``offloads:DEV_RX_OFFLOAD_SECURITY``, * **[uses] rte_eth_txconf,rte_eth_txmode**: ``offloads:DEV_TX_OFFLOAD_SECURITY``. +* **[uses] mbuf**: ``mbuf.l2_len``. * **[implements] rte_security_ops**: ``session_create``, ``session_update``, ``session_stats_get``, ``session_destroy``, ``set_pkt_metadata``, ``get_userdata``, ``capabilities_get``. diff --git a/lib/mbuf/rte_mbuf_core.h b/lib/mbuf/rte_mbuf_core.h index bb38d7f..9d8e3dd 100644 --- a/lib/mbuf/rte_mbuf_core.h +++ b/lib/mbuf/rte_mbuf_core.h @@ -228,6 +228,8 @@ extern "C" { /** * Request security offload processing on the TX packet. + * To use Tx security offload, the user needs to fill l2_len in mbuf + * indicating L2 header size and where L3 header starts. */ #define PKT_TX_SEC_OFFLOAD (1ULL << 43) -- 2.8.4