From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 014C4A0C48; Tue, 20 Jul 2021 15:11:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B7C774111E; Tue, 20 Jul 2021 15:10:26 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2089.outbound.protection.outlook.com [40.107.94.89]) by mails.dpdk.org (Postfix) with ESMTP id D9A3B41190 for ; Tue, 20 Jul 2021 15:10:24 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=H7gfNNM4/BZU8YgpSr0yUCv1dn69C1EPpsDlBS8HMd01eg8zZ7r3BqCWbgJ5XPcPp9qb0Of97vRq3PaJh8T7PptlXsFMUtt1YY2zAU3HSripg5Hr9paJAboXhNrBJVtTIj3SRxO3BLA3d1JSTFUwaaDr6cgCLDVpjbn1s3Ck+5/GONvCbbxbBJR3TXF2mA7DrHG8iBaGXxjhlvnff+FTQe0fpuzGT/EZFYa3Nhe5cMYvXJWC83M7Fl4LdWyO8XMefDP4XscEnxsE+mkVTi7HKgqelsiOP0/n+2AZXFYber28n+0Baq0MRNibOAsNW3mlulDXq4yR4L8+qxVztnvCkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qRGWefQBxPQQ/m7jlWNH2AlgyaSQZMTNs95i5J9a0Pk=; b=gxqhtjqLuvbLXiIyjKSxnIlg9fcFw7OCafgR2UFn+RBLOvMuQVm+olajxtrYidsRVdLd/Pfbgg0IAVbb6DBFJKuYidclkNZicIbZQ9sWkfQa4Qutgpfbkzd7H6g+JNoCvQ8g3ml9EHXe3EV9qpFWjE5oQOS/7dWkqoz1kU/FAI0P/9rS1wFKkGVOCFPdkDO+ubuLB2KlK6D7/ar26iLAmVvZGoEsDWTHycXRd1a1+c5a/4FIatsdX9DQoPT1KGebEf7q2zrsCNM/JMZZMEkCnQv313i2KoK+cyOWBN7o4ZKiZkEw6JhthmfqQ671XKTbqLSKiMTMcwlkEA34gN0/JQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qRGWefQBxPQQ/m7jlWNH2AlgyaSQZMTNs95i5J9a0Pk=; b=iPpoxuw9PrXTbmMk6a/DKJGyBc/UNA9UsrtPeGzAjw9swXfr+xZcxuFWaL7XrQAWrpLE7pni3l3e1NXd/dKIt4dk6LhJwZJXXUWbHqTXgCQeCVENI6N0ISAlqPnNh2whQpowkngS/EeN8O8TiQA8gmRVAP6qJfWUPWkPENT49+C42AaQWjGSrWfhsXK8oomTY2u2knu3LJc+yYOaJnjoen3t2qyJlNmbmmPruhU1bhJ6O7VYKJWFFA0rg63sVYXylt0Ide6L/bHE9ZZDjwJp2yQAG8/iIV8+IKkFlVYxWm3NbPAarUX4VovdpFvrsW7tzO5TxDExKqFTdLSBf8Nk+Q== Received: from MW4P221CA0022.NAMP221.PROD.OUTLOOK.COM (2603:10b6:303:8b::27) by DM4PR12MB5056.namprd12.prod.outlook.com (2603:10b6:5:38b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.23; Tue, 20 Jul 2021 13:10:23 +0000 Received: from CO1NAM11FT036.eop-nam11.prod.protection.outlook.com (2603:10b6:303:8b:cafe::86) by MW4P221CA0022.outlook.office365.com (2603:10b6:303:8b::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.23 via Frontend Transport; Tue, 20 Jul 2021 13:10:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT036.mail.protection.outlook.com (10.13.174.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4331.21 via Frontend Transport; Tue, 20 Jul 2021 13:10:23 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul 2021 13:10:20 +0000 From: Suanming Mou To: , CC: , , Date: Tue, 20 Jul 2021 16:09:39 +0300 Message-ID: <20210720130944.5407-11-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210720130944.5407-1-suanmingm@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210720130944.5407-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4d7fcf7f-67b0-47ea-df45-08d94b7fbbd9 X-MS-TrafficTypeDiagnostic: DM4PR12MB5056: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:295; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yR0EfWu0rBO+oknoZ2tZxApywECxZk/lJ2jBevSMmwyY7/WvSncWiLQsileHDNIfADchDyxfqbiwrO3VI3iXE9xuoWZVxkUlUTH+B2XZRfq9vDiPFf5t4TeJFtkwzKpLypgfsdzqBTjDYfmitSb1z/4eaCTsadtPqUjLEczQVbZKB5kPSTSo6aXM4l/4hGWZVbq7m4bUzQ818xEH2T41BXQjxve4yIbL/yccsR8qgn1dxYl1BXyPcWqSTLz7tcyelhQdN+4I+j8CHL/FU/k7B5cyfKByalP/LKkIMszcyYQd1uBLqRLHgrDpHRrpjW4If0jQmXBLeThCwa2bH/IVnbjzCkXZJVFDj8khPQDeoYwLNGg/IDs0xCJsrEtTft4rLIWneQxAdE8ozEWcTHG6ya9kbeG0j5zJKF5UE83bGfnvjv0NVu3hLlczwm3HvpzLZBiIJAIbhIXo2lgdIc3gHhd1NAycNzH7TuDvHSID7cgpj/x1vmhGN0ywoQ876MkTl+W/tVeaBxZeUQIPHVR8WyLvYsv5aFg1S1xV1XZGtA+CLsdfiqggK6fW0SOnvYR4U3i2JabFbOQfOv7PLjMKlgUJVZ9v7LeVveL9IHqJpyX00LUQ57XudcuZuknHrVT4hXryS0pPzTt8AgDSgx0VOn6J6yVk8LreKp1+vt1rm9bdJo/o2LxFNeKMcOrHM5qE3pbPx/6G0nB3yHqgBtSycQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(376002)(136003)(396003)(39860400002)(36840700001)(46966006)(70206006)(70586007)(36756003)(336012)(7696005)(6286002)(5660300002)(82310400003)(55016002)(426003)(36860700001)(4326008)(54906003)(186003)(8936002)(86362001)(2616005)(83380400001)(2906002)(47076005)(16526019)(7636003)(36906005)(1076003)(82740400003)(478600001)(316002)(6666004)(8676002)(26005)(356005)(110136005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2021 13:10:23.3094 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d7fcf7f-67b0-47ea-df45-08d94b7fbbd9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5056 Subject: [dpdk-dev] [PATCH v9 10/15] crypto/mlx5: add WQE set initialization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, HW handles the WQEs much faster than the software, Using the constant WQE set layout can initialize most of the WQE segments in advanced, and software only needs to configure very limited segments in datapath. This accelerates the software WQE organize in datapath. This commit initializes the fixed WQE set segments. Signed-off-by: Suanming Mou Signed-off-by: Matan Azrad --- drivers/crypto/mlx5/mlx5_crypto.c | 83 +++++++++++++++++++++++++++++-- drivers/crypto/mlx5/mlx5_crypto.h | 10 +++- 2 files changed, 87 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index f7e23d16e9..caad94d2f5 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -295,6 +295,69 @@ mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp) return 0; } +static void +mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp) +{ + uint32_t i; + + for (i = 0 ; i < qp->entries_n; i++) { + struct mlx5_wqe_cseg *cseg = RTE_PTR_ADD(qp->umem_buf, i * + priv->wqe_set_size); + struct mlx5_wqe_umr_cseg *ucseg = (struct mlx5_wqe_umr_cseg *) + (cseg + 1); + struct mlx5_wqe_umr_bsf_seg *bsf = + (struct mlx5_wqe_umr_bsf_seg *)(RTE_PTR_ADD(cseg, + priv->umr_wqe_size)) - 1; + struct mlx5_wqe_rseg *rseg; + + /* Init UMR WQE. */ + cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | + (priv->umr_wqe_size / MLX5_WSEG_SIZE)); + cseg->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR << + MLX5_COMP_MODE_OFFSET); + cseg->misc = rte_cpu_to_be_32(qp->mkey[i]->id); + ucseg->if_cf_toe_cq_res = RTE_BE32(1u << MLX5_UMRC_IF_OFFSET); + ucseg->mkey_mask = RTE_BE64(1u << 0); /* Mkey length bit. */ + ucseg->ko_to_bs = rte_cpu_to_be_32 + ((RTE_ALIGN(priv->max_segs_num, 4u) << + MLX5_UMRC_KO_OFFSET) | (4 << MLX5_UMRC_TO_BS_OFFSET)); + bsf->keytag = priv->keytag; + /* Init RDMA WRITE WQE. */ + cseg = RTE_PTR_ADD(cseg, priv->umr_wqe_size); + cseg->flags = RTE_BE32((MLX5_COMP_ALWAYS << + MLX5_COMP_MODE_OFFSET) | + MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE); + rseg = (struct mlx5_wqe_rseg *)(cseg + 1); + rseg->rkey = rte_cpu_to_be_32(qp->mkey[i]->id); + } +} + +static int +mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv, + struct mlx5_crypto_qp *qp) +{ + struct mlx5_umr_wqe *umr; + uint32_t i; + struct mlx5_devx_mkey_attr attr = { + .pd = priv->pdn, + .umr_en = 1, + .crypto_en = 1, + .set_remote_rw = 1, + .klm_num = RTE_ALIGN(priv->max_segs_num, 4), + }; + + for (umr = (struct mlx5_umr_wqe *)qp->umem_buf, i = 0; + i < qp->entries_n; i++, umr = RTE_PTR_ADD(umr, priv->wqe_set_size)) { + attr.klm_array = (struct mlx5_klm *)&umr->kseg[0]; + qp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->ctx, &attr); + if (!qp->mkey[i]) { + DRV_LOG(ERR, "Failed to allocate indirect mkey."); + return -1; + } + } + return 0; +} + static int mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, const struct rte_cryptodev_qp_conf *qp_conf, @@ -305,7 +368,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, struct mlx5_crypto_qp *qp; uint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors); uint32_t umem_size = RTE_BIT32(log_nb_desc) * - MLX5_CRYPTO_WQE_SET_SIZE + + priv->wqe_set_size + sizeof(*qp->db_rec) * 2; uint32_t alloc_size = sizeof(*qp); struct mlx5_devx_cq_attr cq_attr = { @@ -315,7 +378,9 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, if (dev->data->queue_pairs[qp_id] != NULL) mlx5_crypto_queue_pair_release(dev, qp_id); alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); - alloc_size += sizeof(struct rte_crypto_op *) * RTE_BIT32(log_nb_desc); + alloc_size += (sizeof(struct rte_crypto_op *) + + sizeof(struct mlx5_devx_obj *)) * + RTE_BIT32(log_nb_desc); qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, socket_id); if (qp == NULL) { @@ -360,8 +425,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, attr.wq_umem_id = qp->umem_obj->umem_id; attr.wq_umem_offset = 0; attr.dbr_umem_id = qp->umem_obj->umem_id; - attr.dbr_address = RTE_BIT64(log_nb_desc) * - MLX5_CRYPTO_WQE_SET_SIZE; + attr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size; qp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr); if (qp->qp_obj == NULL) { DRV_LOG(ERR, "Failed to create QP(%u).", rte_errno); @@ -370,8 +434,17 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, qp->db_rec = RTE_PTR_ADD(qp->umem_buf, (uintptr_t)attr.dbr_address); if (mlx5_crypto_qp2rts(qp)) goto error; - qp->ops = (struct rte_crypto_op **)RTE_ALIGN((uintptr_t)(qp + 1), + qp->mkey = (struct mlx5_devx_obj **)RTE_ALIGN((uintptr_t)(qp + 1), RTE_CACHE_LINE_SIZE); + qp->ops = (struct rte_crypto_op **)(qp->mkey + RTE_BIT32(log_nb_desc)); + qp->entries_n = 1 << log_nb_desc; + if (mlx5_crypto_indirect_mkeys_prepare(priv, qp)) { + DRV_LOG(ERR, "Cannot allocate indirect memory regions."); + rte_errno = ENOMEM; + goto error; + } + mlx5_crypto_qp_init(priv, qp); + qp->priv = priv; dev->data->queue_pairs[qp_id] = qp; return 0; error: diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index c0fa8ad4d4..235a43a72a 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -16,7 +16,6 @@ #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11) #define MLX5_CRYPTO_KEY_LENGTH 80 -#define MLX5_CRYPTO_WQE_SET_SIZE 1024 struct mlx5_crypto_priv { TAILQ_ENTRY(mlx5_crypto_priv) next; @@ -24,6 +23,7 @@ struct mlx5_crypto_priv { struct rte_pci_device *pci_dev; struct rte_cryptodev *crypto_dev; void *uar; /* User Access Region. */ + volatile uint64_t *uar_addr; uint32_t pdn; /* Protection Domain number. */ uint32_t max_segs_num; /* Maximum supported data segs. */ struct ibv_pd *pd; @@ -39,13 +39,21 @@ struct mlx5_crypto_priv { }; struct mlx5_crypto_qp { + struct mlx5_crypto_priv *priv; struct mlx5_devx_cq cq_obj; struct mlx5_devx_obj *qp_obj; + struct rte_cryptodev_stats stats; struct mlx5dv_devx_umem *umem_obj; void *umem_buf; volatile uint32_t *db_rec; struct rte_crypto_op **ops; + struct mlx5_devx_obj **mkey; /* WQE's indirect mekys. */ struct mlx5_mr_ctrl mr_ctrl; + uint8_t *wqe; + uint16_t entries_n; + uint16_t pi; + uint16_t ci; + uint16_t db_pi; }; struct mlx5_crypto_dek { -- 2.25.1