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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT009.mail.protection.outlook.com (10.13.176.65) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4352.24 via Frontend Transport; Thu, 22 Jul 2021 07:50:21 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Jul 2021 07:50:16 +0000 From: Dong Zhou To: CC: , Date: Thu, 22 Jul 2021 10:48:39 +0300 Message-ID: <20210722074839.27513-1-dongzhou@nvidia.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4f33c0b7-c5cf-4eec-8028-08d94ce55bae X-MS-TrafficTypeDiagnostic: BYAPR12MB4613: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; 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CAT:NONE; SFS:(4636009)(396003)(136003)(39860400002)(376002)(346002)(46966006)(36840700001)(7636003)(36756003)(356005)(5660300002)(26005)(36906005)(86362001)(6666004)(6636002)(55016002)(186003)(82740400003)(4326008)(8676002)(2906002)(107886003)(478600001)(6862004)(6286002)(7696005)(1076003)(82310400003)(83380400001)(336012)(70206006)(426003)(70586007)(37006003)(36860700001)(16526019)(316002)(54906003)(2616005)(8936002)(47076005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jul 2021 07:50:21.7461 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f33c0b7-c5cf-4eec-8028-08d94ce55bae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB4613 Subject: [dpdk-dev] [PATCH] net/mlx5: add check for pop and push VLAN actions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For CX6 in FDB domain, pop and push VLAN on both ingress and egress directions are supported. For CX6 in NIC domain, and CX5 in both FWD add NIC domain, pop VLAN is only supported on ingress direction, push VLAN is only supported on egress direction. Signed-off-by: Dong Zhou Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 7 ++++- drivers/net/mlx5/linux/mlx5_os.c | 2 ++ drivers/net/mlx5/mlx5.h | 2 ++ drivers/net/mlx5/mlx5_flow_dv.c | 38 ++++++++++++++++++++++++---- 6 files changed, 46 insertions(+), 6 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 10a02d13ee..56407cc332 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -819,6 +819,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); + attr->steering_format_version = + MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, regexp_num_of_engines); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index c11ca6586f..e576e30f24 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -141,6 +141,7 @@ struct mlx5_hca_attr { uint32_t roce:1; uint32_t rq_ts_format:2; uint32_t sq_ts_format:2; + uint32_t steering_format_version:4; uint32_t qp_ts_format:2; uint32_t regex:1; uint32_t reg_c_preserve:1; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 7950070976..915fcb66a2 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1317,6 +1317,10 @@ enum { #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) +/* The device steering logic format. */ +#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0 +#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1 + struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_0[0x30]; u8 vhca_id[0x10]; @@ -1585,7 +1589,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 general_obj_types[0x40]; u8 sq_ts_format[0x2]; u8 rq_ts_format[0x2]; - u8 reserved_at_444[0x1C]; + u8 steering_format_version[0x4]; + u8 reserved_at_448[0x18]; u8 reserved_at_460[0x8]; u8 aes_xts[0x1]; u8 crypto[0x1]; diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index aa5210fa45..1dbb51da0c 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1357,6 +1357,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } sh->rq_ts_format = config->hca_attr.rq_ts_format; sh->sq_ts_format = config->hca_attr.sq_ts_format; + sh->steering_format_version = + config->hca_attr.steering_format_version; sh->qp_ts_format = config->hca_attr.qp_ts_format; /* Check for LRO support. */ if (config->dest_tir && config->hca_attr.lro_cap && diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 94618e10fa..61898e8ea1 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1113,6 +1113,8 @@ struct mlx5_dev_ctx_shared { uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */ uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */ + uint32_t steering_format_version:4; + /* Indicates the device steering logic format. */ uint32_t qp_ts_format:2; /* QP timestamp formats supported. */ uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index d250486950..3f9726d1c3 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -2790,20 +2790,30 @@ flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + bool direction_error = false; - (void)action; - (void)attr; if (!priv->sh->pop_vlan_action) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "pop vlan action is not supported"); - if (attr->egress) + /* Pop VLAN is not supported in egress except for CX6 FDB mode. */ + if (attr->transfer) { + bool fdb_tx = priv->representor_id != UINT16_MAX; + bool is_cx5 = sh->steering_format_version == + MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5; + + if (fdb_tx && is_cx5) + direction_error = true; + } else if (attr->egress) { + direction_error = true; + } + if (direction_error) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, - "pop vlan action not supported for " - "egress"); + "pop vlan action not supported for egress"); if (action_flags & MLX5_FLOW_VLAN_ACTIONS) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action, @@ -2927,6 +2937,8 @@ flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev, { const struct rte_flow_action_of_push_vlan *push_vlan = action->conf; const struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + bool direction_error = false; if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) && push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ)) @@ -2938,6 +2950,22 @@ flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ACTION, action, "wrong action order, port_id should " "be after push VLAN"); + /* Push VLAN is not supported in ingress except for CX6 FDB mode. */ + if (attr->transfer) { + bool fdb_tx = priv->representor_id != UINT16_MAX; + bool is_cx5 = sh->steering_format_version == + MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5; + + if (!fdb_tx && is_cx5) + direction_error = true; + } else if (attr->ingress) { + direction_error = true; + } + if (direction_error) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, + NULL, + "push vlan action not supported for ingress"); if (!attr->transfer && priv->representor) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, -- 2.21.0