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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT059.mail.protection.outlook.com (10.13.174.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4352.24 via Frontend Transport; Sat, 24 Jul 2021 13:27:28 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 24 Jul 2021 13:27:26 +0000 From: Bing Zhao To: , CC: , , , Date: Sat, 24 Jul 2021 16:27:11 +0300 Message-ID: <20210724132711.90109-1-bingz@nvidia.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 20478e43-3d41-4645-c27c-08d94ea6c8de X-MS-TrafficTypeDiagnostic: BYAPR12MB2727: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; 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CAT:NONE; SFS:(4636009)(376002)(136003)(39860400002)(346002)(396003)(46966006)(36840700001)(83380400001)(4326008)(36860700001)(356005)(186003)(70206006)(82310400003)(7636003)(8676002)(26005)(70586007)(7696005)(2906002)(86362001)(316002)(1076003)(6666004)(36906005)(16526019)(47076005)(36756003)(82740400003)(426003)(8936002)(478600001)(5660300002)(6636002)(54906003)(336012)(450100002)(6286002)(110136005)(2616005)(55016002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2021 13:27:28.9376 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20478e43-3d41-4645-c27c-08d94ea6c8de X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2727 Subject: [dpdk-dev] [PATCH] net/mlx5: fix queue leaking in hairpin auto bind checking X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" During the start up stage, the hairpin auto bind was executed for each port. All the Tx and Rx queues configured for this port should be checked to confirm if the auto bind of hairpin is needed. 1. The queue is hairpin queue. 2. The peer port is the same one and the peer queue should also be with hairpin type. 3. The manual bind attribute is not set for this queue. If the queue is not a hairpin queue or it doesn't need to be bound automatically, the reference count should be decreased by 1 since the count was increased when calling the mlx5_*xq_get(). When the peer port is not the same, it means that no auto bind is supported and the mlx5_*xq_release() was missed in the current implementation. By calling the release function before continue, the count is correct when calling the device close. Fixes: aa8bea0e3455 ("net/mlx5: add conditional hairpin auto bind") Cc: stable@dpdk.org Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_trigger.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index a9d5d58fd9..54173bfacb 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -228,12 +228,11 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev) txq_ctrl = mlx5_txq_get(dev, i); if (!txq_ctrl) continue; - if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) { + if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN || + txq_ctrl->hairpin_conf.peers[0].port != self_port) { mlx5_txq_release(dev, i); continue; } - if (txq_ctrl->hairpin_conf.peers[0].port != self_port) - continue; if (txq_ctrl->hairpin_conf.manual_bind) { mlx5_txq_release(dev, i); return 0; @@ -247,13 +246,12 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev) txq_ctrl = mlx5_txq_get(dev, i); if (!txq_ctrl) continue; - if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) { + /* Skip hairpin queues with other peer ports. */ + if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN || + txq_ctrl->hairpin_conf.peers[0].port != self_port) { mlx5_txq_release(dev, i); continue; } - /* Skip hairpin queues with other peer ports. */ - if (txq_ctrl->hairpin_conf.peers[0].port != self_port) - continue; if (!txq_ctrl->obj) { rte_errno = ENOMEM; DRV_LOG(ERR, "port %u no txq object found: %d", -- 2.27.0