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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT021.mail.protection.outlook.com (10.13.175.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4373.18 via Frontend Transport; Thu, 29 Jul 2021 12:27:00 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Jul 2021 12:26:58 +0000 From: Viacheslav Ovsiienko To: CC: , , Date: Thu, 29 Jul 2021 15:26:43 +0300 Message-ID: <20210729122643.24865-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6a43c4e7-d99f-40f8-eb84-08d9528c2a2d X-MS-TrafficTypeDiagnostic: MWHPR12MB1181: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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CAT:NONE; SFS:(4636009)(396003)(346002)(376002)(39830400003)(36840700001)(46966006)(450100002)(26005)(70586007)(70206006)(54906003)(356005)(55016002)(16526019)(336012)(5660300002)(1076003)(4326008)(36756003)(186003)(8676002)(6286002)(36906005)(83380400001)(8936002)(2616005)(426003)(7696005)(86362001)(2906002)(6916009)(36860700001)(82310400003)(508600001)(47076005)(7636003)(6666004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2021 12:27:00.5078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a43c4e7-d99f-40f8-eb84-08d9528c2a2d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1181 Subject: [dpdk-dev] [PATCH] net/mlx5: fix Tx queues creation type check for scheduling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The send scheduling on timestamp offload requires the Send Queue (SQ) shares its User Access Region (UAR) with the pacing Clock Queue. The SQ can be created by mlx5 PMD either with DevX or with Verbs. If the SQ is being created with DevX the dedicated UAR can be specified and all the SQs share the single UAR. Once SQ is being created with Verbs the SQ's UAR is allocated by the rdma-core library internally on its own and there are no UAR sharing. This caused hardware errors on WAIT WQEs and overall send scheduling malfunction. If SQs are going to be created with Verbs and the send scheduling offload is explicitly requested via tx_pp devarg the device probing is rejected as device configuration can't satisfy the requirements. Fixes: 3ec73abeed52 ("net/mlx5/linux: fix Tx queue operations decision") Fixes: 8f848f32fc24 ("net/mlx5: introduce send scheduling devargs") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index aa5210fa45..e3c949ffc8 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1769,6 +1769,24 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } else { priv->obj_ops = ibv_obj_ops; } + if (config->tx_pp && + (priv->config.dv_esw_en || + priv->obj_ops.txq_obj_new != mlx5_os_txq_obj_new)) { + /* + * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support + * packet pacing and already checked above. Hence, we should + * only make sure the SQs will be created with DevX, not with + * Verbs. Verbs allocates the SQ UAR on its own and it can't + * be shared with Clock Queue UAR as it required for the + * Tx scheduling feature. + */ + DRV_LOG(ERR, "Verbs SQs, UAR can't be shared" + " as required for packet pacing"); + err = ENODEV; + goto error; + err = ENODEV; + goto error; + } priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); if (!priv->drop_queue.hrxq) goto error; -- 2.18.1