From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A99BEA0C41; Mon, 2 Aug 2021 12:26:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2960741123; Mon, 2 Aug 2021 12:26:47 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2062.outbound.protection.outlook.com [40.107.223.62]) by mails.dpdk.org (Postfix) with ESMTP id A2B3640140; Mon, 2 Aug 2021 12:26:45 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aVqqn7/WSsi7FjEOl4dXlfFWPzjy0xidpsPzSvDeNqf/IqHxH9B6rOMFezxJK3UICA1SYovhv43r2ZaFKqNisdEllm/XNOboDn5mFOZv6efDpf3NFRImkIYm69gla1t02uo5E2hHkMM5WYKzhx+1aCXScmdY2Z/o64Axfxf1eJWjUfR8KPJQwDusMmrHTF2jbJwJHhcyeBLW3CT+NjruHYPLyenGrAJFtfAXGC1T9TegmM45fD62OHy6jzxXGLy+F9UrKnC+p91PpB8jZX5Y0WKqnxkMzytNJ/GbLyzW1GGb2DBEXHZgVOBKzusrzJ0wlvGQPAciGBcIC4nJgvThGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pgebqQ0FN9wrzRFxzxSqfnE+UXs+50VQzHo4QHfJJno=; b=bdQSIfl3yd7fcLcPVg4lDIVr1FbCyEoaboHTTxvtSalfDAJz7fPSAINvxtrXVMjRhYldhZMfd7mj/9xn7095leMfYNSrv3Q4x+33xfmTGAgIDtLxzJK5vwa25/WWJYSTJD/QprCsWYdj7P54FyJXgUt/5FKFOLBl1u8X1tFA/k0+Cmn6xAwgRKb29Xm2ABQEgjdOEOxromM10VRt+2p1zBBLrEbcS+Feayvb83068j8tfYsnPyuIF/cjBsKRZm68HA81MkKu/X5EtYTnMu0ii5Gz6/Vr4VfSrBcFNwH8psE43bdk2/9oDaDzTkBno39CU7vNtAgNtZM+VWv4eAWnPg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pgebqQ0FN9wrzRFxzxSqfnE+UXs+50VQzHo4QHfJJno=; b=AvbvmZm4OeGEfZTySgbt3590fTEvPYPA+Y1wSmz8tpon9IYA+AcIJ+RowmJo+wgfYF7Ycw9Brb66Z/cFOgAf2SQn53ezwuL1NHbpsGMLj8Q7n4iTKJ/Jogi0gBfGy8cbyQneNxfLq5Bu2P2dQMgWT/YPhCPxZxnY30N+d/K1YIHQj/M4STpU/UW5OlUj5htPCM9w/uUQ2x/0EdoabcOFd8Owgd3VR+yKlUFMZzsqRdQGK1XE9YPKAYKvZ1n3bATpverOpdUuDf3zKHFij18+Btp0dOAGbLvEpMkFBftY0Ytqjismxm74+yuyGhq2xvZi8oWY/rXvynmwzoi4TUkFOw== Received: from MWHPR11CA0023.namprd11.prod.outlook.com (2603:10b6:301:1::33) by BN8PR12MB2932.namprd12.prod.outlook.com (2603:10b6:408:96::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.18; Mon, 2 Aug 2021 10:26:44 +0000 Received: from CO1NAM11FT050.eop-nam11.prod.protection.outlook.com (2603:10b6:301:1:cafe::84) by MWHPR11CA0023.outlook.office365.com (2603:10b6:301:1::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.17 via Frontend Transport; Mon, 2 Aug 2021 10:26:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT050.mail.protection.outlook.com (10.13.174.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4373.18 via Frontend Transport; Mon, 2 Aug 2021 10:26:43 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 2 Aug 2021 10:26:41 +0000 From: Rongwei Liu To: , , , , Shahaf Shuler , Raslan Darawsheh CC: , Date: Mon, 2 Aug 2021 13:26:27 +0300 Message-ID: <20210802102627.548015-1-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 545e6684-a273-4aa4-35a6-08d955a00641 X-MS-TrafficTypeDiagnostic: BN8PR12MB2932: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FpIB6Waot24TDhaT535+Z1l2aTI2bznMATU+uYej1gkXSbgTY74u1xbv5n/ym9LyBychmIQKh2e5EY7Mk29iosJ09m3CKyWEvNrZopUEQLOWTphoPnOoiJGT9OiBCds03tMvkbuh8kSQnI9jmtTPdFTYdMkRJe+/jrUxZGtZNU8MyIDeB8IhWzg6AazVMBhioQm7Zp8O313JhBiXMAPjLHQneHhOI0fv8vAdE60FZT0ISM6iJJaP8TNfIyyXKy6gR8yQw7fcYplBMi/tSiA9GK9ZzYvQKnimgXupJXzrv0LwGTu27p2UKI/gAsOgJwA6gv6jH5H2qMDzpKX/iu1Pdiqtrk6NkwvU0j3G/z6r3hHvUZ6Shd1bO4WdkkbRyfe2MUbWVue0AqIYUnSGNQynYbwYp8HQGLpPcVq/nV2UvZf6MS0SAP03KHsFOf5iRhQbaUSM/Y0XW6i4x1A9/BXXJnErA634bTJzsPdgQOnlCSdiDcNn7DNlfDWR9Yw3hGX0Oy8635T4naAYNRDdoMT491f+93KzaXVnP02Ajkby1WlR7iWm+xhxe2hzYIu992V/ujFXWMwTTYRoxyqVPcOpMbvKldtfaYDnHmXDlya168sikOO+EfODvYbheP3aa+ZYmOZxwSYpjfla7o+ARzkMt2TnxMylwZAsB+KQDIUcEw9GsckFeIfi4xBo43v2G87Tm2fJAXTmJfgJ77mFFZPAag== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(396003)(136003)(376002)(39860400002)(46966006)(36840700001)(55016002)(70206006)(83380400001)(82310400003)(70586007)(86362001)(36756003)(186003)(7696005)(5660300002)(26005)(82740400003)(2906002)(336012)(6666004)(2616005)(8936002)(110136005)(1076003)(426003)(4326008)(6636002)(356005)(7636003)(6286002)(36906005)(54906003)(316002)(16526019)(36860700001)(8676002)(47076005)(478600001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Aug 2021 10:26:43.6531 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 545e6684-a273-4aa4-35a6-08d955a00641 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2932 Subject: [dpdk-dev] [PATCH] net/mlx5: fix vni matching with non-std port X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In the recent update, the misc5 matcher was introduced to match VxLAN header extra fields. However, ConnectX-5 doesn't support misc5 for the UDP ports different from VXLAN's standard one (4789). Need to fall back to the previous approach and use legacy misc matcher if non-standard UDP port is recognized in VxLAN flow. Fixes: 630a587bfb37 ("net/mlx5: support matching on VXLAN reserved field") Cc: stable@dpdk.org Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.c | 21 +++++++++++++++------ drivers/net/mlx5/mlx5_flow.h | 1 + drivers/net/mlx5/mlx5_flow_dv.c | 21 +++++++++++++++++---- drivers/net/mlx5/mlx5_flow_verbs.c | 16 +++++++++++++--- 4 files changed, 46 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 0689e6d45d..e63a297e2a 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -2432,6 +2432,8 @@ mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, * * @param[in] dev * Pointer to the Ethernet device structure. + * @param[in] udp_dport + * UDP destination port * @param[in] item * Item specification. * @param[in] item_flags @@ -2446,6 +2448,7 @@ mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, */ int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, + uint16_t udp_dport, const struct rte_flow_item *item, uint64_t item_flags, const struct rte_flow_attr *attr, @@ -2481,12 +2484,18 @@ mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, "no outer UDP layer found"); if (!mask) mask = &rte_flow_item_vxlan_mask; - /* FDB domain & NIC domain non-zero group */ - if ((attr->transfer || attr->group) && priv->sh->misc5_cap) - valid_mask = &nic_mask; - /* Group zero in NIC domain */ - if (!attr->group && !attr->transfer && priv->sh->tunnel_header_0_1) - valid_mask = &nic_mask; + + if (priv->sh->steering_format_version != + MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || + !udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN) { + /* FDB domain & NIC domain non-zero group */ + if ((attr->transfer || attr->group) && priv->sh->misc5_cap) + valid_mask = &nic_mask; + /* Group zero in NIC domain */ + if (!attr->group && !attr->transfer && + priv->sh->tunnel_header_0_1) + valid_mask = &nic_mask; + } ret = mlx5_flow_item_acceptable (item, (const uint8_t *)mask, (const uint8_t *)valid_mask, diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 3724293d26..22fa007b42 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1522,6 +1522,7 @@ int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, struct rte_eth_dev *dev, struct rte_flow_error *error); int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, + uint16_t udp_dport, const struct rte_flow_item *item, uint64_t item_flags, const struct rte_flow_attr *attr, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 059bd25efc..ae0975e8b3 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -6926,6 +6926,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, const struct rte_flow_item *rule_items = items; const struct rte_flow_item *port_id_item = NULL; bool def_policy = false; + uint16_t udp_dport = 0; if (items == NULL) return -1; @@ -7100,6 +7101,14 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, ret = mlx5_flow_validate_item_udp(items, item_flags, next_protocol, error); + const struct rte_flow_item_udp *spec = items->spec; + const struct rte_flow_item_udp *mask = items->mask; + if (!mask) + mask = &rte_flow_item_udp_mask; + if (spec != NULL) + udp_dport = rte_be_to_cpu_16 + (spec->hdr.dst_port & + mask->hdr.dst_port); if (ret < 0) return ret; last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP : @@ -7129,9 +7138,9 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, last_item = MLX5_FLOW_LAYER_GRE_KEY; break; case RTE_FLOW_ITEM_TYPE_VXLAN: - ret = mlx5_flow_validate_item_vxlan(dev, items, - item_flags, attr, - error); + ret = mlx5_flow_validate_item_vxlan(dev, udp_dport, + items, item_flags, + attr, error); if (ret < 0) return ret; last_item = MLX5_FLOW_LAYER_VXLAN; @@ -8927,6 +8936,7 @@ flow_dv_translate_item_vxlan(struct rte_eth_dev *dev, MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF); MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport); } + dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport); if (!vxlan_v) return; if (!vxlan_m) { @@ -8936,7 +8946,10 @@ flow_dv_translate_item_vxlan(struct rte_eth_dev *dev, else vxlan_m = &nic_mask; } - if ((!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) || + if ((priv->sh->steering_format_version == + MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 && + dport != MLX5_UDP_PORT_VXLAN) || + (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) || ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) { void *misc_m; void *misc_v; diff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c index a36b8adf6b..b93fd4d2c9 100644 --- a/drivers/net/mlx5/mlx5_flow_verbs.c +++ b/drivers/net/mlx5/mlx5_flow_verbs.c @@ -1257,6 +1257,7 @@ flow_verbs_validate(struct rte_eth_dev *dev, uint8_t next_protocol = 0xff; uint16_t ether_type = 0; bool is_empty_vlan = false; + uint16_t udp_dport = 0; if (items == NULL) return -1; @@ -1364,6 +1365,15 @@ flow_verbs_validate(struct rte_eth_dev *dev, ret = mlx5_flow_validate_item_udp(items, item_flags, next_protocol, error); + const struct rte_flow_item_udp *spec = items->spec; + const struct rte_flow_item_udp *mask = items->mask; + if (!mask) + mask = &rte_flow_item_udp_mask; + if (spec != NULL) + udp_dport = rte_be_to_cpu_16 + (spec->hdr.dst_port & + mask->hdr.dst_port); + if (ret < 0) return ret; last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP : @@ -1381,9 +1391,9 @@ flow_verbs_validate(struct rte_eth_dev *dev, MLX5_FLOW_LAYER_OUTER_L4_TCP; break; case RTE_FLOW_ITEM_TYPE_VXLAN: - ret = mlx5_flow_validate_item_vxlan(dev, items, - item_flags, attr, - error); + ret = mlx5_flow_validate_item_vxlan(dev, udp_dport, + items, item_flags, + attr, error); if (ret < 0) return ret; last_item = MLX5_FLOW_LAYER_VXLAN; -- 2.27.0