From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1C37CA0C4D; Thu, 12 Aug 2021 04:00:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E5D6741205; Thu, 12 Aug 2021 04:00:41 +0200 (CEST) Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by mails.dpdk.org (Postfix) with ESMTP id CBC76411FC for ; Thu, 12 Aug 2021 04:00:39 +0200 (CEST) X-QQ-mid: bizesmtp31t1628733630tkn2cpgl Received: from jiawenwu.trustnetic.com (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Thu, 12 Aug 2021 10:00:29 +0800 (CST) X-QQ-SSF: 01400000002000E0F000B00A0000000 X-QQ-FEAT: tSE3IANCkAth1H90zJHD3nKfno1qtcS+ji76fUIM56OlTa6yRxzMr9BFaijHv 3AenfGIvvUYLDmxoDduiDOiKRpyZ5JzFU3Q34uiDHNSVLcEdaOFDU1hFefN3ltucaLN/v5j hVPuUvG+aYx1E1xR//sShvgh4jqGFujkTOLQTygRPU7sIvA13PaQgbtn8AC+Y+VAiIdbvCr rBl0ZimGcpsALmSUR1tU0NyXAFphk4Ov2g8Ve3U0LQ5gNIlQNiKRh9/CcQqvPre8eMbIN/N 007+hkSB8tZ3XSGT16holwescF1Oadupn2vPZlyexTVwo2mLVS++G1sov06vqrfds3ZJ89o tvoCX6+Y3joR7KWO0A= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Date: Thu, 12 Aug 2021 10:00:19 +0800 Message-Id: <20210812020020.12656-3-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20210812020020.12656-1-jiawenwu@trustnetic.com> References: <20210812020020.12656-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign5 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH 2/3] net/txgbe: fix to read SFP module's SFF-8472 data X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix the I2C target address selection to read SFP module's SFF-8472 data. Fixes: 8f09fb4642fa ("net/txgbe: add module identify") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_phy.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index 3e9f507212..2db87ae0c5 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -8,7 +8,7 @@ #include "txgbe_mng.h" #include "txgbe_phy.h" -static void txgbe_i2c_start(struct txgbe_hw *hw); +static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr); static void txgbe_i2c_stop(struct txgbe_hw *hw); static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw); static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability, @@ -1248,11 +1248,9 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset, s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data) { - UNREFERENCED_PARAMETER(dev_addr); - DEBUGFUNC("txgbe_read_i2c_byte"); - txgbe_i2c_start(hw); + txgbe_i2c_start(hw, dev_addr); /* wait tx empty */ if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY, @@ -1314,11 +1312,9 @@ s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data) { - UNREFERENCED_PARAMETER(dev_addr); - DEBUGFUNC("txgbe_write_i2c_byte"); - txgbe_i2c_start(hw); + txgbe_i2c_start(hw, dev_addr); /* wait tx empty */ if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY, @@ -1369,7 +1365,7 @@ s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, * * Sets I2C start condition (High -> Low on SDA while SCL is High) **/ -static void txgbe_i2c_start(struct txgbe_hw *hw) +static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr) { DEBUGFUNC("txgbe_i2c_start"); @@ -1380,9 +1376,9 @@ static void txgbe_i2c_start(struct txgbe_hw *hw) TXGBE_I2CCON_SPEED(1) | TXGBE_I2CCON_RESTART | TXGBE_I2CCON_SDIA)); - wr32(hw, TXGBE_I2CTAR, TXGBE_I2C_SLAVEADDR); - wr32(hw, TXGBE_I2CSSSCLHCNT, 600); - wr32(hw, TXGBE_I2CSSSCLLCNT, 600); + wr32(hw, TXGBE_I2CTAR, dev_addr >> 1); + wr32(hw, TXGBE_I2CSSSCLHCNT, 200); + wr32(hw, TXGBE_I2CSSSCLLCNT, 200); wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */ wr32(hw, TXGBE_I2CTXTL, 4); wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF); -- 2.21.0.windows.1