From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BFE3A0C4C; Thu, 2 Sep 2021 04:18:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DFBCA41176; Thu, 2 Sep 2021 04:17:27 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 217E741144 for ; Thu, 2 Sep 2021 04:17:27 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 181HQCpm011801 for ; Wed, 1 Sep 2021 19:17:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=bGE2mtAAGFuYtVYQ+swggPOmR0vd/9apncuXPZ7/bKc=; b=HMejgsT0WnLr+++WRmfAOkD948snczHnUwM2nTcobVu1BPF7whmpJzg3R+XJFG572sGu aX+XcqmKt0naa4pzRcTRuv2PwW2IPRHMUDCPFLrtPP8YR6748Tc2QK/8VbKfPWQ5Q2uz R5/P3S8VLKBlGL+qNxn6X3d445v5TBwDjH2JLJjzAxwYIHMmxUSh2jrUuK3Bvvey9Kp+ uLPqUKTSgAeJBCJRu8Su9Z2iqFLbnnM4bLQoCWUYSi+JBIfKFsWQ5BVesn83q4UJHHzZ 5SvI/kwkhFKem1bu6MbAl0U65WmxG7Qss1JQY7QKbtGS88+7ZZeGSs0UUtdRqcgL24lQ rA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3atdwq9ht5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 01 Sep 2021 19:17:26 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 1 Sep 2021 19:17:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 1 Sep 2021 19:17:24 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id F331B3F704D; Wed, 1 Sep 2021 19:17:21 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , , Satheesh Paul Date: Thu, 2 Sep 2021 07:44:52 +0530 Message-ID: <20210902021505.17607-15-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210902021505.17607-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: 5R18UrpMCxQNS-P7t8KLXab1CnFniXEs X-Proofpoint-GUID: 5R18UrpMCxQNS-P7t8KLXab1CnFniXEs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 14/27] common/cnxk: add inline IPsec support in rte flow X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satheesh Paul Add support to configure flow rules with inline IPsec action. Signed-off-by: Satheesh Paul --- drivers/common/cnxk/roc_nix_inl.h | 4 ++++ drivers/common/cnxk/roc_nix_inl_dev.c | 3 +++ drivers/common/cnxk/roc_nix_inl_priv.h | 3 +++ drivers/common/cnxk/roc_npc_mcam.c | 28 ++++++++++++++++++++++++++-- 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index efc5a19..1f7ec4f 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -107,6 +107,10 @@ struct roc_nix_inl_dev { struct plt_pci_device *pci_dev; uint16_t ipsec_in_max_spi; bool selftest; + bool is_multi_channel; + uint16_t channel; + uint16_t chan_mask; + /* End of input parameters */ #define ROC_NIX_INL_MEM_SZ (1024) diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 214f183..2dc2188 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -461,6 +461,9 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev) inl_dev->pci_dev = pci_dev; inl_dev->ipsec_in_max_spi = roc_inl_dev->ipsec_in_max_spi; inl_dev->selftest = roc_inl_dev->selftest; + inl_dev->is_multi_channel = roc_inl_dev->is_multi_channel; + inl_dev->channel = roc_inl_dev->channel; + inl_dev->chan_mask = roc_inl_dev->chan_mask; /* Initialize base device */ rc = dev_init(&inl_dev->dev, pci_dev); diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index ab38062..a302118 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -45,6 +45,9 @@ struct nix_inl_dev { /* Device arguments */ uint8_t selftest; + uint16_t channel; + uint16_t chan_mask; + bool is_multi_channel; uint16_t ipsec_in_max_spi; }; diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c index 8ccaaad..4985d22 100644 --- a/drivers/common/cnxk/roc_npc_mcam.c +++ b/drivers/common/cnxk/roc_npc_mcam.c @@ -503,8 +503,11 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, { int use_ctr = (flow->ctr_id == NPC_COUNTER_NONE ? 0 : 1); struct npc_mcam_write_entry_req *req; + struct nix_inl_dev *inl_dev = NULL; struct mbox *mbox = npc->mbox; struct mbox_msghdr *rsp; + struct idev_cfg *idev; + uint16_t pf_func = 0; uint16_t ctr = ~(0); int rc, idx; int entry; @@ -553,9 +556,30 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, req->entry_data.kw_mask[idx] = flow->mcam_mask[idx]; } + idev = idev_get_cfg(); + if (idev) + inl_dev = idev->nix_inl_dev; + if (flow->nix_intf == NIX_INTF_RX) { - req->entry_data.kw[0] |= (uint64_t)npc->channel; - req->entry_data.kw_mask[0] |= (BIT_ULL(12) - 1); + if (inl_dev && inl_dev->is_multi_channel && + (flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) { + req->entry_data.kw[0] |= (uint64_t)inl_dev->channel; + req->entry_data.kw_mask[0] |= + (uint64_t)inl_dev->chan_mask; + pf_func = nix_inl_dev_pffunc_get(); + req->entry_data.action &= ~(GENMASK(19, 4)); + req->entry_data.action |= (uint64_t)pf_func << 4; + + flow->npc_action &= ~(GENMASK(19, 4)); + flow->npc_action |= (uint64_t)pf_func << 4; + flow->mcam_data[0] |= (uint64_t)inl_dev->channel; + flow->mcam_mask[0] |= (uint64_t)inl_dev->chan_mask; + } else { + req->entry_data.kw[0] |= (uint64_t)npc->channel; + req->entry_data.kw_mask[0] |= (BIT_ULL(12) - 1); + flow->mcam_data[0] |= (uint64_t)npc->channel; + flow->mcam_mask[0] |= (BIT_ULL(12) - 1); + } } else { uint16_t pf_func = (flow->npc_action >> 4) & 0xffff; -- 2.8.4