From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83229A0C4C; Thu, 2 Sep 2021 04:19:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AFE47411B2; Thu, 2 Sep 2021 04:18:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8C8F7411B3 for ; Thu, 2 Sep 2021 04:18:06 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 181HQSfM012709 for ; Wed, 1 Sep 2021 19:18:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=o0s4yjX5G2quxbz74T2KF9FkL5QjwO0saYNOOSBIBC8=; b=IAbUaDf/igre5ZTS5kBbvfUi/RkIQkk9pvpWGuC9KgqM2Kscp11EW3csQ7ip/7pzvvwC ii1ApOggBv8XbWyoe1KUbyH/JxdMhmG97mqtwN2Fd0UQllcs8g3giJvU5Pdl1CFcqaEu R8rEZdLkwHqc56oY62UqX/lTIvVlVnuEy+A9W2pEUCLrTO30kGWyGd9OPBOLcULb22zV SRmB+A2r0oKTiFY7vsqGV0ByaWIiRGeUuBBZ0xqXq5cGe3f9Ecw4iChde//w7VPwa8ED zW5iM1F7O3zJDeQVa6l3v4QEZqagOpf7fof5FP3Zo3ax9dosS54TjRp+dAwseC1+o+g8 /g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3atdwq9hwa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 01 Sep 2021 19:18:05 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 1 Sep 2021 19:18:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 1 Sep 2021 19:18:03 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id BB0213F7050; Wed, 1 Sep 2021 19:18:01 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Date: Thu, 2 Sep 2021 07:45:05 +0530 Message-ID: <20210902021505.17607-28-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210902021505.17607-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: PtsEch3oFNGMZtlcyZFGWTZoy-EUOkyS X-Proofpoint-GUID: PtsEch3oFNGMZtlcyZFGWTZoy-EUOkyS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 27/27] net/cnxk: reflect globally enabled offloads in queue conf X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reflect globally enabled Rx and Tx offloads in queue conf. Also fix issue with lmt data prepare for multi seg. Fixes: a24af6361e37 ("net/cnxk: add Tx queue setup and release") Fixes: a86144cd9ded ("net/cnxk: add Rx queue setup and release") Fixes: 305ca2c4c382 ("net/cnxk: support multi-segment vector Tx") Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_tx.h | 2 +- drivers/net/cnxk/cnxk_ethdev.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index f56aa8e..2821f71 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -1280,7 +1280,7 @@ cn10k_nix_prep_lmt_mseg_vector(struct rte_mbuf **mbufs, uint64x2_t *cmd0, vst1q_u64(lmt_addr + 14, cmd1[3]); *data128 |= ((__uint128_t)7) << *shift; - shift += 3; + *shift += 3; return 1; } diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 8a102aa..978ee5b 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -377,6 +377,8 @@ cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, txq_sp->dev = dev; txq_sp->qid = qid; txq_sp->qconf.conf.tx = *tx_conf; + /* Queue config should reflect global offloads */ + txq_sp->qconf.conf.tx.offloads = dev->tx_offloads; txq_sp->qconf.nb_desc = nb_desc; plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p" @@ -511,6 +513,8 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, rxq_sp->dev = dev; rxq_sp->qid = qid; rxq_sp->qconf.conf.rx = *rx_conf; + /* Queue config should reflect global offloads */ + rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads; rxq_sp->qconf.nb_desc = nb_desc; rxq_sp->qconf.mp = mp; -- 2.8.4