From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A6D96A0C4C; Thu, 2 Sep 2021 04:17:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 71F70410E9; Thu, 2 Sep 2021 04:16:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 95EC540E01 for ; Thu, 2 Sep 2021 04:16:56 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 181HQCpe011801 for ; Wed, 1 Sep 2021 19:16:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=JkqJuxejoQXhQnC7JC+9XJVQizmQvfo4DS9/FvHOT00=; b=TSYQSFG0AhYbSB/osVMhEZ+7klUHaBe6ZVda5h0XUD85n3PmRgJiAeXLP5zVMCjMaxen azItY57YLEzdCRjIX5xCZVGqmlk9D+Sjd4C4GfnFy+VMV8WZ06VwHfV1rowCu9aCz5nz Hwb3LjOfCDCiAAiRzCKwMDeSfz7nJwdifCty7eT/y56PeEDWQCES39wodVQcNOoC39iQ M9cVUpEpdFPZCmTvJY7Ndq5XuPFXrlmp4b1RFvXWhxR/rpV1Sp0N50B/FfWJaKmQOdRL QA1A67uR9njxhd4a2vQqVBseVV0R8+f0H2ksBrHQKo6OiV1xJD/EFsZXvTZ6HDjMWJIu mA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3atdwq9hq9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 01 Sep 2021 19:16:55 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 1 Sep 2021 19:16:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 1 Sep 2021 19:16:52 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id CFB623F7040; Wed, 1 Sep 2021 19:16:50 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Date: Thu, 2 Sep 2021 07:44:41 +0530 Message-ID: <20210902021505.17607-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210902021505.17607-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: y55-lSHx8PxDPl5rGgzO1UXduCnTz6VR X-Proofpoint-GUID: y55-lSHx8PxDPl5rGgzO1UXduCnTz6VR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 03/27] common/cnxk: allow reuse of SSO API for inline dev X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Rework interface of sso internal functions to use for nix inline dev's sso LF's. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_sso.c | 52 ++++++++++++++++++++++++-------------- drivers/common/cnxk/roc_sso_priv.h | 9 +++++++ 2 files changed, 42 insertions(+), 19 deletions(-) diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 1ccf262..bdf973f 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -6,11 +6,10 @@ #include "roc_priv.h" /* Private functions. */ -static int -sso_lf_alloc(struct roc_sso *roc_sso, enum sso_lf_type lf_type, uint16_t nb_lf, +int +sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf, void **rsp) { - struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; int rc = -ENOSPC; switch (lf_type) { @@ -41,10 +40,9 @@ sso_lf_alloc(struct roc_sso *roc_sso, enum sso_lf_type lf_type, uint16_t nb_lf, return 0; } -static int -sso_lf_free(struct roc_sso *roc_sso, enum sso_lf_type lf_type, uint16_t nb_lf) +int +sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf) { - struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; int rc = -ENOSPC; switch (lf_type) { @@ -152,7 +150,7 @@ sso_rsrc_get(struct roc_sso *roc_sso) return 0; } -static void +void sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp, uint16_t hwgrp[], uint16_t n, uint16_t enable) { @@ -172,8 +170,10 @@ sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp, k = k ? k : 4; for (j = 0; j < k; j++) { mask[j] = hwgrp[i + j] | enable << 14; - enable ? plt_bitmap_set(bmp, hwgrp[i + j]) : - plt_bitmap_clear(bmp, hwgrp[i + j]); + if (bmp) { + enable ? plt_bitmap_set(bmp, hwgrp[i + j]) : + plt_bitmap_clear(bmp, hwgrp[i + j]); + } plt_sso_dbg("HWS %d Linked to HWGRP %d", hws, hwgrp[i + j]); } @@ -388,10 +388,8 @@ roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos, } int -roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, uint32_t npa_aura_id, - uint16_t hwgrps) +sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps) { - struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; struct sso_hw_setconfig *req; int rc = -ENOSPC; @@ -406,9 +404,17 @@ roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, uint32_t npa_aura_id, } int -roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps) +roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, uint32_t npa_aura_id, + uint16_t hwgrps) { struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + + return sso_hwgrp_alloc_xaq(dev, npa_aura_id, hwgrps); +} + +int +sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps) +{ struct sso_hw_xaq_release *req; req = mbox_alloc_msg_sso_hw_release_xaq_aura(dev->mbox); @@ -420,6 +426,14 @@ roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps) } int +roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + + return sso_hwgrp_release_xaq(dev, hwgrps); +} + +int roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp, uint8_t weight, uint8_t affinity, uint8_t priority) { @@ -468,13 +482,13 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp) goto hwgrp_atch_fail; } - rc = sso_lf_alloc(roc_sso, SSO_LF_TYPE_HWS, nb_hws, NULL); + rc = sso_lf_alloc(&sso->dev, SSO_LF_TYPE_HWS, nb_hws, NULL); if (rc < 0) { plt_err("Unable to alloc SSO HWS LFs"); goto hws_alloc_fail; } - rc = sso_lf_alloc(roc_sso, SSO_LF_TYPE_HWGRP, nb_hwgrp, + rc = sso_lf_alloc(&sso->dev, SSO_LF_TYPE_HWGRP, nb_hwgrp, (void **)&rsp_hwgrp); if (rc < 0) { plt_err("Unable to alloc SSO HWGRP Lfs"); @@ -503,9 +517,9 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp) return 0; sso_msix_fail: - sso_lf_free(roc_sso, SSO_LF_TYPE_HWGRP, nb_hwgrp); + sso_lf_free(&sso->dev, SSO_LF_TYPE_HWGRP, nb_hwgrp); hwgrp_alloc_fail: - sso_lf_free(roc_sso, SSO_LF_TYPE_HWS, nb_hws); + sso_lf_free(&sso->dev, SSO_LF_TYPE_HWS, nb_hws); hws_alloc_fail: sso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWGRP); hwgrp_atch_fail: @@ -523,8 +537,8 @@ roc_sso_rsrc_fini(struct roc_sso *roc_sso) sso_unregister_irqs_priv(roc_sso, &sso->pci_dev->intr_handle, roc_sso->nb_hws, roc_sso->nb_hwgrp); - sso_lf_free(roc_sso, SSO_LF_TYPE_HWS, roc_sso->nb_hws); - sso_lf_free(roc_sso, SSO_LF_TYPE_HWGRP, roc_sso->nb_hwgrp); + sso_lf_free(&sso->dev, SSO_LF_TYPE_HWS, roc_sso->nb_hws); + sso_lf_free(&sso->dev, SSO_LF_TYPE_HWGRP, roc_sso->nb_hwgrp); sso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWS); sso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWGRP); diff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h index 5361d4f..8dffa3f 100644 --- a/drivers/common/cnxk/roc_sso_priv.h +++ b/drivers/common/cnxk/roc_sso_priv.h @@ -39,6 +39,15 @@ roc_sso_to_sso_priv(struct roc_sso *roc_sso) return (struct sso *)&roc_sso->reserved[0]; } +/* SSO LF ops */ +int sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf, + void **rsp); +int sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf); +void sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp, + uint16_t hwgrp[], uint16_t n, uint16_t enable); +int sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps); +int sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps); + /* SSO IRQ */ int sso_register_irqs_priv(struct roc_sso *roc_sso, struct plt_intr_handle *handle, uint16_t nb_hws, -- 2.8.4