From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3B67FA0C47; Tue, 7 Sep 2021 18:55:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1AEDE411A4; Tue, 7 Sep 2021 18:55:06 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 9554A410EF for ; Tue, 7 Sep 2021 18:55:04 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10099"; a="207374740" X-IronPort-AV: E=Sophos;i="5.85,274,1624345200"; d="scan'208";a="207374740" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2021 09:50:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,274,1624345200"; d="scan'208";a="469268922" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by orsmga007.jf.intel.com with ESMTP; 07 Sep 2021 09:50:00 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Tue, 7 Sep 2021 17:49:25 +0100 Message-Id: <20210907164925.291904-9-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210907164925.291904-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210907164925.291904-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 8/8] app/test: add dmadev burst capacity API test X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kevin Laatz Add a test case to validate the functionality of drivers' burst capacity API implementations. Signed-off-by: Kevin Laatz Signed-off-by: Bruce Richardson --- app/test/test_dmadev.c | 68 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index 9ad865f249..98dddae6d6 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -671,6 +671,69 @@ test_enqueue_fill(int dev_id, uint16_t vchan) return 0; } +static int +test_burst_capacity(int dev_id, uint16_t vchan) +{ +#define CAP_TEST_BURST_SIZE 64 + const int ring_space = rte_dmadev_burst_capacity(dev_id, vchan); + struct rte_mbuf *src, *dst; + int i, j, iter; + int cap, ret; + bool dma_err; + + src = rte_pktmbuf_alloc(pool); + dst = rte_pktmbuf_alloc(pool); + + /* to test capacity, we enqueue elements and check capacity is reduced + * by one each time - rebaselining the expected value after each burst + * as the capacity is only for a burst. We enqueue multiple bursts to + * fill up half the ring, before emptying it again. We do this twice to + * ensure that we get to test scenarios where we get ring wrap-around + */ + for (iter = 0; iter < 2; iter++) { + for (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) { + cap = rte_dmadev_burst_capacity(dev_id, vchan); + + for (j = 0; j < CAP_TEST_BURST_SIZE; j++) { + ret = rte_dmadev_copy(dev_id, vchan, rte_pktmbuf_iova(src), + rte_pktmbuf_iova(dst), COPY_LEN, 0); + if (ret < 0) + ERR_RETURN("Error with rte_dmadev_copy\n"); + + if (rte_dmadev_burst_capacity(dev_id, vchan) != cap - (j + 1)) + ERR_RETURN("Error, ring capacity did not change as expected\n"); + } + if (rte_dmadev_submit(dev_id, vchan) < 0) + ERR_RETURN("Error, failed to submit burst\n"); + + if (cap < rte_dmadev_burst_capacity(dev_id, vchan)) + ERR_RETURN("Error, avail ring capacity has gone up, not down\n"); + } + await_hw(dev_id, vchan); + + for (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) { + ret = rte_dmadev_completed(dev_id, vchan, + CAP_TEST_BURST_SIZE, NULL, &dma_err); + if (ret != CAP_TEST_BURST_SIZE || dma_err) { + enum rte_dma_status_code status; + + rte_dmadev_completed_status(dev_id, vchan, 1, NULL, &status); + ERR_RETURN("Error with rte_dmadev_completed, %u [expected: %u], dma_err = %d, i = %u, iter = %u, status = %u\n", + ret, CAP_TEST_BURST_SIZE, dma_err, i, iter, status); + } + } + cap = rte_dmadev_burst_capacity(dev_id, vchan); + if (cap != ring_space) + ERR_RETURN("Error, ring capacity has not reset to original value, got %u, expected %u\n", + cap, ring_space); + } + + rte_pktmbuf_free(src); + rte_pktmbuf_free(dst); + + return 0; +} + static int test_dmadev_instance(uint16_t dev_id) { @@ -741,6 +804,11 @@ test_dmadev_instance(uint16_t dev_id) else if (runtest("fill", test_enqueue_fill, 1, dev_id, vchan, CHECK_ERRS) < 0) goto err; + if (rte_dmadev_burst_capacity(dev_id, vchan) == -ENOTSUP) + printf("DMA Dev %u: Burst capacity API not supported, skipping tests\n", dev_id); + else if (runtest("burst capacity", test_burst_capacity, 1, dev_id, vchan, CHECK_ERRS) < 0) + goto err; + rte_mempool_free(pool); rte_dmadev_stop(dev_id); rte_dmadev_stats_reset(dev_id, vchan); -- 2.30.2