From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E4C76A0547; Thu, 9 Sep 2021 21:42:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AED984068E; Thu, 9 Sep 2021 21:42:54 +0200 (CEST) Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by mails.dpdk.org (Postfix) with ESMTP id AE2664003E for ; Thu, 9 Sep 2021 21:42:52 +0200 (CEST) Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 189JXpIS128330 for ; Thu, 9 Sep 2021 15:42:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : content-transfer-encoding : mime-version; s=pp1; bh=dGNrptNB48s+xUdqw5t2Nq/ah6QiXReZ93vvQH+YA98=; b=g2Tt4B8yjcXcJd+7m47exhdG4XawlRBi9zo6M5udk8pEOmzytieRD8hP4fJBphaVD5zg 3pw2x9aFgQhDT1E5dRux6kMygnLwYBRxouQTSs34IPv7XRxCS+Apls74Ib25YNARN/9t 0me9nQ/LPhEfKmaIDY7LWwfP1/LJC2BuP2xzhDpCOpO0W1gfjeoTMLxFoJH5Rj82oOi7 h06kyDQ6ygiOza41+RFlcOUN1GifYjL100hhSpQZQT1FlArk93pwR7YAsns84v2uY+uJ UyNJBUnV65XnBY15zO29lej8JY+1WrwF/WYNm4lNmtjrOWaRpreaO8aSnoYvqHu5JUwG XA== Received: from ppma04dal.us.ibm.com (7a.29.35a9.ip4.static.sl-reverse.com [169.53.41.122]) by mx0a-001b2d01.pphosted.com with ESMTP id 3ay9ynewfx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 09 Sep 2021 15:42:51 -0400 Received: from pps.filterd (ppma04dal.us.ibm.com [127.0.0.1]) by ppma04dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 189JWA4k021474 for ; Thu, 9 Sep 2021 19:42:51 GMT Received: from b01cxnp23034.gho.pok.ibm.com (b01cxnp23034.gho.pok.ibm.com [9.57.198.29]) by ppma04dal.us.ibm.com with ESMTP id 3axcnk9ww9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 09 Sep 2021 19:42:51 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 189Jgo5v43385126 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Sep 2021 19:42:50 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5D0C5124053; Thu, 9 Sep 2021 19:42:50 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 414FF124055; Thu, 9 Sep 2021 19:42:50 +0000 (GMT) Received: from localhost.localdomain (unknown [9.114.224.51]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Thu, 9 Sep 2021 19:42:50 +0000 (GMT) From: David Christensen To: dev@dpdk.org Cc: David Christensen Date: Thu, 9 Sep 2021 12:42:43 -0700 Message-Id: <20210909194243.19189-1-drc@linux.vnet.ibm.com> X-Mailer: git-send-email 2.27.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Ni0aLvo9O2VH5yWoj8rdAwsRZLU6Mjd6 X-Proofpoint-ORIG-GUID: Ni0aLvo9O2VH5yWoj8rdAwsRZLU6Mjd6 Content-Transfer-Encoding: 8bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-09-09_07:2021-09-09, 2021-09-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 phishscore=0 priorityscore=1501 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109030001 definitions=main-2109090119 Subject: [dpdk-dev] [PATCH] eal/ppc: replace rte_atomicXX ops with C11 atomic builtins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Replace existing PPC assembly code for rte_atomicXX ops with compiler atomic builtins as prevously adopted by DPDK (see [1] and [2]). This has the additional benefit of resolving a POWER10 build failure due to an outstanding gcc issue which fails on the existing PPC assembly code [3]. [1] https://www.dpdk.org/blog/2021/03/26/dpdk-adopts-the-c11-memory-model/ [2] https://doc.dpdk.org/guides/rel_notes/deprecation.html [3] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98519 Signed-off-by: David Christensen --- lib/eal/ppc/include/rte_atomic.h | 231 +++---------------------------- 1 file changed, 21 insertions(+), 210 deletions(-) diff --git a/lib/eal/ppc/include/rte_atomic.h b/lib/eal/ppc/include/rte_atomic.h index 6a7e65210c..86d3f9b2a1 100644 --- a/lib/eal/ppc/include/rte_atomic.h +++ b/lib/eal/ppc/include/rte_atomic.h @@ -1,6 +1,7 @@ /* * SPDX-License-Identifier: BSD-3-Clause * Inspired from FreeBSD src/sys/powerpc/include/atomic.h + * Copyright (c) 2021 IBM Corporation * Copyright (c) 2008 Marcel Moolenaar * Copyright (c) 2001 Benno Rice * Copyright (c) 2001 David E. O'Brien @@ -16,6 +17,7 @@ extern "C" { #endif #include +#include #include "generic/rte_atomic.h" #define rte_mb() asm volatile("sync" : : : "memory") @@ -43,9 +45,6 @@ rte_atomic_thread_fence(int memorder) } /*------------------------- 16 bit atomic operations -------------------------*/ -/* To be compatible with Power7, use GCC built-in functions for 16 bit - * operations */ - #ifndef RTE_FORCE_INTRINSICS static inline int rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src) @@ -92,30 +91,8 @@ rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val) static inline int rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src) { - unsigned int ret = 0; - - asm volatile( - "\tlwsync\n" - "1:\tlwarx %[ret], 0, %[dst]\n" - "cmplw %[exp], %[ret]\n" - "bne 2f\n" - "stwcx. %[src], 0, %[dst]\n" - "bne- 1b\n" - "li %[ret], 1\n" - "b 3f\n" - "2:\n" - "stwcx. %[ret], 0, %[dst]\n" - "li %[ret], 0\n" - "3:\n" - "isync\n" - : [ret] "=&r" (ret), "=m" (*dst) - : [dst] "r" (dst), - [exp] "r" (exp), - [src] "r" (src), - "m" (*dst) - : "cc", "memory"); - - return ret; + return __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE, + __ATOMIC_ACQUIRE) ? 1 : 0; } static inline int rte_atomic32_test_and_set(rte_atomic32_t *v) @@ -126,67 +103,23 @@ static inline int rte_atomic32_test_and_set(rte_atomic32_t *v) static inline void rte_atomic32_inc(rte_atomic32_t *v) { - int t; - - asm volatile( - "1: lwarx %[t],0,%[cnt]\n" - "addic %[t],%[t],1\n" - "stwcx. %[t],0,%[cnt]\n" - "bne- 1b\n" - : [t] "=&r" (t), "=m" (v->cnt) - : [cnt] "r" (&v->cnt), "m" (v->cnt) - : "cc", "xer", "memory"); + __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE); } static inline void rte_atomic32_dec(rte_atomic32_t *v) { - int t; - - asm volatile( - "1: lwarx %[t],0,%[cnt]\n" - "addic %[t],%[t],-1\n" - "stwcx. %[t],0,%[cnt]\n" - "bne- 1b\n" - : [t] "=&r" (t), "=m" (v->cnt) - : [cnt] "r" (&v->cnt), "m" (v->cnt) - : "cc", "xer", "memory"); + __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE); } static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v) { - int ret; - - asm volatile( - "\n\tlwsync\n" - "1: lwarx %[ret],0,%[cnt]\n" - "addic %[ret],%[ret],1\n" - "stwcx. %[ret],0,%[cnt]\n" - "bne- 1b\n" - "isync\n" - : [ret] "=&r" (ret) - : [cnt] "r" (&v->cnt) - : "cc", "xer", "memory"); - - return ret == 0; + return __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0; } static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v) { - int ret; - - asm volatile( - "\n\tlwsync\n" - "1: lwarx %[ret],0,%[cnt]\n" - "addic %[ret],%[ret],-1\n" - "stwcx. %[ret],0,%[cnt]\n" - "bne- 1b\n" - "isync\n" - : [ret] "=&r" (ret) - : [cnt] "r" (&v->cnt) - : "cc", "xer", "memory"); - - return ret == 0; + return __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0; } static inline uint32_t @@ -200,29 +133,8 @@ rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val) static inline int rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src) { - unsigned int ret = 0; - - asm volatile ( - "\tlwsync\n" - "1: ldarx %[ret], 0, %[dst]\n" - "cmpld %[exp], %[ret]\n" - "bne 2f\n" - "stdcx. %[src], 0, %[dst]\n" - "bne- 1b\n" - "li %[ret], 1\n" - "b 3f\n" - "2:\n" - "stdcx. %[ret], 0, %[dst]\n" - "li %[ret], 0\n" - "3:\n" - "isync\n" - : [ret] "=&r" (ret), "=m" (*dst) - : [dst] "r" (dst), - [exp] "r" (exp), - [src] "r" (src), - "m" (*dst) - : "cc", "memory"); - return ret; + return __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE, + __ATOMIC_ACQUIRE) ? 1 : 0; } static inline void @@ -234,167 +146,66 @@ rte_atomic64_init(rte_atomic64_t *v) static inline int64_t rte_atomic64_read(rte_atomic64_t *v) { - long ret; - - asm volatile("ld%U1%X1 %[ret],%[cnt]" - : [ret] "=r"(ret) - : [cnt] "m"(v->cnt)); - - return ret; + return v->cnt; } static inline void rte_atomic64_set(rte_atomic64_t *v, int64_t new_value) { - asm volatile("std%U0%X0 %[new_value],%[cnt]" - : [cnt] "=m"(v->cnt) - : [new_value] "r"(new_value)); + v->cnt = new_value; } static inline void rte_atomic64_add(rte_atomic64_t *v, int64_t inc) { - long t; - - asm volatile( - "1: ldarx %[t],0,%[cnt]\n" - "add %[t],%[inc],%[t]\n" - "stdcx. %[t],0,%[cnt]\n" - "bne- 1b\n" - : [t] "=&r" (t), "=m" (v->cnt) - : [cnt] "r" (&v->cnt), [inc] "r" (inc), "m" (v->cnt) - : "cc", "memory"); + __atomic_add_fetch(&v->cnt, inc, __ATOMIC_ACQUIRE); } static inline void rte_atomic64_sub(rte_atomic64_t *v, int64_t dec) { - long t; - - asm volatile( - "1: ldarx %[t],0,%[cnt]\n" - "subf %[t],%[dec],%[t]\n" - "stdcx. %[t],0,%[cnt]\n" - "bne- 1b\n" - : [t] "=&r" (t), "+m" (v->cnt) - : [cnt] "r" (&v->cnt), [dec] "r" (dec), "m" (v->cnt) - : "cc", "memory"); + __atomic_sub_fetch(&v->cnt, dec, __ATOMIC_ACQUIRE); } static inline void rte_atomic64_inc(rte_atomic64_t *v) { - long t; - - asm volatile( - "1: ldarx %[t],0,%[cnt]\n" - "addic %[t],%[t],1\n" - "stdcx. %[t],0,%[cnt]\n" - "bne- 1b\n" - : [t] "=&r" (t), "+m" (v->cnt) - : [cnt] "r" (&v->cnt), "m" (v->cnt) - : "cc", "xer", "memory"); + __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE); } static inline void rte_atomic64_dec(rte_atomic64_t *v) { - long t; - - asm volatile( - "1: ldarx %[t],0,%[cnt]\n" - "addic %[t],%[t],-1\n" - "stdcx. %[t],0,%[cnt]\n" - "bne- 1b\n" - : [t] "=&r" (t), "+m" (v->cnt) - : [cnt] "r" (&v->cnt), "m" (v->cnt) - : "cc", "xer", "memory"); + __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE); } static inline int64_t rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc) { - long ret; - - asm volatile( - "\n\tlwsync\n" - "1: ldarx %[ret],0,%[cnt]\n" - "add %[ret],%[inc],%[ret]\n" - "stdcx. %[ret],0,%[cnt]\n" - "bne- 1b\n" - "isync\n" - : [ret] "=&r" (ret) - : [inc] "r" (inc), [cnt] "r" (&v->cnt) - : "cc", "memory"); - - return ret; + return __atomic_add_fetch(&v->cnt, inc, __ATOMIC_ACQUIRE); } static inline int64_t rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec) { - long ret; - - asm volatile( - "\n\tlwsync\n" - "1: ldarx %[ret],0,%[cnt]\n" - "subf %[ret],%[dec],%[ret]\n" - "stdcx. %[ret],0,%[cnt]\n" - "bne- 1b\n" - "isync\n" - : [ret] "=&r" (ret) - : [dec] "r" (dec), [cnt] "r" (&v->cnt) - : "cc", "memory"); - - return ret; + return __atomic_sub_fetch(&v->cnt, dec, __ATOMIC_ACQUIRE); } static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v) { - long ret; - - asm volatile( - "\n\tlwsync\n" - "1: ldarx %[ret],0,%[cnt]\n" - "addic %[ret],%[ret],1\n" - "stdcx. %[ret],0,%[cnt]\n" - "bne- 1b\n" - "isync\n" - : [ret] "=&r" (ret) - : [cnt] "r" (&v->cnt) - : "cc", "xer", "memory"); - - return ret == 0; + return __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0; } static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v) { - long ret; - - asm volatile( - "\n\tlwsync\n" - "1: ldarx %[ret],0,%[cnt]\n" - "addic %[ret],%[ret],-1\n" - "stdcx. %[ret],0,%[cnt]\n" - "bne- 1b\n" - "isync\n" - : [ret] "=&r" (ret) - : [cnt] "r" (&v->cnt) - : "cc", "xer", "memory"); - - return ret == 0; + return __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0; } static inline int rte_atomic64_test_and_set(rte_atomic64_t *v) { return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1); } -/** - * Atomically set a 64-bit counter to 0. - * - * @param v - * A pointer to the atomic counter. - */ + static inline void rte_atomic64_clear(rte_atomic64_t *v) { v->cnt = 0; -- 2.27.0