* [dpdk-dev] [PATCH v1 0/2] support L4 for QinQ switch filter
@ 2021-09-10 8:54 Steve Yang
2021-09-10 8:54 ` [dpdk-dev] [PATCH v1 1/2] net/ice: add L4 support " Steve Yang
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Steve Yang @ 2021-09-10 8:54 UTC (permalink / raw)
To: dev; +Cc: qiming.yang, qi.z.zhang, Steve Yang
The requirement to support filter by
dst MAC + outer VLAN id + inner VLAN id + dst IP + dst port.
Currently we only support pattern eth / vlan/ vlan/ IP,
in switch filter, the request to add l4 support as
eth / vlan / vlan / IP / udp|tcp.
Steve Yang (2):
net/ice: add L4 support for QinQ switch filter
net/ice/base: support L4 for QinQ switch filter
drivers/net/ice/base/ice_switch.c | 173 +++++++++++++++++++++++++++-
drivers/net/ice/ice_generic_flow.c | 4 +
drivers/net/ice/ice_switch_filter.c | 20 ++++
3 files changed, 192 insertions(+), 5 deletions(-)
--
2.27.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [dpdk-dev] [PATCH v1 1/2] net/ice: add L4 support for QinQ switch filter
2021-09-10 8:54 [dpdk-dev] [PATCH v1 0/2] support L4 for QinQ switch filter Steve Yang
@ 2021-09-10 8:54 ` Steve Yang
2021-09-10 8:54 ` [dpdk-dev] [PATCH v1 2/2] net/ice/base: support L4 " Steve Yang
2021-09-16 7:14 ` [dpdk-dev] [PATCH v1 0/2] " Zhang, Qi Z
2 siblings, 0 replies; 4+ messages in thread
From: Steve Yang @ 2021-09-10 8:54 UTC (permalink / raw)
To: dev; +Cc: qiming.yang, qi.z.zhang, Steve Yang
Add L4 support for QinQ switch filter as following flow patterns:
eth / vlan / vlan / ipv4 / udp
eth / vlan / vlan / ipv4 / tcp
eth / vlan / vlan / ipv6 / udp
eth / vlan / vlan / ipv6 / tcp
Signed-off-by: Steve Yang <stevex.yang@intel.com>
---
drivers/net/ice/ice_generic_flow.c | 4 ++++
drivers/net/ice/ice_switch_filter.c | 20 ++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c
index c2fa75f165..9e03c2856c 100644
--- a/drivers/net/ice/ice_generic_flow.c
+++ b/drivers/net/ice/ice_generic_flow.c
@@ -2134,11 +2134,15 @@ static struct ice_ptype_match ice_ptype_map[] = {
{pattern_eth_arp, ICE_PTYPE_MAC_PAY},
{pattern_eth_vlan_ipv4, ICE_PTYPE_IPV4_PAY},
{pattern_eth_qinq_ipv4, ICE_PTYPE_IPV4_PAY},
+ {pattern_eth_qinq_ipv4_udp, ICE_PTYPE_IPV4_UDP_PAY},
+ {pattern_eth_qinq_ipv4_tcp, ICE_PTYPE_IPV4_TCP_PAY},
{pattern_eth_vlan_ipv4_udp, ICE_PTYPE_IPV4_UDP_PAY},
{pattern_eth_vlan_ipv4_tcp, ICE_PTYPE_IPV4_TCP_PAY},
{pattern_eth_vlan_ipv4_sctp, ICE_PTYPE_IPV4_SCTP_PAY},
{pattern_eth_vlan_ipv6, ICE_PTYPE_IPV6_PAY},
{pattern_eth_qinq_ipv6, ICE_PTYPE_IPV6_PAY},
+ {pattern_eth_qinq_ipv6_udp, ICE_PTYPE_IPV6_UDP_PAY},
+ {pattern_eth_qinq_ipv6_tcp, ICE_PTYPE_IPV6_TCP_PAY},
{pattern_eth_vlan_ipv6_udp, ICE_PTYPE_IPV6_UDP_PAY},
{pattern_eth_vlan_ipv6_tcp, ICE_PTYPE_IPV6_TCP_PAY},
{pattern_eth_vlan_ipv6_sctp, ICE_PTYPE_IPV6_SCTP_PAY},
diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c
index f222cb9cb0..bbd2805c37 100644
--- a/drivers/net/ice/ice_switch_filter.c
+++ b/drivers/net/ice/ice_switch_filter.c
@@ -44,6 +44,12 @@
ICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS)
#define ICE_SW_INSET_MAC_QINQ_IPV4 ( \
ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV4)
+#define ICE_SW_INSET_MAC_QINQ_IPV4_TCP ( \
+ ICE_SW_INSET_MAC_QINQ_IPV4 | \
+ ICE_INSET_TCP_DST_PORT | ICE_INSET_TCP_SRC_PORT)
+#define ICE_SW_INSET_MAC_QINQ_IPV4_UDP ( \
+ ICE_SW_INSET_MAC_QINQ_IPV4 | \
+ ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT)
#define ICE_SW_INSET_MAC_IPV4_TCP ( \
ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \
ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | \
@@ -58,6 +64,12 @@
ICE_INSET_IPV6_NEXT_HDR)
#define ICE_SW_INSET_MAC_QINQ_IPV6 ( \
ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV6)
+#define ICE_SW_INSET_MAC_QINQ_IPV6_TCP ( \
+ ICE_SW_INSET_MAC_QINQ_IPV6 | \
+ ICE_INSET_TCP_DST_PORT | ICE_INSET_TCP_SRC_PORT)
+#define ICE_SW_INSET_MAC_QINQ_IPV6_UDP ( \
+ ICE_SW_INSET_MAC_QINQ_IPV6 | \
+ ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT)
#define ICE_SW_INSET_MAC_IPV6_TCP ( \
ICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \
ICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_IPV6_TC | \
@@ -216,7 +228,11 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = {
{pattern_eth_ipv4_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_ipv6_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv4, ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv4_tcp, ICE_SW_INSET_MAC_QINQ_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv4_udp, ICE_SW_INSET_MAC_QINQ_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv6, ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv6_tcp, ICE_SW_INSET_MAC_QINQ_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv6_udp, ICE_SW_INSET_MAC_QINQ_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_proto, ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_ipv4, ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
@@ -295,7 +311,11 @@ ice_pattern_match_item ice_switch_pattern_perm_list[] = {
{pattern_eth_ipv4_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_ipv6_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv4, ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv4_tcp, ICE_SW_INSET_MAC_QINQ_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv4_udp, ICE_SW_INSET_MAC_QINQ_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv6, ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv6_tcp, ICE_SW_INSET_MAC_QINQ_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv6_udp, ICE_SW_INSET_MAC_QINQ_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_proto, ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_ipv4, ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
--
2.27.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [dpdk-dev] [PATCH v1 2/2] net/ice/base: support L4 for QinQ switch filter
2021-09-10 8:54 [dpdk-dev] [PATCH v1 0/2] support L4 for QinQ switch filter Steve Yang
2021-09-10 8:54 ` [dpdk-dev] [PATCH v1 1/2] net/ice: add L4 support " Steve Yang
@ 2021-09-10 8:54 ` Steve Yang
2021-09-16 7:14 ` [dpdk-dev] [PATCH v1 0/2] " Zhang, Qi Z
2 siblings, 0 replies; 4+ messages in thread
From: Steve Yang @ 2021-09-10 8:54 UTC (permalink / raw)
To: dev; +Cc: qiming.yang, qi.z.zhang, Steve Yang
This patch adds more dummy packet types for QinQ packet,
it enables tcp/udp layer of ipv4/ipv6 for QinQ payload,
so we can use L4 dst/src port as input set for switch
filter.
For Example:
flow create 0 ingress pattern eth / vlan tci is 2 / vlan tci is 1 \
/ ipv4 src is 10.1.1.1 / tcp src is 400 / end actions vf id 1 / end
Signed-off-by: Steve Yang <stevex.yang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 173 +++++++++++++++++++++++++++++-
1 file changed, 168 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 9179f66c20..5da8d650da 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -1660,7 +1660,7 @@ static const struct ice_dummy_pkt_offsets dummy_qinq_ipv4_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
- { ICE_ETYPE_OL, 20 },
+ { ICE_ETYPE_OL, 20 },
{ ICE_IPV4_OFOS, 22 },
{ ICE_PROTOCOL_LAST, 0 },
};
@@ -1674,6 +1674,35 @@ static const u8 dummy_qinq_ipv4_pkt[] = {
0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
0x08, 0x00, /* ICE_ETYPE_OL 20 */
+ 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_OFOS 22 */
+ 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x00, 0x00, /* 2 bytes for 4 byte alignment */
+};
+
+static const
+struct ice_dummy_pkt_offsets dummy_qinq_ipv4_udp_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
+ { ICE_IPV4_OFOS, 22 },
+ { ICE_UDP_ILOS, 42 },
+ { ICE_PROTOCOL_LAST, 0 },
+};
+
+static const u8 dummy_qinq_ipv4_udp_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
+ 0x08, 0x00, /* ICE_ETYPE_OL 20 */
+
0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 22 */
0x00, 0x01, 0x00, 0x00,
0x00, 0x11, 0x00, 0x00,
@@ -1686,11 +1715,46 @@ static const u8 dummy_qinq_ipv4_pkt[] = {
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
+static const
+struct ice_dummy_pkt_offsets dummy_qinq_ipv4_tcp_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
+ { ICE_IPV4_OFOS, 22 },
+ { ICE_TCP_IL, 42 },
+ { ICE_PROTOCOL_LAST, 0 },
+};
+
+static const u8 dummy_qinq_ipv4_tcp_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
+ 0x08, 0x00, /* ICE_ETYPE_OL 20 */
+
+ 0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_OFOS 22 */
+ 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x06, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 42 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x50, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x00, 0x00, /* 2 bytes for 4 byte alignment */
+};
+
static const struct ice_dummy_pkt_offsets dummy_qinq_ipv6_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_VLAN_EX, 12 },
{ ICE_VLAN_IN, 16 },
- { ICE_ETYPE_OL, 20 },
+ { ICE_ETYPE_OL, 20 },
{ ICE_IPV6_OFOS, 22 },
{ ICE_PROTOCOL_LAST, 0 },
};
@@ -1705,7 +1769,41 @@ static const u8 dummy_qinq_ipv6_pkt[] = {
0x86, 0xDD, /* ICE_ETYPE_OL 20 */
0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */
- 0x00, 0x10, 0x11, 0x00, /* Next header UDP */
+ 0x00, 0x00, 0x3b, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x00, 0x00, /* 2 bytes for 4 byte alignment */
+};
+
+static const
+struct ice_dummy_pkt_offsets dummy_qinq_ipv6_udp_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
+ { ICE_IPV6_OFOS, 22 },
+ { ICE_UDP_ILOS, 62 },
+ { ICE_PROTOCOL_LAST, 0 },
+};
+
+static const u8 dummy_qinq_ipv6_udp_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
+ 0x86, 0xDD, /* ICE_ETYPE_OL 20 */
+
+ 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */
+ 0x00, 0x08, 0x11, 0x00, /* Next header UDP */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
@@ -1716,9 +1814,46 @@ static const u8 dummy_qinq_ipv6_pkt[] = {
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 62 */
- 0x00, 0x10, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, /* needed for ESP packets */
+ 0x00, 0x00, /* 2 bytes for 4 byte alignment */
+};
+
+static const
+struct ice_dummy_pkt_offsets dummy_qinq_ipv6_tcp_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
+ { ICE_IPV6_OFOS, 22 },
+ { ICE_TCP_IL, 62 },
+ { ICE_PROTOCOL_LAST, 0 },
+};
+
+static const u8 dummy_qinq_ipv6_tcp_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
+ 0x86, 0xDD, /* ICE_ETYPE_OL 20 */
+
+ 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */
+ 0x00, 0x14, 0x06, 0x00, /* Next header TCP */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 62 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x50, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, /* 2 bytes for 4 byte alignment */
@@ -7918,12 +8053,40 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
if ((tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||
tun_type == ICE_NON_TUN_QINQ) && ipv6) {
+ if (tcp) {
+ *pkt = dummy_qinq_ipv6_tcp_pkt;
+ *pkt_len = sizeof(dummy_qinq_ipv6_tcp_pkt);
+ *offsets = dummy_qinq_ipv6_tcp_packet_offsets;
+ return;
+ }
+
+ if (udp) {
+ *pkt = dummy_qinq_ipv6_udp_pkt;
+ *pkt_len = sizeof(dummy_qinq_ipv6_udp_pkt);
+ *offsets = dummy_qinq_ipv6_udp_packet_offsets;
+ return;
+ }
+
*pkt = dummy_qinq_ipv6_pkt;
*pkt_len = sizeof(dummy_qinq_ipv6_pkt);
*offsets = dummy_qinq_ipv6_packet_offsets;
return;
} else if (tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||
tun_type == ICE_NON_TUN_QINQ) {
+ if (tcp) {
+ *pkt = dummy_qinq_ipv4_tcp_pkt;
+ *pkt_len = sizeof(dummy_qinq_ipv4_tcp_pkt);
+ *offsets = dummy_qinq_ipv4_tcp_packet_offsets;
+ return;
+ }
+
+ if (udp) {
+ *pkt = dummy_qinq_ipv4_udp_pkt;
+ *pkt_len = sizeof(dummy_qinq_ipv4_udp_pkt);
+ *offsets = dummy_qinq_ipv4_udp_packet_offsets;
+ return;
+ }
+
*pkt = dummy_qinq_ipv4_pkt;
*pkt_len = sizeof(dummy_qinq_ipv4_pkt);
*offsets = dummy_qinq_ipv4_packet_offsets;
--
2.27.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [dpdk-dev] [PATCH v1 0/2] support L4 for QinQ switch filter
2021-09-10 8:54 [dpdk-dev] [PATCH v1 0/2] support L4 for QinQ switch filter Steve Yang
2021-09-10 8:54 ` [dpdk-dev] [PATCH v1 1/2] net/ice: add L4 support " Steve Yang
2021-09-10 8:54 ` [dpdk-dev] [PATCH v1 2/2] net/ice/base: support L4 " Steve Yang
@ 2021-09-16 7:14 ` Zhang, Qi Z
2 siblings, 0 replies; 4+ messages in thread
From: Zhang, Qi Z @ 2021-09-16 7:14 UTC (permalink / raw)
To: Yang, SteveX, dev; +Cc: Yang, Qiming
> -----Original Message-----
> From: Yang, SteveX <stevex.yang@intel.com>
> Sent: Friday, September 10, 2021 4:55 PM
> To: dev@dpdk.org
> Cc: Yang, Qiming <qiming.yang@intel.com>; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Yang, SteveX <stevex.yang@intel.com>
> Subject: [PATCH v1 0/2] support L4 for QinQ switch filter
>
> The requirement to support filter by
> dst MAC + outer VLAN id + inner VLAN id + dst IP + dst port.
>
> Currently we only support pattern eth / vlan/ vlan/ IP, in switch filter, the
> request to add l4 support as eth / vlan / vlan / IP / udp|tcp.
>
> Steve Yang (2):
> net/ice: add L4 support for QinQ switch filter
> net/ice/base: support L4 for QinQ switch filter
>
> drivers/net/ice/base/ice_switch.c | 173 +++++++++++++++++++++++++++-
> drivers/net/ice/ice_generic_flow.c | 4 +
> drivers/net/ice/ice_switch_filter.c | 20 ++++
> 3 files changed, 192 insertions(+), 5 deletions(-)
>
> --
> 2.27.0
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Applied to dpdk-next-net-intel.
Thanks
Qi
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-09-16 7:14 UTC | newest]
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