* [dpdk-dev] [PATCH 01/12] net/ice/base: calculate logical PF ID
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
@ 2021-09-16 9:52 ` Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 02/12] net/ice/base: include more E810T adapters Qi Zhang
` (11 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:52 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, stable, Dan Nowlin
In some devices, the function numbers used are non-contiguous. For
example, some two port devices will report as functions 0 and 2.
When distributing RSS and FDIR masks, which are global resources across
the active devices, it is required to have a contiguous PF id, which can
be described as a logical PF id. In the case above, function 0 would
have a logical PF id of 0, and function 2 would have a logical PF id of
1.
Cc: stable@dpdk.org
Using logical PF id can properly describe which slice of resources can
be used by a particular PF.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 19 +++++++++++++++++++
drivers/net/ice/base/ice_flex_pipe.c | 2 +-
drivers/net/ice/base/ice_type.h | 1 +
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 641859f752..6004c95625 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2535,6 +2535,23 @@ ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
ice_recalc_port_limited_caps(hw, &func_p->common_cap);
}
+/**
+ * ice_func_id_to_logical_id - map from function id to logical pf id
+ * @active_function_bitmap: active function bitmap
+ * @pf_id: function number of device
+ */
+static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id)
+{
+ u8 logical_id = 0;
+ u8 i;
+
+ for (i = 0; i < pf_id; i++)
+ if (active_function_bitmap & BIT(i))
+ logical_id++;
+
+ return logical_id;
+}
+
/**
* ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
* @hw: pointer to the HW struct
@@ -2552,6 +2569,8 @@ ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
dev_p->num_funcs = ice_hweight32(number);
ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
dev_p->num_funcs);
+
+ hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id);
}
/**
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index fd98b3837d..8a6fc8a9a5 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -3432,7 +3432,7 @@ static void ice_init_prof_masks(struct ice_hw *hw, enum ice_block blk)
per_pf = ICE_PROF_MASK_COUNT / hw->dev_caps.num_funcs;
hw->blk[blk].masks.count = per_pf;
- hw->blk[blk].masks.first = hw->pf_id * per_pf;
+ hw->blk[blk].masks.first = hw->logical_pf_id * per_pf;
ice_memset(hw->blk[blk].masks.masks, 0,
sizeof(hw->blk[blk].masks.masks), ICE_NONDMA_MEM);
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 56ee628f10..b1e03b10ff 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1132,6 +1132,7 @@ struct ice_hw {
u8 revision_id;
u8 pf_id; /* device profile info */
+ u8 logical_pf_id;
u16 max_burst_size; /* driver sets this value */
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 02/12] net/ice/base: include more E810T adapters
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 01/12] net/ice/base: calculate logical PF ID Qi Zhang
@ 2021-09-16 9:52 ` Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 03/12] net/ice/base: use macro instead of open-coded division Qi Zhang
` (10 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:52 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Maciej Machnikowski
Expand the ice_is_e810t to include:
- Intel(R) Ethernet Network Adapter E810-C-Q2T
- Intel(R) Ethernet 25G 4P E810-XXV-st
Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 17 +++++++++++++++--
drivers/net/ice/base/ice_devids.h | 1 +
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 6004c95625..a7804219d8 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -208,8 +208,21 @@ bool ice_is_e810(struct ice_hw *hw)
*/
bool ice_is_e810t(struct ice_hw *hw)
{
- return (hw->device_id == ICE_DEV_ID_E810C_SFP &&
- hw->subsystem_device_id == ICE_SUBDEV_ID_E810T);
+ switch (hw->device_id) {
+ case ICE_DEV_ID_E810C_SFP:
+ if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T ||
+ hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
+ return true;
+ break;
+ case ICE_DEV_ID_E810C_QSFP:
+ if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
+ return true;
+ break;
+ default:
+ break;
+ }
+
+ return false;
}
/**
diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h
index 18397f1925..e52bb71403 100644
--- a/drivers/net/ice/base/ice_devids.h
+++ b/drivers/net/ice/base/ice_devids.h
@@ -23,6 +23,7 @@
/* Intel(R) Ethernet Controller E810-C for SFP */
#define ICE_DEV_ID_E810C_SFP 0x1593
#define ICE_SUBDEV_ID_E810T 0x000E
+#define ICE_SUBDEV_ID_E810T2 0x000F
/* Intel(R) Ethernet Controller E810-XXV for backplane */
#define ICE_DEV_ID_E810_XXV_BACKPLANE 0x1599
/* Intel(R) Ethernet Controller E810-XXV for QSFP */
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 03/12] net/ice/base: use macro instead of open-coded division
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 01/12] net/ice/base: calculate logical PF ID Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 02/12] net/ice/base: include more E810T adapters Qi Zhang
@ 2021-09-16 9:52 ` Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 04/12] net/ice/base: allow to enable LAN and loopback in switch Qi Zhang
` (9 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:52 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Jacob Keller
For some operating systems, 64-bit division requires using specific
implementations. Use the DIV_64BIT macro to replace open-coded division
so that the driver may convert this to the appropriate operating-system
specific implementation when necessary.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 53 +++++++++++++++++++------------
1 file changed, 32 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 8ea75538fa..70eb87abf9 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1634,7 +1634,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
#define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
/* Program the 10Gb/40Gb conversion ratio */
- uix = (tu_per_sec * LINE_UI_10G_40G) / 390625000;
+ uix = DIV_64BIT(tu_per_sec * LINE_UI_10G_40G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
uix);
@@ -1645,7 +1645,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
}
/* Program the 25Gb/100Gb conversion ratio */
- uix = (tu_per_sec * LINE_UI_25G_100G) / 390625000;
+ uix = DIV_64BIT(tu_per_sec * LINE_UI_25G_100G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
uix);
@@ -1727,7 +1727,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_par_clk)
- phy_tus = tu_per_sec / e822_vernier[link_spd].tx_par_clk;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].tx_par_clk);
else
phy_tus = 0;
@@ -1738,7 +1739,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_par_clk)
- phy_tus = tu_per_sec / e822_vernier[link_spd].rx_par_clk;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].rx_par_clk);
else
phy_tus = 0;
@@ -1749,7 +1751,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_pcs_clk)
- phy_tus = tu_per_sec / e822_vernier[link_spd].tx_pcs_clk;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].tx_pcs_clk);
else
phy_tus = 0;
@@ -1760,7 +1763,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_pcs_clk)
- phy_tus = tu_per_sec / e822_vernier[link_spd].rx_pcs_clk;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].rx_pcs_clk);
else
phy_tus = 0;
@@ -1771,7 +1775,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_par)
- phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_par;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].tx_desk_rsgb_par);
else
phy_tus = 0;
@@ -1782,7 +1787,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_desk_rsgb_par)
- phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_par;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].rx_desk_rsgb_par);
else
phy_tus = 0;
@@ -1793,7 +1799,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
- phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_pcs;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].tx_desk_rsgb_pcs);
else
phy_tus = 0;
@@ -1804,7 +1811,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
- phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_pcs;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].rx_desk_rsgb_pcs);
else
phy_tus = 0;
@@ -1836,9 +1844,9 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
* overflows 64 bit integer arithmetic, so break it up into two
* divisions by 1e4 first then by 1e7.
*/
- fixed_offset = tu_per_sec / 10000;
+ fixed_offset = DIV_64BIT(tu_per_sec, 10000);
fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
- fixed_offset /= 10000000;
+ fixed_offset = DIV_64BIT(fixed_offset, 10000000);
return fixed_offset;
}
@@ -1982,9 +1990,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
{
u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
+ u32 pmd_adj_divisor, val;
enum ice_status status;
u8 pmd_align;
- u32 val;
status = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);
if (status) {
@@ -2001,6 +2009,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
/* Calculate TUs per second */
tu_per_sec = cur_freq * clk_incval;
+ /* Get the link speed dependent PMD adjustment divisor */
+ pmd_adj_divisor = e822_vernier[link_spd].pmd_adj_divisor;
+
/* The PMD alignment adjustment measurement depends on the link speed,
* and whether FEC is enabled. For each link speed, the alignment
* adjustment is calculated by dividing a value by the length of
@@ -2063,9 +2074,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
* divide by 125, and then handle remaining divisor based on the link
* speed pmd_adj_divisor value.
*/
- adj = tu_per_sec / 125;
+ adj = DIV_64BIT(tu_per_sec, 125);
adj *= mult;
- adj /= e822_vernier[link_spd].pmd_adj_divisor;
+ adj = DIV_64BIT(adj, pmd_adj_divisor);
/* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
* cycle count is necessary.
@@ -2086,9 +2097,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
if (rx_cycle) {
mult = (4 - rx_cycle) * 40;
- cycle_adj = tu_per_sec / 125;
+ cycle_adj = DIV_64BIT(tu_per_sec, 125);
cycle_adj *= mult;
- cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
+ cycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);
adj += cycle_adj;
}
@@ -2108,9 +2119,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
if (rx_cycle) {
mult = rx_cycle * 40;
- cycle_adj = tu_per_sec / 125;
+ cycle_adj = DIV_64BIT(tu_per_sec, 125);
cycle_adj *= mult;
- cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
+ cycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);
adj += cycle_adj;
}
@@ -2146,9 +2157,9 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
* overflows 64 bit integer arithmetic, so break it up into two
* divisions by 1e4 first then by 1e7.
*/
- fixed_offset = tu_per_sec / 10000;
+ fixed_offset = DIV_64BIT(tu_per_sec, 10000);
fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
- fixed_offset /= 10000000;
+ fixed_offset = DIV_64BIT(fixed_offset, 10000000);
return fixed_offset;
}
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 04/12] net/ice/base: allow to enable LAN and loopback in switch
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (2 preceding siblings ...)
2021-09-16 9:52 ` [dpdk-dev] [PATCH 03/12] net/ice/base: use macro instead of open-coded division Qi Zhang
@ 2021-09-16 9:52 ` Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 05/12] net/ice/base: change addr param to u16 Qi Zhang
` (8 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:52 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Wojciech Drewek
Currently shared code API oes not allow to set/unset lb_en
and lan_en flags for advanced rules during their creation.
Because of that we have to use a workaround in switchdev
which is to update rule immediately after its creation.
This change will allow us to set/unset those flags right
away.
Signed-off-by: Wojciech Drewek <wojciech.drewek@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 7 ++++++-
drivers/net/ice/base/ice_switch.h | 11 +++++++++++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 93cd79e8ef..b945e1499d 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -8750,7 +8750,12 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
s_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rule_buf_sz);
if (!s_rule)
return ICE_ERR_NO_MEMORY;
- act |= ICE_SINGLE_ACT_LAN_ENABLE;
+ if (!rinfo->flags_info.act_valid)
+ act |= ICE_SINGLE_ACT_LAN_ENABLE;
+ else
+ act |= rinfo->flags_info.act & (ICE_SINGLE_ACT_LAN_ENABLE |
+ ICE_SINGLE_ACT_LB_ENABLE);
+
switch (rinfo->sw_act.fltr_act) {
case ICE_FWD_TO_VSI:
act |= (rinfo->sw_act.fwd_id.hw_vsi_id <<
diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h
index 980bae5806..a2b3c80107 100644
--- a/drivers/net/ice/base/ice_switch.h
+++ b/drivers/net/ice/base/ice_switch.h
@@ -250,12 +250,23 @@ struct ice_rule_query_data {
u16 vsi_handle;
};
+/* This structure allows to pass info about lb_en and lan_en
+ * flags to ice_add_adv_rule. Values in act would be used
+ * only if act_valid was set to true, otherwise dflt
+ * values would be used.
+ */
+struct ice_adv_rule_flags_info {
+ u32 act;
+ u8 act_valid; /* indicate if flags in act are valid */
+};
+
struct ice_adv_rule_info {
enum ice_sw_tunnel_type tun_type;
struct ice_sw_act_ctrl sw_act;
u32 priority;
u8 rx; /* true means LOOKUP_RX otherwise LOOKUP_TX */
u16 fltr_rule_id;
+ struct ice_adv_rule_flags_info flags_info;
};
/* A collection of one or more four word recipe */
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 05/12] net/ice/base: change addr param to u16
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (3 preceding siblings ...)
2021-09-16 9:52 ` [dpdk-dev] [PATCH 04/12] net/ice/base: allow to enable LAN and loopback in switch Qi Zhang
@ 2021-09-16 9:52 ` Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 06/12] net/ice/base: allow tool access to MNG register Qi Zhang
` (7 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:52 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Chinh T Cao
Change one of the input parameter (addr) in ice_read_cgu_reg_e822 and
ice_write_cgu_reg_e822 functions. This will avoid the shrink down
conversion from addr to cgu_msg.msg_addr_low.
Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 70eb87abf9..9ed335349b 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -709,7 +709,7 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)
* applicable to E822 devices.
*/
static enum ice_status
-ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val)
+ice_read_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 *val)
{
struct ice_sbq_msg_input cgu_msg;
enum ice_status status;
@@ -741,7 +741,7 @@ ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val)
* applicable to E822 devices.
*/
static enum ice_status
-ice_write_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 val)
+ice_write_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 val)
{
struct ice_sbq_msg_input cgu_msg;
enum ice_status status;
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 06/12] net/ice/base: allow tool access to MNG register
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (4 preceding siblings ...)
2021-09-16 9:52 ` [dpdk-dev] [PATCH 05/12] net/ice/base: change addr param to u16 Qi Zhang
@ 2021-09-16 9:52 ` Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 07/12] net/ice/base: add package segment ID Qi Zhang
` (6 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:52 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Anirudh Venkataramanan
E810-T supports signed netlists and to support this, the NVM update
tool needs to be able to read the GL_MNG_DEF_DEVID register. Add
said register to the allowlist in ice_validate_nvm_rw_reg.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_nvm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index aeb4da9ed1..2b76a11e22 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -4,6 +4,8 @@
#include "ice_common.h"
+#define GL_MNG_DEF_DEVID 0x000B611C
+
/**
* ice_aq_read_nvm
* @hw: pointer to the HW struct
@@ -1203,6 +1205,7 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
case GLGEN_CSR_DEBUG_C:
case GLGEN_RSTAT:
case GLPCI_LBARCTRL:
+ case GL_MNG_DEF_DEVID:
case GLNVM_GENS:
case GLNVM_FLA:
case PF_FUNC_RID:
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 07/12] net/ice/base: add package segment ID
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (5 preceding siblings ...)
2021-09-16 9:52 ` [dpdk-dev] [PATCH 06/12] net/ice/base: allow tool access to MNG register Qi Zhang
@ 2021-09-16 9:52 ` Qi Zhang
2021-09-16 9:53 ` [dpdk-dev] [PATCH 08/12] net/ice/base: add a helper to check for 100M speed support Qi Zhang
` (5 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:52 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Dan Nowlin
DDP package format is shared with different devices, for E810 device
we only support SEGMENT_TYPE_ICE_810.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 9 +++++++--
drivers/net/ice/base/ice_flex_type.h | 2 +-
drivers/net/ice/base/ice_type.h | 1 +
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 8a6fc8a9a5..3631ddba2c 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1263,8 +1263,13 @@ ice_init_pkg_info(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr)
if (!pkg_hdr)
return ICE_ERR_PARAM;
+ hw->pkg_seg_id = SEGMENT_TYPE_ICE_E810;
+
+ ice_debug(hw, ICE_DBG_INIT, "Pkg using segment id: 0x%08X\n",
+ hw->pkg_seg_id);
+
seg_hdr = (struct ice_generic_seg_hdr *)
- ice_find_seg_in_pkg(hw, SEGMENT_TYPE_ICE, pkg_hdr);
+ ice_find_seg_in_pkg(hw, hw->pkg_seg_id, pkg_hdr);
if (seg_hdr) {
struct ice_meta_sect *meta;
struct ice_pkg_enum state;
@@ -1496,7 +1501,7 @@ ice_chk_pkg_compat(struct ice_hw *hw, struct ice_pkg_hdr *ospkg,
}
/* find ICE segment in given package */
- *seg = (struct ice_seg *)ice_find_seg_in_pkg(hw, SEGMENT_TYPE_ICE,
+ *seg = (struct ice_seg *)ice_find_seg_in_pkg(hw, hw->pkg_seg_id,
ospkg);
if (!*seg) {
ice_debug(hw, ICE_DBG_INIT, "no ice segment in package.\n");
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index 247b85a192..3f2038c931 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -33,7 +33,7 @@ struct ice_pkg_hdr {
/* generic segment */
struct ice_generic_seg_hdr {
#define SEGMENT_TYPE_METADATA 0x00000001
-#define SEGMENT_TYPE_ICE 0x00000010
+#define SEGMENT_TYPE_ICE_E810 0x00000010
__le32 seg_type;
struct ice_pkg_ver seg_format_ver;
__le32 seg_size;
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index b1e03b10ff..b2b3291fb7 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1208,6 +1208,7 @@ struct ice_hw {
/* Active package version (currently active) */
struct ice_pkg_ver active_pkg_ver;
+ u32 pkg_seg_id;
u32 active_track_id;
u8 active_pkg_name[ICE_PKG_NAME_SIZE];
u8 active_pkg_in_nvm;
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 08/12] net/ice/base: add a helper to check for 100M speed support
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (6 preceding siblings ...)
2021-09-16 9:52 ` [dpdk-dev] [PATCH 07/12] net/ice/base: add package segment ID Qi Zhang
@ 2021-09-16 9:53 ` Qi Zhang
2021-09-16 9:53 ` [dpdk-dev] [PATCH 09/12] net/ice/base: add GCO defines and new GCO flex descriptor Qi Zhang
` (4 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:53 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Anirudh Venkataramanan
Add a helper function to check if the underlying part can
support 100M speeds.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 22 ++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index a7804219d8..107cebcb87 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -3011,6 +3011,28 @@ ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
+/**
+ * ice_is_100m_speed_supported
+ * @hw: pointer to the HW struct
+ *
+ * returns true if 100M speeds are supported by the device,
+ * false otherwise.
+ */
+bool ice_is_100m_speed_supported(struct ice_hw *hw)
+{
+ switch (hw->device_id) {
+ case ICE_DEV_ID_E822C_10G_BASE_T:
+ case ICE_DEV_ID_E822C_SGMII:
+ case ICE_DEV_ID_E822L_10G_BASE_T:
+ case ICE_DEV_ID_E822L_SGMII:
+ case ICE_DEV_ID_E823L_10G_BASE_T:
+ case ICE_DEV_ID_E823L_1GBE:
+ return true;
+ default:
+ return false;
+ }
+}
+
/**
* ice_get_link_speed_based_on_phy_type - returns link speed
* @phy_type_low: lower part of phy_type
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index e84308444d..a5bfdc072e 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -256,6 +256,7 @@ ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
enum ice_status
ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
bool *value, struct ice_sq_cd *cd);
+bool ice_is_100m_speed_supported(struct ice_hw *hw);
enum ice_status
ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
struct ice_sq_cd *cd);
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 09/12] net/ice/base: add GCO defines and new GCO flex descriptor
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (7 preceding siblings ...)
2021-09-16 9:53 ` [dpdk-dev] [PATCH 08/12] net/ice/base: add a helper to check for 100M speed support Qi Zhang
@ 2021-09-16 9:53 ` Qi Zhang
2021-09-16 9:53 ` [dpdk-dev] [PATCH 10/12] net/ice/base: add get/set functions for shared parameters Qi Zhang
` (3 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:53 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Alice Michael
Added the memory needed for the generic checksum offload (GCO)
feature, including the new flex descriptor ICE_RXDID_GSC.
Signed-off-by: Alice Michael <alice.michael@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 1 +
drivers/net/ice/base/ice_lan_tx_rx.h | 49 +++++++++++++++++++++++++++-
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 107cebcb87..46b0dd11b8 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1357,6 +1357,7 @@ const struct ice_ctx_ele ice_tlan_ctx_info[] = {
ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
+ ICE_CTX_STORE(ice_tlan_ctx, gsc_ena, 1, 172),
{ 0 }
};
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 4255e9963e..2b6f039dcb 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -522,6 +522,46 @@ struct ice_32b_rx_flex_desc_nic {
} flex_ts;
};
+/* Rx Flex Descriptor NIC Raw CSUM Profile
+ * RxDID Profile ID 9
+ * Flex-field 0: RSS hash lower 16-bits
+ * Flex-field 1: RSS hash upper 16-bits
+ * Flex-field 2: Flow ID lower 16-bits
+ * Flex-field 3: Raw CSUM
+ * Flex-field 4: reserved, VLAN ID taken from L2Tag
+ */
+struct ice_32b_rx_flex_desc_nic_raw_csum {
+ /* Qword 0 */
+ u8 rxdid;
+ u8 mir_id_umb_cast;
+ __le16 ptype_flexi_flags0;
+ __le16 pkt_len;
+ __le16 hdr_len_sph_flex_flags1;
+
+ /* Qword 1 */
+ __le16 status_error0;
+ __le16 l2tag1;
+ __le32 rss_hash;
+
+ /* Qword 2 */
+ __le16 status_error1; /* bit 6 Raw CSUM present */
+ u8 flexi_flags2;
+ u8 ts_low;
+ __le16 l2tag2_1st;
+ __le16 l2tag2_2nd;
+
+ /* Qword 3 */
+ __le16 flow_id;
+ __le16 raw_csum;
+ union {
+ struct {
+ __le16 rsvd;
+ __le16 flow_id_ipv6;
+ } flex;
+ __le32 ts_high;
+ } flex_ts;
+};
+
/* Rx Flex Descriptor Switch Profile
* RxDID Profile ID 3
* Flex-field 0: Source VSI
@@ -708,6 +748,7 @@ enum ice_rxdid {
ICE_RXDID_FLEX_NIC = 2,
ICE_RXDID_FLEX_NIC_2 = 6,
ICE_RXDID_HW = 7,
+ ICE_RXDID_GSC = 9,
ICE_RXDID_COMMS_GENERIC = 16,
ICE_RXDID_COMMS_AUX_VLAN = 17,
ICE_RXDID_COMMS_AUX_IPV4 = 18,
@@ -1029,10 +1070,15 @@ enum ice_tx_desc_len_fields {
struct ice_tx_ctx_desc {
__le32 tunneling_params;
__le16 l2tag2;
- __le16 rsvd;
+ __le16 gsc;
__le64 qw1;
};
+#define ICE_TX_GSC_DESC_START 0 /* 7 BITS */
+#define ICE_TX_GSC_DESC_OFFSET 7 /* 4 BITS */
+#define ICE_TX_GSC_DESC_TYPE 11 /* 2 BITS */
+#define ICE_TX_GSC_DESC_ENA 13 /* 1 BIT */
+
#define ICE_TXD_CTX_QW1_DTYPE_S 0
#define ICE_TXD_CTX_QW1_DTYPE_M (0xFUL << ICE_TXD_CTX_QW1_DTYPE_S)
@@ -1143,6 +1189,7 @@ struct ice_tlan_ctx {
u8 drop_ena;
u8 cache_prof_idx;
u8 pkt_shaper_prof_idx;
+ u8 gsc_ena;
u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */
};
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 10/12] net/ice/base: add get/set functions for shared parameters
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (8 preceding siblings ...)
2021-09-16 9:53 ` [dpdk-dev] [PATCH 09/12] net/ice/base: add GCO defines and new GCO flex descriptor Qi Zhang
@ 2021-09-16 9:53 ` Qi Zhang
2021-09-16 9:53 ` [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for SMA controller Qi Zhang
` (2 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:53 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Jacob Keller
Add functions used by the driver for setting and getting the shared
driver parameters. These will be used by the driver in order to share
the PTP clock index identifier between PF drivers.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 10 ++++
drivers/net/ice/base/ice_common.c | 75 +++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 6 +++
3 files changed, 91 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index e9d6fcc3ad..253b971dfd 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2713,6 +2713,16 @@ struct ice_aqc_driver_shared_params {
__le32 addr_low;
};
+enum ice_aqc_driver_params {
+ /* OS clock index for PTP timer Domain 0 */
+ ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0,
+ /* OS clock index for PTP timer Domain 1 */
+ ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1,
+
+ /* Add new parameters above */
+ ICE_AQC_DRIVER_PARAM_MAX = 16,
+};
+
/* Lan Queue Overflow Event (direct, 0x1001) */
struct ice_aqc_event_lan_overflow {
__le32 prtdcb_ruptq;
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 46b0dd11b8..ae55bebaa2 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -5494,6 +5494,81 @@ ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
+/**
+ * ice_aq_set_driver_param - Set driver parameter to share via firmware
+ * @hw: pointer to the HW struct
+ * @idx: parameter index to set
+ * @value: the value to set the parameter to
+ * @cd: pointer to command details structure or NULL
+ *
+ * Set the value of one of the software defined parameters. All PFs connected
+ * to this device can read the value using ice_aq_get_driver_param.
+ *
+ * Note that firmware provides no synchronization or locking, and will not
+ * save the parameter value during a device reset. It is expected that
+ * a single PF will write the parameter value, while all other PFs will only
+ * read it.
+ */
+enum ice_status
+ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
+ u32 value, struct ice_sq_cd *cd)
+{
+ struct ice_aqc_driver_shared_params *cmd;
+ struct ice_aq_desc desc;
+
+ if (idx >= ICE_AQC_DRIVER_PARAM_MAX)
+ return ICE_ERR_OUT_OF_RANGE;
+
+ cmd = &desc.params.drv_shared_params;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);
+
+ cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET;
+ cmd->param_indx = idx;
+ cmd->param_val = CPU_TO_LE32(value);
+
+ return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
+}
+
+/**
+ * ice_aq_get_driver_param - Get driver parameter shared via firmware
+ * @hw: pointer to the HW struct
+ * @idx: parameter index to set
+ * @value: storage to return the shared parameter
+ * @cd: pointer to command details structure or NULL
+ *
+ * Get the value of one of the software defined parameters.
+ *
+ * Note that firmware provides no synchronization or locking. It is expected
+ * that only a single PF will write a given parameter.
+ */
+enum ice_status
+ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
+ u32 *value, struct ice_sq_cd *cd)
+{
+ struct ice_aqc_driver_shared_params *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+
+ if (idx >= ICE_AQC_DRIVER_PARAM_MAX)
+ return ICE_ERR_OUT_OF_RANGE;
+
+ cmd = &desc.params.drv_shared_params;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);
+
+ cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET;
+ cmd->param_indx = idx;
+
+ status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
+ if (status)
+ return status;
+
+ *value = LE32_TO_CPU(cmd->param_val);
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_aq_set_gpio
* @hw: pointer to the hw struct
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index a5bfdc072e..1d8882c279 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -251,6 +251,12 @@ enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_txsched_elem_data *buf);
enum ice_status
+ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
+ u32 value, struct ice_sq_cd *cd);
+enum ice_status
+ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
+ u32 *value, struct ice_sq_cd *cd);
+enum ice_status
ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
struct ice_sq_cd *cd);
enum ice_status
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for SMA controller
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (9 preceding siblings ...)
2021-09-16 9:53 ` [dpdk-dev] [PATCH 10/12] net/ice/base: add get/set functions for shared parameters Qi Zhang
@ 2021-09-16 9:53 ` Qi Zhang
2021-09-22 12:43 ` Ferruh Yigit
2021-09-16 9:53 ` [dpdk-dev] [PATCH 12/12] net/ice/base: update auto generated hardware register Qi Zhang
2021-09-17 2:14 ` [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Guo, Junfeng
12 siblings, 1 reply; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:53 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Maciej Machnikowski
Add support for controlling SMA connectors using GPIO get/set AQs.
Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 213 ++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_ptp_hw.h | 11 ++
drivers/net/ice/base/ice_type.h | 1 +
3 files changed, 225 insertions(+)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 9ed335349b..7e797c9511 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -3077,6 +3077,219 @@ ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
return ICE_SUCCESS;
}
+/* E810T SMA functions
+ *
+ * The following functions operate specifically on E810T hardware and are used
+ * to access the extended GPIOs available.
+ */
+
+/**
+ * ice_get_pca9575_handle
+ * @hw: pointer to the hw struct
+ * @pca9575_handle: GPIO controller's handle
+ *
+ * Find and return the GPIO controller's handle in the netlist.
+ * When found - the value will be cached in the hw structure and following calls
+ * will return cached value
+ */
+static enum ice_status
+ice_get_pca9575_handle(struct ice_hw *hw, __le16 *pca9575_handle)
+{
+ struct ice_aqc_get_link_topo *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+ u8 idx;
+
+ if (!hw || !pca9575_handle)
+ return ICE_ERR_PARAM;
+
+ /* If handle was read previously return cached value */
+ if (hw->io_expander_handle) {
+ *pca9575_handle = hw->io_expander_handle;
+ return ICE_SUCCESS;
+ }
+
+ /* If handle was not detected read it from the netlist */
+ cmd = &desc.params.get_link_topo;
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
+
+ /* Set node type to GPIO controller */
+ cmd->addr.topo_params.node_type_ctx =
+ (ICE_AQC_LINK_TOPO_NODE_TYPE_M &
+ ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL);
+
+#define SW_PCA9575_SFP_TOPO_IDX 2
+#define SW_PCA9575_QSFP_TOPO_IDX 1
+
+ /* Check if the SW IO expander controlling SMA exists in the netlist. */
+ if (hw->device_id == ICE_DEV_ID_E810C_SFP)
+ idx = SW_PCA9575_SFP_TOPO_IDX;
+ else if (hw->device_id == ICE_DEV_ID_E810C_QSFP)
+ idx = SW_PCA9575_QSFP_TOPO_IDX;
+ else
+ return ICE_ERR_NOT_SUPPORTED;
+
+ cmd->addr.topo_params.index = idx;
+
+ status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
+ if (status)
+ return ICE_ERR_NOT_SUPPORTED;
+
+ /* Verify if we found the right IO expander type */
+ if (desc.params.get_link_topo.node_part_num !=
+ ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575)
+ return ICE_ERR_NOT_SUPPORTED;
+
+ /* If present save the handle and return it */
+ hw->io_expander_handle = desc.params.get_link_topo.addr.handle;
+ *pca9575_handle = hw->io_expander_handle;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_read_e810t_pca9575_reg
+ * @hw: pointer to the hw struct
+ * @offset: GPIO controller register offset
+ * @data: pointer to data to be read from the GPIO controller
+ *
+ * Read the register from the GPIO controller
+ */
+enum ice_status
+ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)
+{
+ struct ice_aqc_link_topo_addr link_topo;
+ enum ice_status status;
+ __le16 addr;
+
+ memset(&link_topo, 0, sizeof(link_topo));
+
+ status = ice_get_pca9575_handle(hw, &link_topo.handle);
+ if (status)
+ return status;
+
+ link_topo.topo_params.node_type_ctx =
+ (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
+ ICE_AQC_LINK_TOPO_NODE_CTX_S);
+
+ addr = CPU_TO_LE16((u16)offset);
+
+ return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);
+}
+
+/**
+ * ice_write_e810t_pca9575_reg
+ * @hw: pointer to the hw struct
+ * @offset: GPIO controller register offset
+ * @data: data to be written to the GPIO controller
+ *
+ * Write the data to the GPIO controller register
+ */
+enum ice_status
+ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data)
+{
+ struct ice_aqc_link_topo_addr link_topo;
+ enum ice_status status;
+ __le16 addr;
+
+ memset(&link_topo, 0, sizeof(link_topo));
+
+ status = ice_get_pca9575_handle(hw, &link_topo.handle);
+ if (status)
+ return status;
+
+ link_topo.topo_params.node_type_ctx =
+ (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
+ ICE_AQC_LINK_TOPO_NODE_CTX_S);
+
+ addr = CPU_TO_LE16((u16)offset);
+
+ return ice_aq_write_i2c(hw, link_topo, 0, addr, 1, &data, NULL);
+}
+
+/**
+ * ice_read_sma_ctrl_e810t
+ * @hw: pointer to the hw struct
+ * @data: pointer to data to be read from the GPIO controller
+ *
+ * Read the SMA controller state. Only bits 3-7 in data are valid.
+ */
+enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)
+{
+ enum ice_status status;
+ u16 handle;
+ u8 i;
+
+ status = ice_get_pca9575_handle(hw, &handle);
+ if (status)
+ return status;
+
+ *data = 0;
+
+ for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) {
+ bool pin;
+
+ status = ice_aq_get_gpio(hw, handle, i + ICE_E810T_P1_OFFSET,
+ &pin, NULL);
+ if (status)
+ break;
+ *data |= (u8)(!pin) << i;
+ }
+
+ return status;
+}
+
+/**
+ * ice_write_sma_ctrl_e810t
+ * @hw: pointer to the hw struct
+ * @data: data to be written to the GPIO controller
+ *
+ * Write the data to the SMA controller. Only bits 3-7 in data are valid.
+ */
+enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
+{
+ enum ice_status status;
+ u16 handle;
+ u8 i;
+
+ status = ice_get_pca9575_handle(hw, &handle);
+ if (status)
+ return status;
+
+ for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) {
+ bool pin;
+
+ pin = !(data & (1 << i));
+ status = ice_aq_set_gpio(hw, handle, i + ICE_E810T_P1_OFFSET,
+ pin, NULL);
+ if (status)
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * ice_e810t_is_pca9575_present
+ * @hw: pointer to the hw struct
+ *
+ * Check if the SW IO expander is present in the netlist
+ */
+bool ice_e810t_is_pca9575_present(struct ice_hw *hw)
+{
+ enum ice_status status;
+ __le16 handle = 0;
+
+ if (!ice_is_e810t(hw))
+ return false;
+
+ status = ice_get_pca9575_handle(hw, &handle);
+ if (!status && handle)
+ return true;
+
+ return false;
+}
+
/* Device agnostic functions
*
* The following functions implement shared behavior common to both E822 and
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index c804085095..ee3366e83c 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -222,6 +222,13 @@ enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port);
/* E810 family functions */
enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);
+enum ice_status
+ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
+enum ice_status
+ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data);
+enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
+enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
+bool ice_e810t_is_pca9575_present(struct ice_hw *hw);
#define PFTSYN_SEM_BYTES 4
@@ -470,4 +477,8 @@ enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);
#define ICE_E810T_P1_SMA2_DIR_EN BIT(6)
#define ICE_E810T_P1_SMA2_TX_EN BIT(7)
+#define ICE_E810T_SMA_MIN_BIT 3
+#define ICE_E810T_SMA_MAX_BIT 7
+#define ICE_E810T_P1_OFFSET 8
+
#endif /* _ICE_PTP_HW_H_ */
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index b2b3291fb7..72cda11a4f 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1261,6 +1261,7 @@ struct ice_hw {
struct LIST_HEAD_TYPE rss_list_head;
ice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX);
u8 dvm_ena;
+ __le16 io_expander_handle;
};
/* Statistics collected by each port, VSI, VEB, and S-channel */
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for SMA controller
2021-09-16 9:53 ` [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for SMA controller Qi Zhang
@ 2021-09-22 12:43 ` Ferruh Yigit
2021-09-22 12:56 ` Machnikowski, Maciej
0 siblings, 1 reply; 20+ messages in thread
From: Ferruh Yigit @ 2021-09-22 12:43 UTC (permalink / raw)
To: Qi Zhang, qiming.yang; +Cc: junfeng.guo, dev, Maciej Machnikowski
On 9/16/2021 10:53 AM, Qi Zhang wrote:
> Add support for controlling SMA connectors using GPIO get/set AQs.
>
> Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_ptp_hw.c | 213 ++++++++++++++++++++++++++++++
> drivers/net/ice/base/ice_ptp_hw.h | 11 ++
> drivers/net/ice/base/ice_type.h | 1 +
> 3 files changed, 225 insertions(+)
Hi Qi, Qiming, What 'SMA' stands for?
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for SMA controller
2021-09-22 12:43 ` Ferruh Yigit
@ 2021-09-22 12:56 ` Machnikowski, Maciej
2021-09-22 13:51 ` Ferruh Yigit
0 siblings, 1 reply; 20+ messages in thread
From: Machnikowski, Maciej @ 2021-09-22 12:56 UTC (permalink / raw)
To: Yigit, Ferruh, Zhang, Qi Z, Yang, Qiming; +Cc: Guo, Junfeng, dev
It's SubMiniature version A - type of external connector we use on our time-enhanced NICs.
> -----Original Message-----
> From: Yigit, Ferruh <ferruh.yigit@intel.com>
> Sent: Wednesday, September 22, 2021 2:44 PM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Yang, Qiming
> <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Machnikowski,
> Maciej <maciej.machnikowski@intel.com>
> Subject: Re: [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for
> SMA controller
>
> On 9/16/2021 10:53 AM, Qi Zhang wrote:
> > Add support for controlling SMA connectors using GPIO get/set AQs.
> >
> > Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
> > Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> > ---
> > drivers/net/ice/base/ice_ptp_hw.c | 213
> ++++++++++++++++++++++++++++++
> > drivers/net/ice/base/ice_ptp_hw.h | 11 ++
> > drivers/net/ice/base/ice_type.h | 1 +
> > 3 files changed, 225 insertions(+)
>
> Hi Qi, Qiming, What 'SMA' stands for?
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for SMA controller
2021-09-22 12:56 ` Machnikowski, Maciej
@ 2021-09-22 13:51 ` Ferruh Yigit
0 siblings, 0 replies; 20+ messages in thread
From: Ferruh Yigit @ 2021-09-22 13:51 UTC (permalink / raw)
To: Machnikowski, Maciej, Zhang, Qi Z, Yang, Qiming; +Cc: Guo, Junfeng, dev
On 9/22/2021 1:56 PM, Machnikowski, Maciej wrote:
> It's SubMiniature version A - type of external connector we use on our time-enhanced NICs.
>
Thanks, will use it in the commit log as "SMA (SubMiniature version A) ..."
>> -----Original Message-----
>> From: Yigit, Ferruh <ferruh.yigit@intel.com>
>> Sent: Wednesday, September 22, 2021 2:44 PM
>> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Yang, Qiming
>> <qiming.yang@intel.com>
>> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Machnikowski,
>> Maciej <maciej.machnikowski@intel.com>
>> Subject: Re: [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for
>> SMA controller
>>
>> On 9/16/2021 10:53 AM, Qi Zhang wrote:
>>> Add support for controlling SMA connectors using GPIO get/set AQs.
>>>
>>> Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
>>> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
>>> ---
>>> drivers/net/ice/base/ice_ptp_hw.c | 213
>> ++++++++++++++++++++++++++++++
>>> drivers/net/ice/base/ice_ptp_hw.h | 11 ++
>>> drivers/net/ice/base/ice_type.h | 1 +
>>> 3 files changed, 225 insertions(+)
>>
>> Hi Qi, Qiming, What 'SMA' stands for?
^ permalink raw reply [flat|nested] 20+ messages in thread
* [dpdk-dev] [PATCH 12/12] net/ice/base: update auto generated hardware register
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (10 preceding siblings ...)
2021-09-16 9:53 ` [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for SMA controller Qi Zhang
@ 2021-09-16 9:53 ` Qi Zhang
2021-09-17 2:14 ` [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Guo, Junfeng
12 siblings, 0 replies; 20+ messages in thread
From: Qi Zhang @ 2021-09-16 9:53 UTC (permalink / raw)
To: qiming.yang; +Cc: junfeng.guo, dev, Qi Zhang, Scott W Taylor
Update ice_hw_autogen.h.
Remove duplicated one in ice_nvm.h.
Replace ICE_NVM_ACCESS_GL_HIBA_MAX with GL_HIBA_MAX_INDEX.
Signed-off-by: Scott W Taylor <scott.w.taylor@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_hw_autogen.h | 148 ++++++++++++++------------
drivers/net/ice/base/ice_nvm.c | 4 +-
drivers/net/ice/base/ice_nvm.h | 13 ---
3 files changed, 81 insertions(+), 84 deletions(-)
diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h
index cbca4b0629..10b1116931 100644
--- a/drivers/net/ice/base/ice_hw_autogen.h
+++ b/drivers/net/ice/base/ice_hw_autogen.h
@@ -2,10 +2,20 @@
* Copyright(c) 2001-2021 Intel Corporation
*/
-/* Machine-generated file; do not edit */
+/* Machine generated file. Do not edit. */
+
#ifndef _ICE_HW_AUTOGEN_H_
#define _ICE_HW_AUTOGEN_H_
+#define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
+#define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
+#define GL_HICR 0x00082040
+#define GL_HICR_EN 0x00082044
+#define GLGEN_CSR_DEBUG_C 0x00075750
+#define GLNVM_GENS 0x000B6100
+#define GLNVM_FLA 0x000B6108
+#define GL_HIDA_MAX_INDEX 15
+#define GL_HIBA_MAX_INDEX 1023
#define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */
#define GL_RDPU_CNTRL_RX_PAD_EN_S 0
#define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)
@@ -448,8 +458,8 @@
#define PF0INT_OICR_CPM_PAGE_RSV3_M BIT(23)
#define PF0INT_OICR_CPM_PAGE_STORM_DETECT_S 24
#define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M BIT(24)
-#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25
-#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)
+#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25
+#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)
#define PF0INT_OICR_CPM_PAGE_HMC_ERR_S 26
#define PF0INT_OICR_CPM_PAGE_HMC_ERR_M BIT(26)
#define PF0INT_OICR_CPM_PAGE_PE_PUSH_S 27
@@ -512,8 +522,8 @@
#define PF0INT_OICR_HLP_PAGE_RSV3_M BIT(23)
#define PF0INT_OICR_HLP_PAGE_STORM_DETECT_S 24
#define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M BIT(24)
-#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25
-#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)
+#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25
+#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)
#define PF0INT_OICR_HLP_PAGE_HMC_ERR_S 26
#define PF0INT_OICR_HLP_PAGE_HMC_ERR_M BIT(26)
#define PF0INT_OICR_HLP_PAGE_PE_PUSH_S 27
@@ -561,8 +571,8 @@
#define PF0INT_OICR_PSM_PAGE_RSV3_M BIT(23)
#define PF0INT_OICR_PSM_PAGE_STORM_DETECT_S 24
#define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M BIT(24)
-#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25
-#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)
+#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25
+#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)
#define PF0INT_OICR_PSM_PAGE_HMC_ERR_S 26
#define PF0INT_OICR_PSM_PAGE_HMC_ERR_M BIT(26)
#define PF0INT_OICR_PSM_PAGE_PE_PUSH_S 27
@@ -702,8 +712,8 @@
#define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M MAKEMASK(0x1F, 8)
#define GL_ACL_PROFILE_DWSB_SEL(_i) (0x00391088 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
#define GL_ACL_PROFILE_DWSB_SEL_MAX_INDEX 15
-#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0
-#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)
+#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0
+#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)
#define GL_ACL_PROFILE_PF_CFG(_i) (0x003910C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
#define GL_ACL_PROFILE_PF_CFG_MAX_INDEX 7
#define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S 0
@@ -861,8 +871,8 @@
#define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M BIT(6)
#define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_S 7
#define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7)
-#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14
-#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)
+#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14
+#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)
#define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_S 22
#define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M MAKEMASK(0x3FF, 22)
#define GLTCLAN_CQ_CNTX0(_CQ) (0x000F0800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
@@ -2205,8 +2215,8 @@
#define PRTDCB_TX_DSCP2UP_CTL 0x00040980 /* Reset Source: CORER */
#define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S 0
#define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M BIT(0)
-#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1
-#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)
+#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1
+#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)
#define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i) (0x000409A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */
#define PRTDCB_TX_DSCP2UP_IPV4_LUT_MAX_INDEX 7
#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0
@@ -2354,8 +2364,8 @@
#define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0
#define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
#define TPB_PRTTCB_LL_DWRR_WB_CREDITS 0x00099320 /* Reset Source: CORER */
-#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
-#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
+#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
+#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
#define TPB_WB_RL_TC_CFG(_i) (0x00099360 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define TPB_WB_RL_TC_CFG_MAX_INDEX 31
#define TPB_WB_RL_TC_CFG_TOKENS_S 0
@@ -2420,8 +2430,8 @@
#define GL_ACLEXT_FORCE_L1CDID_MAX_INDEX 2
#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S 0
#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
#define GL_ACLEXT_FORCE_PID(_i) (0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_ACLEXT_FORCE_PID_MAX_INDEX 2
#define GL_ACLEXT_FORCE_PID_STATIC_PID_S 0
@@ -2614,8 +2624,8 @@
#define GL_PREEXT_FORCE_L1CDID_MAX_INDEX 2
#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S 0
#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
-#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
-#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
#define GL_PREEXT_FORCE_PID(_i) (0x0020F000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PREEXT_FORCE_PID_MAX_INDEX 2
#define GL_PREEXT_FORCE_PID_STATIC_PID_S 0
@@ -2816,8 +2826,8 @@
#define GL_PSTEXT_FORCE_L1CDID_MAX_INDEX 2
#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S 0
#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
-#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
-#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
#define GL_PSTEXT_FORCE_PID(_i) (0x0020E000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PSTEXT_FORCE_PID_MAX_INDEX 2
#define GL_PSTEXT_FORCE_PID_STATIC_PID_S 0
@@ -2984,10 +2994,10 @@
#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4)
#define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_S 8
#define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8)
-#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12
-#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)
-#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14
-#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)
+#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12
+#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)
+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14
+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)
#define GLFLXP_RX_CMD_PROTIDS(_i, _j) (0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 */ /* Reset Source: CORER */
#define GLFLXP_RX_CMD_PROTIDS_MAX_INDEX 255
#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S 0
@@ -3066,8 +3076,8 @@
#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M MAKEMASK(0xFF, 0)
#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_S 8
#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M MAKEMASK(0x1F, 8)
-#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16
-#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)
+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16
+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)
#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_S 24
#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M MAKEMASK(0x1F, 24)
#define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
@@ -3280,18 +3290,18 @@
#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9
#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
-#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14
-#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
+#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14
+#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
#define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_S 16
#define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16)
-#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
-#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
+#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
+#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
#define GLGEN_ANA_TX_ABORT_PTYPE 0x0020D21C /* Reset Source: CORER */
#define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S 0
#define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0)
#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT 0x0020D208 /* Reset Source: CORER */
-#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
-#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
+#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
+#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
#define GLGEN_ANA_TX_CFG_CTRL 0x0020D104 /* Reset Source: CORER */
#define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S 0
#define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0)
@@ -3317,10 +3327,10 @@
#define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S 0
#define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT 0x0020D15C /* Reset Source: CORER */
-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0
-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1
-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_S 4
#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
#define GLGEN_ANA_TX_CFG_WRDATA 0x0020D108 /* Reset Source: CORER */
@@ -3639,8 +3649,8 @@
#define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S 0
#define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
#define GLHMC_FWSDDATAHIGH_FPMAT 0x00102078 /* Reset Source: CORER */
-#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
-#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
+#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
#define GLHMC_FWSDDATALOW 0x00522074 /* Reset Source: CORER */
#define GLHMC_FWSDDATALOW_PMSDVALID_S 0
#define GLHMC_FWSDDATALOW_PMSDVALID_M BIT(0)
@@ -4038,8 +4048,8 @@
#define GLHMC_VFPEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0)
#define GLHMC_VFPEOOISCBASE(_i) (0x0052E600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define GLHMC_VFPEOOISCBASE_MAX_INDEX 31
-#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0
-#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0
+#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
#define GLHMC_VFPEOOISCCNT(_i) (0x0052E700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define GLHMC_VFPEOOISCCNT_MAX_INDEX 31
#define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S 0
@@ -4086,8 +4096,8 @@
#define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0)
#define GLHMC_VFPERRFFLBASE(_i) (0x0052EA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define GLHMC_VFPERRFFLBASE_MAX_INDEX 31
-#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0
-#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0
+#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
#define GLHMC_VFPETIMERBASE(_i) (0x0052DA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define GLHMC_VFPETIMERBASE_MAX_INDEX 31
#define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S 0
@@ -4114,8 +4124,8 @@
#define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
#define GLHMC_VFSDDATAHIGH_FPMAT(_i) (0x00108200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define GLHMC_VFSDDATAHIGH_FPMAT_MAX_INDEX 31
-#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
-#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
+#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
#define GLHMC_VFSDDATALOW(_i) (0x00528100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define GLHMC_VFSDDATALOW_MAX_INDEX 31
#define GLHMC_VFSDDATALOW_PMSDVALID_S 0
@@ -4221,8 +4231,8 @@
#define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M BIT(7)
#define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_S 8
#define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8)
-#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16
-#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
+#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16
+#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
#define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_S 31
#define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M BIT(31)
#define PFHMC_PDINV 0x00520300 /* Reset Source: PFR */
@@ -4309,8 +4319,8 @@
#define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11)
#define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_S 12
#define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12)
-#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13
-#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)
+#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13
+#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)
#define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_S 14
#define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14)
#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_S 15
@@ -5205,10 +5215,10 @@
#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E36C0 /* Reset Source: GLOBR */
#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0
#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */
+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */
#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0
#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */
+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */
#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0
#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)
#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E3180 /* Reset Source: GLOBR */
@@ -5309,10 +5319,10 @@
#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M BIT(17)
#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_S 18
#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M BIT(18)
-#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19
-#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)
-#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20
-#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)
+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19
+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)
+#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20
+#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)
#define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_S 21
#define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M BIT(21)
#define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_S 22
@@ -5331,8 +5341,8 @@
#define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */
#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0
#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
-#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
-#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2
#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)
#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3
@@ -5345,8 +5355,8 @@
#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7
#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)
-#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
-#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10
@@ -5428,8 +5438,8 @@
#define VP_MDET_TX_TDPU_VALID_M BIT(0)
#define GENERAL_MNG_FW_DBG_CSR(_i) (0x000B6180 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: POR */
#define GENERAL_MNG_FW_DBG_CSR_MAX_INDEX 9
-#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0
-#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)
+#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0
+#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)
#define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */
#define GL_FWRESETCNT_FWRESETCNT_S 0
#define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0)
@@ -5841,8 +5851,8 @@
#define GL_XLR_MARKER_TRIG_RCU_PRS 0x002001C0 /* Reset Source: CORER */
#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S 0
#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
-#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10
-#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)
+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10
+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)
#define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_S 12
#define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M MAKEMASK(0x7, 12)
#define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_S 16
@@ -6721,11 +6731,11 @@
#define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S 0
#define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M MAKEMASK(0xFFFFFFFF, 0)
#define GLPES_TCPRXFOURHOLEHI 0x0055E03C /* Reset Source: CORER */
-#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0
-#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)
+#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0
+#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)
#define GLPES_TCPRXFOURHOLELO 0x0055E038 /* Reset Source: CORER */
-#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0
-#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0
+#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
#define GLPES_TCPRXONEHOLEHI 0x0055E024 /* Reset Source: CORER */
#define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S 0
#define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M MAKEMASK(0xFFFFFF, 0)
@@ -8206,7 +8216,7 @@
#define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S 0
#define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M MAKEMASK(0xFFFFFFFF, 0)
#define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i) (0x00099094 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
-#define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63
+#define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63
#define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S 0
#define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)
#define EMP_SWT_PRUNIND 0x00204020 /* Reset Source: CORER */
@@ -9448,5 +9458,5 @@
#define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0)
#define VFPE_WQEALLOC1_WQE_DESC_INDEX_S 20
#define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
+#endif /* !_ICE_HW_AUTOGEN_H_ */
-#endif
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 2b76a11e22..7860006206 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -1214,11 +1214,11 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
break;
}
- for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
+ for (i = 0; i <= GL_HIDA_MAX_INDEX; i++)
if (offset == (u32)GL_HIDA(i))
return ICE_SUCCESS;
- for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
+ for (i = 0; i <= GL_HIBA_MAX_INDEX; i++)
if (offset == (u32)GL_HIBA(i))
return ICE_SUCCESS;
diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h
index af18344cf8..52e8853b19 100644
--- a/drivers/net/ice/base/ice_nvm.h
+++ b/drivers/net/ice/base/ice_nvm.h
@@ -67,19 +67,6 @@ union ice_nvm_access_data {
struct ice_nvm_features drv_features; /* NVM features */
};
-/* NVM Access registers */
-#define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
-#define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
-#define GL_HICR 0x00082040
-#define GL_HICR_EN 0x00082044
-#define GLGEN_CSR_DEBUG_C 0x00075750
-#define GLPCI_LBARCTRL 0x0009DE74
-#define GLNVM_GENS 0x000B6100
-#define GLNVM_FLA 0x000B6108
-
-#define ICE_NVM_ACCESS_GL_HIDA_MAX 15
-#define ICE_NVM_ACCESS_GL_HIBA_MAX 1023
-
u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd);
u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd);
u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd);
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
` (11 preceding siblings ...)
2021-09-16 9:53 ` [dpdk-dev] [PATCH 12/12] net/ice/base: update auto generated hardware register Qi Zhang
@ 2021-09-17 2:14 ` Guo, Junfeng
2021-09-17 8:48 ` Zhang, Qi Z
12 siblings, 1 reply; 20+ messages in thread
From: Guo, Junfeng @ 2021-09-17 2:14 UTC (permalink / raw)
To: Zhang, Qi Z, Yang, Qiming; +Cc: dev
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Thursday, September 16, 2021 17:53
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [PATCH 00/12] ice base code batch 2 for DPDK 21.11
>
> Qi Zhang (12):
> net/ice/base: calculate logical PF ID
> net/ice/base: include more E810T adapters
> net/ice/base: use macro instead of open-coded division
> net/ice/base: allow to enable LAN and loopback in switch
> net/ice/base: change addr param to u16
> net/ice/base: allow tool access to MNG register
> net/ice/base: add package segment ID
> net/ice/base: add a helper to check for 100M speed support
> net/ice/base: add GCO defines and new GCO flex descriptor
> net/ice/base: add get/set functions for shared parameters
> net/ice/base: implement support for SMA controller
> net/ice/base: update auto generated hardware register
>
> drivers/net/ice/base/ice_adminq_cmd.h | 10 +
> drivers/net/ice/base/ice_common.c | 134 ++++++++++++-
> drivers/net/ice/base/ice_common.h | 7 +
> drivers/net/ice/base/ice_devids.h | 1 +
> drivers/net/ice/base/ice_flex_pipe.c | 11 +-
> drivers/net/ice/base/ice_flex_type.h | 2 +-
> drivers/net/ice/base/ice_hw_autogen.h | 148 +++++++-------
> drivers/net/ice/base/ice_lan_tx_rx.h | 49 ++++-
> drivers/net/ice/base/ice_nvm.c | 7 +-
> drivers/net/ice/base/ice_nvm.h | 13 --
> drivers/net/ice/base/ice_ptp_hw.c | 270 +++++++++++++++++++++++--
> -
> drivers/net/ice/base/ice_ptp_hw.h | 11 ++
> drivers/net/ice/base/ice_switch.c | 7 +-
> drivers/net/ice/base/ice_switch.h | 11 ++
> drivers/net/ice/base/ice_type.h | 3 +
> 15 files changed, 569 insertions(+), 115 deletions(-)
>
> --
> 2.26.2
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Regards,
Junfeng Guo
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11
2021-09-17 2:14 ` [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Guo, Junfeng
@ 2021-09-17 8:48 ` Zhang, Qi Z
2021-09-22 12:45 ` Ferruh Yigit
0 siblings, 1 reply; 20+ messages in thread
From: Zhang, Qi Z @ 2021-09-17 8:48 UTC (permalink / raw)
To: Guo, Junfeng, Yang, Qiming; +Cc: dev
> -----Original Message-----
> From: Guo, Junfeng <junfeng.guo@intel.com>
> Sent: Friday, September 17, 2021 10:14 AM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Yang, Qiming
> <qiming.yang@intel.com>
> Cc: dev@dpdk.org
> Subject: RE: [PATCH 00/12] ice base code batch 2 for DPDK 21.11
>
>
>
> > -----Original Message-----
> > From: Zhang, Qi Z <qi.z.zhang@intel.com>
> > Sent: Thursday, September 16, 2021 17:53
> > To: Yang, Qiming <qiming.yang@intel.com>
> > Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> > <qi.z.zhang@intel.com>
> > Subject: [PATCH 00/12] ice base code batch 2 for DPDK 21.11
> >
> > Qi Zhang (12):
> > net/ice/base: calculate logical PF ID
> > net/ice/base: include more E810T adapters
> > net/ice/base: use macro instead of open-coded division
> > net/ice/base: allow to enable LAN and loopback in switch
> > net/ice/base: change addr param to u16
> > net/ice/base: allow tool access to MNG register
> > net/ice/base: add package segment ID
> > net/ice/base: add a helper to check for 100M speed support
> > net/ice/base: add GCO defines and new GCO flex descriptor
> > net/ice/base: add get/set functions for shared parameters
> > net/ice/base: implement support for SMA controller
> > net/ice/base: update auto generated hardware register
> >
> > drivers/net/ice/base/ice_adminq_cmd.h | 10 +
> > drivers/net/ice/base/ice_common.c | 134 ++++++++++++-
> > drivers/net/ice/base/ice_common.h | 7 +
> > drivers/net/ice/base/ice_devids.h | 1 +
> > drivers/net/ice/base/ice_flex_pipe.c | 11 +-
> > drivers/net/ice/base/ice_flex_type.h | 2 +-
> > drivers/net/ice/base/ice_hw_autogen.h | 148 +++++++-------
> > drivers/net/ice/base/ice_lan_tx_rx.h | 49 ++++-
> > drivers/net/ice/base/ice_nvm.c | 7 +-
> > drivers/net/ice/base/ice_nvm.h | 13 --
> > drivers/net/ice/base/ice_ptp_hw.c | 270 +++++++++++++++++++++++--
> > -
> > drivers/net/ice/base/ice_ptp_hw.h | 11 ++
> > drivers/net/ice/base/ice_switch.c | 7 +-
> > drivers/net/ice/base/ice_switch.h | 11 ++
> > drivers/net/ice/base/ice_type.h | 3 +
> > 15 files changed, 569 insertions(+), 115 deletions(-)
> >
> > --
> > 2.26.2
>
> Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Applied to dpdk-next-net-intel.
Thanks
Qi
>
> Regards,
> Junfeng Guo
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11
2021-09-17 8:48 ` Zhang, Qi Z
@ 2021-09-22 12:45 ` Ferruh Yigit
2021-09-23 0:21 ` Zhang, Qi Z
0 siblings, 1 reply; 20+ messages in thread
From: Ferruh Yigit @ 2021-09-22 12:45 UTC (permalink / raw)
To: Zhang, Qi Z, Guo, Junfeng, Yang, Qiming; +Cc: dev
On 9/17/2021 9:48 AM, Zhang, Qi Z wrote:
>
>
>> -----Original Message-----
>> From: Guo, Junfeng <junfeng.guo@intel.com>
>> Sent: Friday, September 17, 2021 10:14 AM
>> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Yang, Qiming
>> <qiming.yang@intel.com>
>> Cc: dev@dpdk.org
>> Subject: RE: [PATCH 00/12] ice base code batch 2 for DPDK 21.11
>>
>>
>>
>>> -----Original Message-----
>>> From: Zhang, Qi Z <qi.z.zhang@intel.com>
>>> Sent: Thursday, September 16, 2021 17:53
>>> To: Yang, Qiming <qiming.yang@intel.com>
>>> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
>>> <qi.z.zhang@intel.com>
>>> Subject: [PATCH 00/12] ice base code batch 2 for DPDK 21.11
>>>
>>> Qi Zhang (12):
>>> net/ice/base: calculate logical PF ID
>>> net/ice/base: include more E810T adapters
>>> net/ice/base: use macro instead of open-coded division
>>> net/ice/base: allow to enable LAN and loopback in switch
>>> net/ice/base: change addr param to u16
>>> net/ice/base: allow tool access to MNG register
>>> net/ice/base: add package segment ID
>>> net/ice/base: add a helper to check for 100M speed support
>>> net/ice/base: add GCO defines and new GCO flex descriptor
>>> net/ice/base: add get/set functions for shared parameters
>>> net/ice/base: implement support for SMA controller
>>> net/ice/base: update auto generated hardware register
>>>
>>> drivers/net/ice/base/ice_adminq_cmd.h | 10 +
>>> drivers/net/ice/base/ice_common.c | 134 ++++++++++++-
>>> drivers/net/ice/base/ice_common.h | 7 +
>>> drivers/net/ice/base/ice_devids.h | 1 +
>>> drivers/net/ice/base/ice_flex_pipe.c | 11 +-
>>> drivers/net/ice/base/ice_flex_type.h | 2 +-
>>> drivers/net/ice/base/ice_hw_autogen.h | 148 +++++++-------
>>> drivers/net/ice/base/ice_lan_tx_rx.h | 49 ++++-
>>> drivers/net/ice/base/ice_nvm.c | 7 +-
>>> drivers/net/ice/base/ice_nvm.h | 13 --
>>> drivers/net/ice/base/ice_ptp_hw.c | 270 +++++++++++++++++++++++--
>>> -
>>> drivers/net/ice/base/ice_ptp_hw.h | 11 ++
>>> drivers/net/ice/base/ice_switch.c | 7 +-
>>> drivers/net/ice/base/ice_switch.h | 11 ++
>>> drivers/net/ice/base/ice_type.h | 3 +
>>> 15 files changed, 569 insertions(+), 115 deletions(-)
>>>
>>> --
>>> 2.26.2
>>
>> Acked-by: Junfeng Guo <junfeng.guo@intel.com>
>
> Applied to dpdk-next-net-intel.
>
Hi Qi, Junfeng, Qiming,
Won't the version information in the 'drivers/net/ice/base/README' updated with
these changes?
Thanks,
ferruh
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11
2021-09-22 12:45 ` Ferruh Yigit
@ 2021-09-23 0:21 ` Zhang, Qi Z
0 siblings, 0 replies; 20+ messages in thread
From: Zhang, Qi Z @ 2021-09-23 0:21 UTC (permalink / raw)
To: Yigit, Ferruh, Guo, Junfeng, Yang, Qiming; +Cc: dev
> -----Original Message-----
> From: Yigit, Ferruh <ferruh.yigit@intel.com>
> Sent: Wednesday, September 22, 2021 8:45 PM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Guo, Junfeng
> <junfeng.guo@intel.com>; Yang, Qiming <qiming.yang@intel.com>
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11
>
> On 9/17/2021 9:48 AM, Zhang, Qi Z wrote:
> >
> >
> >> -----Original Message-----
> >> From: Guo, Junfeng <junfeng.guo@intel.com>
> >> Sent: Friday, September 17, 2021 10:14 AM
> >> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Yang, Qiming
> >> <qiming.yang@intel.com>
> >> Cc: dev@dpdk.org
> >> Subject: RE: [PATCH 00/12] ice base code batch 2 for DPDK 21.11
> >>
> >>
> >>
> >>> -----Original Message-----
> >>> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> >>> Sent: Thursday, September 16, 2021 17:53
> >>> To: Yang, Qiming <qiming.yang@intel.com>
> >>> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> >>> <qi.z.zhang@intel.com>
> >>> Subject: [PATCH 00/12] ice base code batch 2 for DPDK 21.11
> >>>
> >>> Qi Zhang (12):
> >>> net/ice/base: calculate logical PF ID
> >>> net/ice/base: include more E810T adapters
> >>> net/ice/base: use macro instead of open-coded division
> >>> net/ice/base: allow to enable LAN and loopback in switch
> >>> net/ice/base: change addr param to u16
> >>> net/ice/base: allow tool access to MNG register
> >>> net/ice/base: add package segment ID
> >>> net/ice/base: add a helper to check for 100M speed support
> >>> net/ice/base: add GCO defines and new GCO flex descriptor
> >>> net/ice/base: add get/set functions for shared parameters
> >>> net/ice/base: implement support for SMA controller
> >>> net/ice/base: update auto generated hardware register
> >>>
> >>> drivers/net/ice/base/ice_adminq_cmd.h | 10 +
> >>> drivers/net/ice/base/ice_common.c | 134 ++++++++++++-
> >>> drivers/net/ice/base/ice_common.h | 7 +
> >>> drivers/net/ice/base/ice_devids.h | 1 +
> >>> drivers/net/ice/base/ice_flex_pipe.c | 11 +-
> >>> drivers/net/ice/base/ice_flex_type.h | 2 +-
> >>> drivers/net/ice/base/ice_hw_autogen.h | 148 +++++++-------
> >>> drivers/net/ice/base/ice_lan_tx_rx.h | 49 ++++-
> >>> drivers/net/ice/base/ice_nvm.c | 7 +-
> >>> drivers/net/ice/base/ice_nvm.h | 13 --
> >>> drivers/net/ice/base/ice_ptp_hw.c | 270
> +++++++++++++++++++++++--
> >>> -
> >>> drivers/net/ice/base/ice_ptp_hw.h | 11 ++
> >>> drivers/net/ice/base/ice_switch.c | 7 +-
> >>> drivers/net/ice/base/ice_switch.h | 11 ++
> >>> drivers/net/ice/base/ice_type.h | 3 +
> >>> 15 files changed, 569 insertions(+), 115 deletions(-)
> >>>
> >>> --
> >>> 2.26.2
> >>
> >> Acked-by: Junfeng Guo <junfeng.guo@intel.com>
> >
> > Applied to dpdk-next-net-intel.
> >
>
> Hi Qi, Junfeng, Qiming,
>
> Won't the version information in the 'drivers/net/ice/base/README' updated
> with these changes?
There will be more base code update for DPDK 21.11, we will update it in following patches.
Thanks
Qi
>
> Thanks,
> ferruh
^ permalink raw reply [flat|nested] 20+ messages in thread