From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56AA1A0C41; Thu, 16 Sep 2021 12:40:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 31D6640151; Thu, 16 Sep 2021 12:40:27 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 2DBE44003F for ; Thu, 16 Sep 2021 12:40:26 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18FNsWQn009366 for ; Thu, 16 Sep 2021 03:40:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=mavYtPRkv9gyBSCt00MJoFQwb3VWfkGLb/BtDvsADcE=; b=TGpcRnQlKaoOlVdZb2dXs2m3Xpdkx87VkvbMBno4Pfq9R2+uargE/0MSoZYHrMtT7MN2 68n4cV/Yz7T9WfDzvFXZHcgGyT7pnrsCTMUh4ho4jdJmxVETQ/7fQwBaPFX+/1imosPB d0HWTAMxyzk4IDOlcQFCwYNxnIMxf91h185w4XvWt8oN5sPUHg4qjm/vQTWnZKFNBtPn t8aDShktZDVxXAUnPZ5Fm8FMBp6VI/3q4Pwl6+FQi3rZSXmlAsoyTpOv77/DsR0VYvwj p0mx8YoRLHphoVlDTshsmxxbVQKcwXiLGRkiIEfK6tgc8075MzUCRVW0A11lfG9Z454z 9Q== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3b3twmsxbd-10 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Sep 2021 03:40:25 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 16 Sep 2021 03:40:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 16 Sep 2021 03:40:21 -0700 Received: from hyd1554T5810.caveonetworks.com.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 07E925B6941; Thu, 16 Sep 2021 03:40:19 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Tejasree Kondoj , Anoob Joseph , Jerin Jacob , Date: Thu, 16 Sep 2021 17:04:19 +0530 Message-ID: <20210916113419.16734-1-ktejasree@marvell.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: ZkdAOhCpSCzne4CGKSgL9R96EDcnJ88u X-Proofpoint-ORIG-GUID: ZkdAOhCpSCzne4CGKSgL9R96EDcnJ88u X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-16_03,2021-09-16_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH] common/cnxk: support 98XX CPT dual block X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" CN98xx SoC comes up with two CPT blocks wrt CN96xx, CN93xx, to achieve higher performance. Adding support to allocate all LFs of VF with even BDF from CPT0 and all LFs of VF with odd BDF from CPT1. If LFs are not available in one block then they will be allocated from alternate block. Signed-off-by: Tejasree Kondoj --- doc/guides/rel_notes/release_21_11.rst | 1 + drivers/common/cnxk/roc_cpt.c | 36 ++++++++++++++++++++------ drivers/common/cnxk/roc_cpt.h | 10 +++++++ 3 files changed, 39 insertions(+), 8 deletions(-) diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 43d367bcad..1aae9fce7b 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -68,6 +68,7 @@ New Features * Added Transport mode support in lookaside protocol (IPsec) for CN10K. * Added UDP encapsulation support in lookaside protocol (IPsec) for CN10K. * Added support for lookaside protocol (IPsec) offload for CN9K. + * Added CN98xx dual block support. * **Added support for event crypto adapter on Marvell CN10K and CN9K.** diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 33524ef504..db201b1396 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -367,7 +367,7 @@ cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf) if (rc) return -EIO; - *nb_lf = rsp->cpt; + *nb_lf = PLT_MAX((uint16_t)rsp->cpt, (uint16_t)rsp->cpt1); return 0; } @@ -401,7 +401,7 @@ cpt_lfs_free(struct dev *dev) } static int -cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps) +cpt_hardware_caps_get(struct dev *dev, struct roc_cpt *roc_cpt) { struct cpt_caps_rsp_msg *rsp; int ret; @@ -412,7 +412,8 @@ cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps) if (ret) return -EIO; - mbox_memcpy(hw_caps, rsp->eng_caps, + roc_cpt->cpt_revision = rsp->cpt_revision; + mbox_memcpy(roc_cpt->hw_caps, rsp->eng_caps, sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES); return 0; @@ -472,21 +473,40 @@ int roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf) { struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); - uint8_t blkaddr = RVU_BLOCK_ADDR_CPT0; + uint8_t blkaddr[ROC_CPT_MAX_BLKS]; struct msix_offset_rsp *rsp; uint8_t eng_grpmsk; + int blknum = 0; int rc, i; + blkaddr[0] = RVU_BLOCK_ADDR_CPT0; + blkaddr[1] = RVU_BLOCK_ADDR_CPT1; + + if ((roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_98XX) && + (cpt->dev.pf_func & 0x1)) + blknum = (blknum + 1) % ROC_CPT_MAX_BLKS; + /* Request LF resources */ - rc = cpt_lfs_attach(&cpt->dev, blkaddr, true, nb_lf); - if (rc) + rc = cpt_lfs_attach(&cpt->dev, blkaddr[blknum], true, nb_lf); + + /* Request LFs from another block if current block has less LFs */ + if (roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_98XX && rc == ENOSPC) { + blknum = (blknum + 1) % ROC_CPT_MAX_BLKS; + rc = cpt_lfs_attach(&cpt->dev, blkaddr[blknum], true, nb_lf); + } + if (rc) { + plt_err("Could not attach LFs"); return rc; + } + + for (i = 0; i < nb_lf; i++) + cpt->lf_blkaddr[i] = blkaddr[blknum]; eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) | (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) | (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]); - rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr, false); + rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false); if (rc) goto lfs_detach; @@ -617,7 +637,7 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt) cpt->pci_dev = pci_dev; roc_cpt->lmt_base = dev->lmt_base; - rc = cpt_hardware_caps_get(dev, roc_cpt->hw_caps); + rc = cpt_hardware_caps_get(dev, roc_cpt); if (rc) { plt_err("Could not determine hardware capabilities"); goto fail; diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 9e63073a52..38fcd4d399 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -16,6 +16,7 @@ #define ROC_CPT_DFLT_ENG_GRP_AE 2UL #define ROC_CPT_MAX_LFS 64 +#define ROC_CPT_MAX_BLKS 2 #define ROC_CN10K_CPT_INST_DW_M1 \ ((uint64_t)(((sizeof(struct cpt_inst_s) / 16) - 1) & 0x7)) #define ROC_CN10K_TWO_CPT_INST_DW_M1 \ @@ -76,6 +77,14 @@ #define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20 #define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40 +enum { + ROC_CPT_REVISION_ID_83XX = 0, + ROC_CPT_REVISION_ID_96XX_B0 = 1, + ROC_CPT_REVISION_ID_96XX_C0 = 2, + ROC_CPT_REVISION_ID_98XX = 3, + ROC_CPT_REVISION_ID_106XX = 4, +}; + struct roc_cpt_lmtline { uint64_t io_addr; uint64_t *fc_addr; @@ -111,6 +120,7 @@ struct roc_cpt { /**< CPT device capabilities */ union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES]; uint8_t eng_grp[CPT_MAX_ENG_TYPES]; + uint8_t cpt_revision; #define ROC_CPT_MEM_SZ (6 * 1024) uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned; -- 2.27.0