From: Ashwin Sekhar T K <asekhar@marvell.com>
To: <dev@dpdk.org>
Cc: <jerinj@marvell.com>, <skori@marvell.com>,
<skoteshwar@marvell.com>, <pbhagavatula@marvell.com>,
<kirankumark@marvell.com>, <psatheesh@marvell.com>,
<asekhar@marvell.com>, <anoobj@marvell.com>, <gakhil@marvell.com>
Subject: [dpdk-dev] [PATCH v2 1/2] common/cnxk: update roc models
Date: Fri, 17 Sep 2021 15:04:36 +0530 [thread overview]
Message-ID: <20210917093437.269363-1-asekhar@marvell.com> (raw)
In-Reply-To: <20210830162903.2736191-1-asekhar@marvell.com>
Make following updates to roc models.
- Use consistent upper/lower case in macros defining different
ROC models.
- Add api to detect cn96 Cx stepping.
- Make all current cn10k models as A0 stepping.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
drivers/common/cnxk/roc_model.c | 51 +++++++++++++++----------------
drivers/common/cnxk/roc_model.h | 53 +++++++++++++++++++++++++--------
2 files changed, 67 insertions(+), 37 deletions(-)
diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index bc255b53cc..e5aeabe2e2 100644
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -13,14 +13,14 @@ struct roc_model *roc_model;
#define SOC_PART_CN10K 0xD49
-#define PART_106XX 0xB9
-#define PART_105XX 0xBA
-#define PART_105XXN 0xBC
-#define PART_98XX 0xB1
-#define PART_96XX 0xB2
-#define PART_95XX 0xB3
-#define PART_95XXN 0xB4
-#define PART_95XXMM 0xB5
+#define PART_106xx 0xB9
+#define PART_105xx 0xBA
+#define PART_105xxN 0xBC
+#define PART_98xx 0xB1
+#define PART_96xx 0xB2
+#define PART_95xx 0xB3
+#define PART_95xxN 0xB4
+#define PART_95xxMM 0xB5
#define PART_95O 0xB6
#define MODEL_IMPL_BITS 8
@@ -44,20 +44,21 @@ static const struct model_db {
uint64_t flag;
char name[ROC_MODEL_STR_LEN_MAX];
} model_db[] = {
- {VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, "cn10ka"},
- {VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, "cnf10ka"},
- {VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, "cnf10kb"},
- {VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
- {VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
- {VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
- {VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
- {VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
- {VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
- {VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, "cnf95xxn_a0"},
- {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, "cnf95O_a0"},
- {VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0,
- "cnf95xxmm_a0"}
-};
+ {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"},
+ {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"},
+ {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"},
+ {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
+ {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
+ {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
+ {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
+ {VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, "cn96xx_c1"},
+ {VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
+ {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
+ {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
+ {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
+ {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
+ {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
+ "cnf95xxmm_a0"}};
static uint32_t
cn10k_part_get(void)
@@ -85,11 +86,11 @@ cn10k_part_get(void)
}
ptr++;
if (strcmp("cn10ka", ptr) == 0) {
- soc = PART_106XX;
+ soc = PART_106xx;
} else if (strcmp("cnf10ka", ptr) == 0) {
- soc = PART_105XX;
+ soc = PART_105xx;
} else if (strcmp("cnf10kb", ptr) == 0) {
- soc = PART_105XXN;
+ soc = PART_105xxN;
} else {
plt_err("Unidentified 'CPU compatible': <%s>", ptr);
goto fclose;
diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
index c1d11b77c6..a54f435b46 100644
--- a/drivers/common/cnxk/roc_model.h
+++ b/drivers/common/cnxk/roc_model.h
@@ -15,13 +15,14 @@ struct roc_model {
#define ROC_MODEL_CN96xx_C0 BIT_ULL(2)
#define ROC_MODEL_CNF95xx_A0 BIT_ULL(4)
#define ROC_MODEL_CNF95xx_B0 BIT_ULL(6)
-#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8)
-#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12)
-#define ROC_MODEL_CNF95XXO_A0 BIT_ULL(13)
+#define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8)
+#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)
+#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)
+#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14)
#define ROC_MODEL_CN98xx_A0 BIT_ULL(16)
-#define ROC_MODEL_CN106XX BIT_ULL(20)
-#define ROC_MODEL_CNF105XX BIT_ULL(21)
-#define ROC_MODEL_CNF105XXN BIT_ULL(22)
+#define ROC_MODEL_CN106xx_A0 BIT_ULL(20)
+#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)
+#define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22)
uint64_t flag;
#define ROC_MODEL_STR_LEN_MAX 128
@@ -31,11 +32,15 @@ struct roc_model {
#define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0)
#define ROC_MODEL_CN9K \
(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \
- ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \
- ROC_MODEL_CNF95XXO_A0 | ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0)
+ ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \
+ ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
+ ROC_MODEL_CNF95xxN_A1)
+#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)
+#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)
+#define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0)
#define ROC_MODEL_CN10K \
- (ROC_MODEL_CN106XX | ROC_MODEL_CNF105XX | ROC_MODEL_CNF105XXN)
+ (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)
/* Runtime variants */
static inline uint64_t
@@ -105,6 +110,12 @@ roc_model_is_cn96_ax(void)
return (roc_model->flag & ROC_MODEL_CN96xx_Ax);
}
+static inline uint64_t
+roc_model_is_cn96_cx(void)
+{
+ return (roc_model->flag & ROC_MODEL_CN96xx_C0);
+}
+
static inline uint64_t
roc_model_is_cn95_a0(void)
{
@@ -114,19 +125,37 @@ roc_model_is_cn95_a0(void)
static inline uint64_t
roc_model_is_cn10ka(void)
{
- return roc_model->flag & ROC_MODEL_CN106XX;
+ return roc_model->flag & ROC_MODEL_CN106xx;
}
static inline uint64_t
roc_model_is_cnf10ka(void)
{
- return roc_model->flag & ROC_MODEL_CNF105XX;
+ return roc_model->flag & ROC_MODEL_CNF105xx;
}
static inline uint64_t
roc_model_is_cnf10kb(void)
{
- return roc_model->flag & ROC_MODEL_CNF105XXN;
+ return roc_model->flag & ROC_MODEL_CNF105xxN;
+}
+
+static inline uint64_t
+roc_model_is_cn10ka_a0(void)
+{
+ return roc_model->flag & ROC_MODEL_CN106xx_A0;
+}
+
+static inline uint64_t
+roc_model_is_cnf10ka_a0(void)
+{
+ return roc_model->flag & ROC_MODEL_CNF105xx_A0;
+}
+
+static inline uint64_t
+roc_model_is_cnf10kb_a0(void)
+{
+ return roc_model->flag & ROC_MODEL_CNF105xxN_A0;
}
int roc_model_init(struct roc_model *model);
--
2.32.0
next prev parent reply other threads:[~2021-09-17 9:36 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-30 14:08 [dpdk-dev] [PATCH] common/cnxk: avoid using stype STSTP in batch alloc Ashwin Sekhar T K
2021-08-30 16:29 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Ashwin Sekhar T K
2021-08-30 16:29 ` [dpdk-dev] [PATCH 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
2021-09-16 14:36 ` Jerin Jacob
2021-09-16 14:37 ` [dpdk-dev] [PATCH 1/2] common/cnxk: update roc models Jerin Jacob
2021-09-17 9:34 ` Ashwin Sekhar T K [this message]
2021-09-17 9:34 ` [dpdk-dev] [PATCH v2 2/2] common/cnxk: avoid using stashing option of stype Ashwin Sekhar T K
2021-09-20 8:51 ` [dpdk-dev] [PATCH v2 1/2] common/cnxk: update roc models Jerin Jacob
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