From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E900A0C46; Fri, 17 Sep 2021 13:24:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A8D8A410F1; Fri, 17 Sep 2021 13:24:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4511E40689 for ; Fri, 17 Sep 2021 13:24:33 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18GNENol030260; Fri, 17 Sep 2021 04:24:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=XTDzlRk0fq68fUxGXTJ2l/YKFUJhPLvgucATvBDJtHI=; b=Or0cdKl8tppX8XBdBTWbXyt6MdP0+yIsBRFIgPPIb8/ubxTXBUjjB6SqwZ7QaA8N/KN2 DUBYGn2KweStUDQk5L16rzwXVVy4DRrEUel/OemLqESKx5xIjJRdziMvrJNIEDu/1sM0 DcbP1/zs+y4ORzmRSR7pm5+H3n8/w+XNhn9R8LvaxBlRP/atXHy4dzCbYQSk3/hGggfV 6fCAwHtZqNzErbmLB/7pX6g9OHDvj0OuxWFb4Hm9SFJBR813HvwdBKvSe6ivBRtl/BOm Kw2u3Ykld2h6lyyHgUrIaBpFZaR7s2PTMwWCulQd03PY0eTTLsayaYxwkTO0a8scToSE rQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3b4fe1sw0f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 17 Sep 2021 04:24:31 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 17 Sep 2021 04:24:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 17 Sep 2021 04:24:30 -0700 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 46E093F705F; Fri, 17 Sep 2021 04:24:25 -0700 (PDT) From: Ashwin Sekhar T K To: CC: , , , , , , , , , Date: Fri, 17 Sep 2021 16:53:09 +0530 Message-ID: <20210917112309.270554-1-asekhar@marvell.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210830135231.2610152-1-asekhar@marvell.com> References: <20210830135231.2610152-1-asekhar@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: fwMo7rA2hq7Z0dYpmPIDfOoKKsAVrm-N X-Proofpoint-ORIG-GUID: fwMo7rA2hq7Z0dYpmPIDfOoKKsAVrm-N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-17_05,2021-09-17_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2] common/cnxk: align NPA stack to ROC cache line size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Network Pool accelerator (NPA) is part of ROC (Rest Of Chip). So NPA structures should be aligned to ROC Cache line size and not CPU cache line size. Non alignment of NPA stack to ROC cache line will result in undefined runtime NPA behaviour. Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations") Signed-off-by: Ashwin Sekhar T K Acked-by: Jerin Jacob --- drivers/common/cnxk/roc_npa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index d064d125c1..a0d2cc8f19 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size) { const char *mz_name = npa_stack_memzone_name(lf, pool_id, name); - return plt_memzone_reserve_cache_align(mz_name, size); + return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN); } static inline int -- 2.32.0