From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 487CDA0C4C; Tue, 21 Sep 2021 13:01:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 35AAF410FA; Tue, 21 Sep 2021 13:01:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id ADD08410F7 for ; Tue, 21 Sep 2021 13:01:01 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18L99JBx005235 for ; Tue, 21 Sep 2021 04:01:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=XBos2qS3rok7CCb3iznJ++OkTrZnATjQeGsTTkzSdo4=; b=c4RzwGhuExX31rGTtwMsHsYrDbzW4tac4Ch2mdPtjH0mBNXcmLmwXrJDeQnlAdrCZueQ jiiTJqbYP9D5Qp+xhmhC/55OkIRt4EgMHjjrWQCG/kgFilJLzrG94RJDpxse27dIP2QV iCPKK44l4mFCOAwlVWPSdK/zcnf6ARd69bm0WHXQHrR0xWSuYU09xM4HaW2cnUqW3k+c ZPvYEkkFZgpqn6EmZ127PcISKe/4cPqD7O9zD6I6p3A4zP0zRY6mIazdtH3qRIQKWTqY KIZS74/ThU9AI8wYZ1z3zxXLzxg9e7Z0EK5LXcuTU9keOAPVkDgvCU1WIGd0cVZCQy82 GA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3b7cgt88vk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 21 Sep 2021 04:01:00 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 21 Sep 2021 04:00:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 21 Sep 2021 04:00:59 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 5F3CA3F706B; Tue, 21 Sep 2021 04:00:57 -0700 (PDT) From: Harman Kalra To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Harman Kalra Date: Tue, 21 Sep 2021 16:30:38 +0530 Message-ID: <20210921110038.115560-2-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210921110038.115560-1-hkalra@marvell.com> References: <20210921110038.115560-1-hkalra@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: fmcGzj_u7022ngmbKmauWCYJPsYOIBMu X-Proofpoint-GUID: fmcGzj_u7022ngmbKmauWCYJPsYOIBMu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-21_01,2021-09-20_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 2/2] common/cnxk: cq overflow issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" An issue exists on some HW revisions whereby if a CQ overflows NIX may have undefined behavior, e.g. free incorrect buffers. Implementing a workaround for this known HW issue. Signed-off-by: Harman Kalra --- drivers/common/cnxk/roc_nix_priv.h | 3 ++- drivers/common/cnxk/roc_nix_queue.c | 18 +++++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 9dc0c88a6f..1bd1b6a36b 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -17,7 +17,8 @@ /* Apply BP/DROP when CQ is 95% full */ #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100) -#define NIX_RQ_AURA_THRESH(x) (((x) * 95) / 100) +#define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256) +#define NIX_RQ_AURA_THRESH(x) (((x)*95) / 100) /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */ #define CQ_CQE_THRESH_DEFAULT 0x1ULL diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 76e439e7a9..d7c4844d69 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -2,6 +2,8 @@ * Copyright(C) 2021 Marvell. */ +#include + #include "roc_api.h" #include "roc_priv.h" @@ -435,7 +437,6 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) cq->status = (int64_t *)(nix->base + NIX_LF_CQ_OP_STATUS); cq->wdata = (uint64_t)cq->qid << 32; cq->roc_nix = roc_nix; - cq->drop_thresh = NIX_CQ_THRESH_LEVEL; /* CQE of W16 */ desc_sz = cq->nb_desc * NIX_CQ_ENTRY_SZ; @@ -476,8 +477,19 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */ cq_ctx->cint_idx = cq->qid; - cq_ctx->drop = cq->drop_thresh; - cq_ctx->drop_ena = 1; + if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) { + const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID; + uint16_t min_rx_drop; + + min_rx_drop = ceil(rx_cq_skid / (float)cq->nb_desc); + cq_ctx->drop = min_rx_drop; + cq_ctx->drop_ena = 1; + cq->drop_thresh = min_rx_drop; + } else { + cq->drop_thresh = NIX_CQ_THRESH_LEVEL; + cq_ctx->drop = cq->drop_thresh; + cq_ctx->drop_ena = 1; + } /* TX pause frames enable flow ctrl on RX side */ if (nix->tx_pause) { -- 2.18.0