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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.36 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.36; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.36) by CO1NAM11FT045.mail.protection.outlook.com (10.13.175.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4544.13 via Frontend Transport; Mon, 27 Sep 2021 08:34:02 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 27 Sep 2021 08:34:01 +0000 Received: from nvidia.com (172.20.187.5) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 27 Sep 2021 08:34:00 +0000 From: Xueming Li To: CC: , Matan Azrad , "Viacheslav Ovsiienko" Date: Mon, 27 Sep 2021 16:32:54 +0800 Message-ID: <20210927083256.337450-7-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210927083256.337450-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3a0a06f3-a13c-406c-5fab-08d981918f5b X-MS-TrafficTypeDiagnostic: DM6PR12MB4249: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:227; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(316002)(70586007)(508600001)(5660300002)(2616005)(2906002)(6666004)(82310400003)(6916009)(36860700001)(36756003)(36906005)(70206006)(83380400001)(356005)(1076003)(336012)(8676002)(107886003)(86362001)(54906003)(16526019)(55016002)(7696005)(426003)(47076005)(26005)(186003)(6286002)(4326008)(8936002)(7636003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2021 08:34:02.3917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a0a06f3-a13c-406c-5fab-08d981918f5b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4249 Subject: [dpdk-dev] [PATCH 6/8] net/mlx5: supports flow item of normal Tx queue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Extends txq flow pattern to support both hairpin and regular txq. Signed-off-by: Xueming Li --- drivers/net/mlx5/mlx5_flow_dv.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index d4242a4aa8d..e388e2d5e10 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -10916,22 +10916,22 @@ flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev, void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters); struct mlx5_txq_ctrl *txq; - uint32_t queue; - + uint32_t queue, mask; queue_m = (const void *)item->mask; - if (!queue_m) - return; queue_v = (const void *)item->spec; if (!queue_v) return; txq = mlx5_txq_get(dev, queue_v->queue); if (!txq) return; - queue = txq->obj->sq->id; - MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue); - MLX5_SET(fte_match_set_misc, misc_v, source_sqn, - queue & queue_m->queue); + if (txq->type == MLX5_TXQ_TYPE_HAIRPIN) + queue = txq->obj->sq->id; + else + queue = txq->obj->sq_obj.sq->id; + mask = queue_m == NULL ? UINT32_MAX : queue_m->queue; + MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask); + MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask); mlx5_txq_release(dev, queue_v->queue); } -- 2.33.0