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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.35 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.35; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.35) by BN8NAM11FT024.mail.protection.outlook.com (10.13.177.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4544.13 via Frontend Transport; Mon, 27 Sep 2021 08:34:05 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 27 Sep 2021 08:34:03 +0000 Received: from nvidia.com (172.20.187.5) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 27 Sep 2021 08:34:02 +0000 From: Xueming Li To: CC: , Matan Azrad , "Viacheslav Ovsiienko" , Dong Zhou Date: Mon, 27 Sep 2021 16:32:55 +0800 Message-ID: <20210927083256.337450-8-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210927083256.337450-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0eddf403-9242-44b6-acc6-08d981919145 X-MS-TrafficTypeDiagnostic: CY4PR12MB1526: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(2616005)(70206006)(6286002)(7696005)(70586007)(1076003)(7636003)(26005)(2906002)(54906003)(8676002)(36756003)(6916009)(82310400003)(316002)(107886003)(47076005)(36860700001)(356005)(186003)(508600001)(16526019)(83380400001)(4326008)(86362001)(426003)(5660300002)(55016002)(336012)(6666004)(36906005)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2021 08:34:05.5640 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0eddf403-9242-44b6-acc6-08d981919145 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1526 Subject: [dpdk-dev] [PATCH 7/8] net/mlx5: fix internal root table flow priroity X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When creating internal transfer flow on root table with lowerest priority, the flow was created with u32 priority. It was wrong since the flow is created in kernel and max priority supported is 16. This patch fixes this by adding internal flow check. Fixes: 5f8ae44dd454 ("net/mlx5: enlarge maximal flow priority") Signed-off-by: Xueming Li --- drivers/net/mlx5/mlx5_flow.c | 7 +++++-- drivers/net/mlx5/mlx5_flow.h | 4 ++-- drivers/net/mlx5/mlx5_flow_dv.c | 3 ++- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index c914a7120cc..8dc79340f2d 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -980,13 +980,15 @@ mlx5_get_lowest_priority(struct rte_eth_dev *dev, * Pointer to device flow rule attributes. * @param[in] subpriority * The priority based on the items. + * @param[in] external + * Flow is user flow. * @return * The matcher priority of the flow. */ uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, - uint32_t subpriority) + uint32_t subpriority, bool external) { uint16_t priority = (uint16_t)attr->priority; struct mlx5_priv *priv = dev->data->dev_private; @@ -997,7 +999,8 @@ mlx5_get_matcher_priority(struct rte_eth_dev *dev, return mlx5_os_flow_adjust_priority(dev, priority, subpriority); } if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) - priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; + priority = external ? + MLX5_NON_ROOT_FLOW_MAX_PRIO : priv->config.flow_prio; return priority * 3 + subpriority; } diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 861e18fb3b1..1e31d25f319 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1434,8 +1434,8 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, const struct rte_flow_attr *attr); uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, - const struct rte_flow_attr *attr, - uint32_t subpriority); + const struct rte_flow_attr *attr, + uint32_t subpriority, bool external); int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, enum mlx5_feature_name feature, uint32_t id, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index e388e2d5e10..3744f3e5917 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -13633,7 +13633,8 @@ flow_dv_translate(struct rte_eth_dev *dev, matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf, matcher.mask.size); matcher.priority = mlx5_get_matcher_priority(dev, attr, - matcher.priority); + matcher.priority, + dev_flow->external); /** * When creating meter drop flow in drop table, using original * 5-tuple match, the matcher priority should be lower than -- 2.33.0