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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT053.mail.protection.outlook.com (10.13.175.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4544.13 via Frontend Transport; Tue, 28 Sep 2021 12:17:11 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 28 Sep 2021 12:17:10 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 28 Sep 2021 12:17:09 +0000 From: Raja Zidane To: Date: Tue, 28 Sep 2021 12:16:48 +0000 Message-ID: <20210928121650.40181-4-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210928121650.40181-1-rzidane@nvidia.com> References: <20210915000504.5660-1-rzidane@nvidia.com> <20210928121650.40181-1-rzidane@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 685000ff-6a63-4165-d34d-08d98279e625 X-MS-TrafficTypeDiagnostic: MWHPR1201MB2479: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:792; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(2906002)(86362001)(36756003)(6916009)(8936002)(186003)(83380400001)(26005)(1076003)(6286002)(36860700001)(47076005)(508600001)(7696005)(82310400003)(426003)(16526019)(336012)(70586007)(55016002)(8676002)(70206006)(356005)(2616005)(5660300002)(316002)(6666004)(7636003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2021 12:17:11.2458 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 685000ff-6a63-4165-d34d-08d98279e625 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB2479 Subject: [dpdk-dev] [PATCH V4 3/5] common/mlx5: add MMO configuration for the DevX QP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A new configuration MMO was added to QP Context. If set, MMO WQEs are supported on this QP. For DMA MMO, supported only when dma_mmo_qp==1. For REGEXP MMO, supported only when regexp_mmo_qp==1. For COMPRESS MMO, supported only when compress_mmo_qp==1. For DECOMPRESS MMO, supported only when decompress_mmo_qp==1. Add support to DevX interface to set MMO bit. Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 28 +++++++++++++++++++++++++++- 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 00c78b1288..eefb869b7d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -2032,6 +2032,13 @@ mlx5_devx_cmd_create_qp(void *ctx, MLX5_SET(qpc, qpc, ts_format, attr->ts_format); MLX5_SET(qpc, qpc, user_index, attr->user_index); if (attr->uar_index) { + if (attr->mmo) { + void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, + in, qpc_extension_and_pas_list); + void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, + qpc_ext_and_pas_list, qpc_data_extension); + MLX5_SET(qpc_extension, qpc_ext, mmo, 1); + } MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); MLX5_SET(qpc, qpc, uar_page, attr->uar_index); if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index b21df0fd9b..e149f8b4f5 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -403,6 +403,7 @@ struct mlx5_devx_qp_attr { uint32_t wq_umem_id; uint64_t wq_umem_offset; uint32_t user_index:24; + uint32_t mmo:1; }; struct mlx5_devx_virtio_q_couners_attr { diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ec5f871c61..54e62aa153 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3243,6 +3243,28 @@ struct mlx5_ifc_create_qp_out_bits { u8 reserved_at_60[0x20]; }; +struct mlx5_ifc_qpc_extension_bits { + u8 reserved_at_0[0x2]; + u8 mmo[0x1]; + u8 reserved_at_3[0x5fd]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_pas_list_bits { + u8 pas[0][0x40]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_extension_and_pas_list_bits { + struct mlx5_ifc_qpc_extension_bits qpc_data_extension; + u8 pas[0][0x40]; +}; + + #ifdef PEDANTIC #pragma GCC diagnostic ignored "-Wpedantic" #endif @@ -3260,7 +3282,11 @@ struct mlx5_ifc_create_qp_in_bits { u8 wq_umem_id[0x20]; u8 wq_umem_valid[0x1]; u8 reserved_at_861[0x1f]; - u8 pas[0][0x40]; + union { + struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; + struct mlx5_ifc_qpc_extension_and_pas_list_bits + qpc_extension_and_pas_list; + }; }; #ifdef PEDANTIC #pragma GCC diagnostic error "-Wpedantic" -- 2.17.1