From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 150EBA0032; Fri, 1 Oct 2021 15:41:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DFF8A41196; Fri, 1 Oct 2021 15:40:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 0400A411C1 for ; Fri, 1 Oct 2021 15:40:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 191A8GOk029756 for ; Fri, 1 Oct 2021 06:40:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=3c375LWcwIFvmYdIdGvJcfA/PnfdswhT+vSwBrWhNl4=; b=GN5NDymiLUydhp4jxERkzuna2XhN0NVDY37Du0ZE95hn4c1WRYnNw56oUipqq84DZHnq YAWPbXpnwuE+rbchuT4LfgvRxspDwlWbzb0+T7SFp9VxxozdY8QtXE+tD4Ycn+Vw6avS zHW6OGrb843xsX7lSR1szdH4V8bQ5myhxIHFhlraxOfddrMfcr3/D55TecPjq2Cp6oiP uLc2RfC2DtqtT4aOSdgr4xVcsWBt+RfY7kIbhpMStItaZABsBvOFhjD6bgW6mXQGjblh 52DAa/GLDetukyWy34kjjwkY3GKvT2HJlJ3VSRkNEER/2FvNhnz3n1xqHj8UTCGtjcU2 gA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bdrxmhxa4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 01 Oct 2021 06:40:53 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 1 Oct 2021 06:40:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 1 Oct 2021 06:40:51 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 8830D3F7041; Fri, 1 Oct 2021 06:40:49 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Date: Fri, 1 Oct 2021 19:10:03 +0530 Message-ID: <20211001134022.22700-10-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211001134022.22700-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> <20211001134022.22700-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: M0xuJeHvW53gz_KvMfeLHKK_cZVSesPj X-Proofpoint-ORIG-GUID: M0xuJeHvW53gz_KvMfeLHKK_cZVSesPj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-01_02,2021-10-01_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 09/28] common/cnxk: dump CPT LF registers on error intr X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Dump CPT LF registers on error interrupt for debugging purpose. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_cpt.c | 5 ++++- drivers/common/cnxk/roc_cpt_debug.c | 32 ++++++++++++++++++++++++++++++-- drivers/common/cnxk/roc_cpt_priv.h | 1 + 3 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 48a378b..6ddbaa2 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -51,6 +51,9 @@ cpt_lf_misc_irq(void *param) plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf); + /* Dump lf registers */ + cpt_lf_print(lf); + /* Clear interrupt */ plt_write64(intr, lf->rbase + CPT_LF_MISC_INT); } @@ -203,7 +206,7 @@ cpt_lf_dump(struct roc_cpt_lf *lf) plt_cpt_dbg("CPT LF REG:"); plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016" PRIx64, CPT_LF_CTL, plt_read64(lf->rbase + CPT_LF_CTL)); - plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG, + plt_cpt_dbg("LF_INPROG[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG, plt_read64(lf->rbase + CPT_LF_INPROG)); plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_BASE, diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c index a6c9004..847d969 100644 --- a/drivers/common/cnxk/roc_cpt_debug.c +++ b/drivers/common/cnxk/roc_cpt_debug.c @@ -157,11 +157,40 @@ roc_cpt_afs_print(struct roc_cpt *roc_cpt) return 0; } -static void +void cpt_lf_print(struct roc_cpt_lf *lf) { uint64_t reg_val; + reg_val = plt_read64(lf->rbase + CPT_LF_Q_BASE); + plt_print(" CPT_LF_Q_BASE:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_Q_SIZE); + plt_print(" CPT_LF_Q_SIZE:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_Q_INST_PTR); + plt_print(" CPT_LF_Q_INST_PTR:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR); + plt_print(" CPT_LF_Q_GRP_PTR:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_CTL); + plt_print(" CPT_LF_CTL:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT_ENA_W1S); + plt_print(" CPT_LF_MISC_INT_ENA_W1S:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT); + plt_print(" CPT_LF_MISC_INT:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_INPROG); + plt_print(" CPT_LF_INPROG:\t%016lx", reg_val); + + if (roc_model_is_cn9k()) + return; + + plt_print("Count registers for CPT LF%d:", lf->lf_id); + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT); plt_print(" Encrypted byte count:\t%" PRIu64, reg_val); @@ -190,7 +219,6 @@ roc_cpt_lfs_print(struct roc_cpt *roc_cpt) if (lf == NULL) continue; - plt_print("Count registers for CPT LF%d:", lf_id); cpt_lf_print(lf); } diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h index 21911e5..61dec9a 100644 --- a/drivers/common/cnxk/roc_cpt_priv.h +++ b/drivers/common/cnxk/roc_cpt_priv.h @@ -31,5 +31,6 @@ int cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func, uint8_t lf_id, bool ena); int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp); uint64_t cpt_get_blkaddr(struct dev *dev); +void cpt_lf_print(struct roc_cpt_lf *lf); #endif /* _ROC_CPT_PRIV_H_ */ -- 2.8.4