From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9D088A0032; Fri, 1 Oct 2021 21:35:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C9BBE41244; Fri, 1 Oct 2021 21:35:01 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2060.outbound.protection.outlook.com [40.107.94.60]) by mails.dpdk.org (Postfix) with ESMTP id 1406E41245 for ; Fri, 1 Oct 2021 21:35:01 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VzC/T+z4BrjQJQuvkcetit+OGI9sln1ES2EwL9xp5x6Oofn6HCnhS6ZgUbbDh5NXxphmP+xjHKUJ+fkVWvGGCk2XtMsJaD71gZXW+bPm60KKpzQ7vw2BFm3TGQ2c/zJ/7uPSXUdHiRTzaERFnk+UVzzU5X77AmcldIyA9XqRMpyDWMh3/PqrekvNY1Ca2Eaz0bSZnDt71DetP/ctEMxYz3W8pSoa8rhFJeANCy18NmZPARjvcUZ8alKrAOxRwFc4BxO7uKITFMK54NTmnWyroRV5XjtS1KcL8I8DPCXuyqzfgbfQ05xckN0i7e8QuyJ702BijAyPOv/BdvJNjFjbOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=krJNwU4i8QalYZx3Dy+KWCkDmGIqCG9VmFqWbMMUr/w=; b=iuyDKHChlQ8JfagwNI3hLBPtAg/xhWGfsRbl5ppPVrAKVIBYm4Z36teg6JzuBK+o/Xty9vx9TWGrBVtOdkfrW9RARiHwc6QRSkpPmWSujFlQjAVoFnK+rare+jlO56PzYALZcwhjpmTs8XV100aHhsPHuuyD+eKzsSDEhtRH2S0h4jNcgMUsPptuG+CyIOJuQBDpXyh03GziCE4AuF7VdmvO2JgPK+KSAKZiOuj/guPKZ9A7wcPjeeZ4Kx/mHqEVZmrxof6//JbdtZkCfZqdJA58fKWXQnQ32it5RH5cuvHQRmm6lbvTB43fc+dONwDcBq8OtE7Y8Bq7KUL+695I/g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=krJNwU4i8QalYZx3Dy+KWCkDmGIqCG9VmFqWbMMUr/w=; b=j3mD1EWo05LcoYMdpS8fqdbdzoD1Eo6REG4aM9Z4Fq88LLGhp5jGPNaw2okN2PcXDjHcbRTOQUMejJD3hxUp4fiu1J06h8ofpELa5zPA9y19iBtQcfKfb8c+XnpF6G0IVG/DtZmsQTaltAdSaAecbwzJexrno8QuogaCsRm36Nky05whht7/loxV+a0wrqOfUMo1uFGYCt+fZ6gR/SgsYJUQYx96rLGP9IZdECq4akBGezF/gktrCGpJQZ5a7ZyaQs02x9Uz41ExGORsOTiwPR6F7HhSc918U/0ThGCJsi0qDoWgqqCf6ECfNWAE2QaDeZ5CsJ2OLmjJUQiU7PZbHg== Received: from BN6PR14CA0019.namprd14.prod.outlook.com (2603:10b6:404:79::29) by CY4PR12MB1926.namprd12.prod.outlook.com (2603:10b6:903:11b::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.15; Fri, 1 Oct 2021 19:34:58 +0000 Received: from BN8NAM11FT068.eop-nam11.prod.protection.outlook.com (2603:10b6:404:79:cafe::b5) by BN6PR14CA0019.outlook.office365.com (2603:10b6:404:79::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.20 via Frontend Transport; Fri, 1 Oct 2021 19:34:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT068.mail.protection.outlook.com (10.13.177.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4566.14 via Frontend Transport; Fri, 1 Oct 2021 19:34:57 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 1 Oct 2021 19:34:54 +0000 From: Viacheslav Ovsiienko To: CC: , , , , , Date: Fri, 1 Oct 2021 22:34:08 +0300 Message-ID: <20211001193415.23288-8-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20211001193415.23288-1-viacheslavo@nvidia.com> References: <20210922180418.20663-1-viacheslavo@nvidia.com> <20211001193415.23288-1-viacheslavo@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f2786a0e-c803-488b-32e6-08d985128d7e X-MS-TrafficTypeDiagnostic: CY4PR12MB1926: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2201; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sxlHP58oEY92wjPK4r32/kAAMmofeHILfYfaF4zO+/P/nK4sFkqS+K7gGeztyUA0r2mu6gxYkUKcsT7qRlIHmwQQFuYPj/Xx+i4pyKUcoqQykSHv/mtsM+TZEQHxIqPpTcmzYxar+M9MjSmpTNP64o/OSNpiZ9D+pJjAagVxTT3trqbNa07eJY6c6Xwdnz0cL5/twrR32grqxTTTKpcJ1ZvigYWDqZJdGr5Ur644F/n8D39CsZIGUrqpJEmScyC9uUsBQiicV6tk1YfOshmm483XfsUjPUyoYORnPliNzuftoJ3phGHyKtmVvw0vCFLpi8CPUyfjP4T2EdIhUcMcP50/AK/1yetTiDxy2/OQvxs/pil4S8Yv9NM7oxnbsZPBZVsbh+Ofcv2WkuuHIjSELVUPkD0MaUZ98VJZIPNnr0c598NkQWwQphp0yQgNRy6G+y68wzZlQIbFSDtki4YoZQVX49t85+zHC04qm/XvkJguzUB7wxPHGNJ0Donhdz9dPzOLVtyzOYA2B8eHstkuHEqhJTSnR2H0/lrOTbUPyOHPuVW5/8n216bvPKaA+aDsKRzqbLK8WzuPE7K0dVgHlLCqPOyXqsasQ4IbrdFdfLFZ+NgsdNKQNydvocNJfXt0Cd6u/JGoXlSv7e3P8EjsHCWhnoojtd5EoVWsAOew1UslY1p4kDymKoodf92O4sSoc75ezzVWU+SjCC403kXZSQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(36756003)(82310400003)(7696005)(336012)(6916009)(508600001)(4326008)(186003)(16526019)(6666004)(5660300002)(356005)(86362001)(26005)(7636003)(55016002)(2616005)(8936002)(316002)(6286002)(54906003)(8676002)(36860700001)(2906002)(83380400001)(70206006)(47076005)(70586007)(1076003)(426003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2021 19:34:57.7013 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2786a0e-c803-488b-32e6-08d985128d7e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1926 Subject: [dpdk-dev] [PATCH v2 07/14] common/mlx5: extend flex parser capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Gregory Etelson MLX5 PARSE_GRAPH_NODE is the main data structure used by the Flex Parser when a new parsing protocol is defined. While software creates PARSE_GRAPH_NODE object for a new protocol, it must verify that configuration parameters it uses comply with hardware limits. The patch queries hardware PARSE_GRAPH_NODE capabilities and stores ones in PMD internal configuration structure: - query capabilties from parse_graph_node attribute page - query max_num_prog_sample_field capability from HCA page 2 Signed-off-by: Gregory Etelson --- drivers/common/mlx5/mlx5_devx_cmds.c | 57 ++++++++++++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 65 +++++++++++++++++++++++++++- drivers/common/mlx5/mlx5_prm.h | 50 ++++++++++++++++++++- 3 files changed, 168 insertions(+), 4 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 8273e98146..294ac480dc 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -729,6 +729,53 @@ mlx5_devx_cmd_create_flex_parser(void *ctx, return parse_flex_obj; } +static int +mlx5_devx_cmd_query_hca_parse_graph_node_cap + (void *ctx, struct mlx5_hca_flex_attr *attr) +{ + uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; + uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; + void *hcattr; + int rc; + + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) + return rc; + attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); + attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); + attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, + header_length_mode); + attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, + sample_offset_mode); + attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, + max_num_arc_in); + attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, + max_num_arc_out); + attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, + max_num_sample); + attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, + sample_id_in_out); + attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, + max_base_header_length); + attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, + max_sample_base_offset); + attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, + max_next_header_offset); + attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, + header_length_mask_width); + /* Get the max supported samples from HCA CAP 2 */ + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) + return rc; + attr->max_num_prog_sample = + MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); + return 0; +} + static int mlx5_devx_query_pkt_integrity_match(void *hcattr) { @@ -933,6 +980,16 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, log_max_num_meter_aso); } } + /* + * Flex item support needs max_num_prog_sample_field + * from the Capabilities 2 table for PARSE_GRAPH_NODE + */ + if (attr->parse_graph_flex_node) { + rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap + (ctx, &attr->flex); + if (rc) + return -1; + } if (attr->vdpa.valid) mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); if (!attr->eth_net_offloads) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index e576e30f24..fcd0b12e22 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -8,6 +8,7 @@ #include "mlx5_glue.h" #include "mlx5_prm.h" #include +#include /* * Defines the amount of retries to allocate the first UAR in the page. @@ -94,6 +95,64 @@ struct mlx5_hca_flow_attr { uint32_t tunnel_header_2_3; }; +/** + * Accumulate port PARSE_GRAPH_NODE capabilities from + * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables + */ +__extension__ +struct mlx5_hca_flex_attr { + uint32_t node_in; + uint32_t node_out; + uint16_t header_length_mode; + uint16_t sample_offset_mode; + uint8_t max_num_arc_in; + uint8_t max_num_arc_out; + uint8_t max_num_sample; + uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ + uint8_t sample_id_in_out:1; + uint16_t max_base_header_length; + uint8_t max_sample_base_offset; + uint16_t max_next_header_offset; + uint8_t header_length_mask_width; +}; + +/* ISO C restricts enumerator values to range of 'int' */ +__extension__ +enum { + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) +}; + +enum { + PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), + PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), + PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) +}; + +/* + * DWORD shift is the base for calculating header_length_field_mask + * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. + */ +#define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 + +static inline uint32_t +mlx5_hca_parse_graph_node_base_hdr_len_mask + (const struct mlx5_hca_flex_attr *attr) +{ + return (1 << attr->header_length_mask_width) - 1; +} + /* HCA supports this number of time periods for LRO. */ #define MLX5_LRO_NUM_SUPP_PERIODS 4 @@ -164,6 +223,7 @@ struct mlx5_hca_attr { struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; struct mlx5_hca_flow_attr flow; + struct mlx5_hca_flex_attr flex; int log_max_qp_sz; int log_max_cq_sz; int log_max_qp; @@ -570,8 +630,9 @@ int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, uint32_t ids[], uint32_t num); __rte_internal -struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, - struct mlx5_devx_graph_node_attr *data); +struct mlx5_devx_obj * +mlx5_devx_cmd_create_flex_parser(void *ctx, + struct mlx5_devx_graph_node_attr *data); __rte_internal int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index d361bcf90e..3ff14b4a5a 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -975,7 +975,14 @@ struct mlx5_ifc_fte_match_set_misc4_bits { u8 prog_sample_field_id_2[0x20]; u8 prog_sample_field_value_3[0x20]; u8 prog_sample_field_id_3[0x20]; - u8 reserved_at_100[0x100]; + u8 prog_sample_field_value_4[0x20]; + u8 prog_sample_field_id_4[0x20]; + u8 prog_sample_field_value_5[0x20]; + u8 prog_sample_field_id_5[0x20]; + u8 prog_sample_field_value_6[0x20]; + u8 prog_sample_field_id_6[0x20]; + u8 prog_sample_field_value_7[0x20]; + u8 prog_sample_field_id_7[0x20]; }; struct mlx5_ifc_fte_match_set_misc5_bits { @@ -1244,6 +1251,7 @@ enum { MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, + MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, }; @@ -1750,6 +1758,27 @@ struct mlx5_ifc_virtio_emulation_cap_bits { u8 reserved_at_1c0[0x620]; }; +/** + * PARSE_GRAPH_NODE Capabilities Field Descriptions + */ +struct mlx5_ifc_parse_graph_node_cap_bits { + u8 node_in[0x20]; + u8 node_out[0x20]; + u8 header_length_mode[0x10]; + u8 sample_offset_mode[0x10]; + u8 max_num_arc_in[0x08]; + u8 max_num_arc_out[0x08]; + u8 max_num_sample[0x08]; + u8 reserved_at_78[0x07]; + u8 sample_id_in_out[0x1]; + u8 max_base_header_length[0x10]; + u8 reserved_at_90[0x08]; + u8 max_sample_base_offset[0x08]; + u8 max_next_header_offset[0x10]; + u8 reserved_at_b0[0x08]; + u8 header_length_mask_width[0x08]; +}; + struct mlx5_ifc_flow_table_prop_layout_bits { u8 ft_support[0x1]; u8 flow_tag[0x1]; @@ -1844,9 +1873,14 @@ struct mlx5_ifc_flow_table_nic_cap_bits { ft_field_support_2_nic_receive; }; +/* + * HCA Capabilities 2 + */ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 reserved_at_0[0x80]; /* End of DW4. */ - u8 reserved_at_80[0xb]; + u8 reserved_at_80[0x3]; + u8 max_num_prog_sample_field[0x5]; + u8 reserved_at_88[0x3]; u8 log_max_num_reserved_qpn[0x5]; u8 reserved_at_90[0x3]; u8 log_reserved_qpn_granularity[0x5]; @@ -3877,6 +3911,12 @@ enum mlx5_parse_graph_flow_match_sample_offset_mode { MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, }; +enum mlx5_parse_graph_flow_match_sample_tunnel_mode { + MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0, + MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1, + MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2 +}; + /* Node index for an input / output arc of the flex parser graph. */ enum mlx5_parse_graph_arc_node_index { MLX5_GRAPH_ARC_NODE_NULL = 0x0, @@ -3890,9 +3930,15 @@ enum mlx5_parse_graph_arc_node_index { MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, + MLX5_GRAPH_ARC_NODE_IPV4 = 0xb, + MLX5_GRAPH_ARC_NODE_IPV6 = 0xc, MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, }; +#define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8 +#define MLX5_PARSE_GRAPH_IN_ARC_MAX 8 +#define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8 + /** * Convert a user mark to flow mark. * -- 2.18.1