From: <pbhagavatula@marvell.com>
To: <ruifeng.wang@arm.com>, <konstantin.ananyev@intel.com>,
<jerinj@marvell.com>, Yipeng Wang <yipeng1.wang@intel.com>,
Sameh Gobriel <sameh.gobriel@intel.com>,
Bruce Richardson <bruce.richardson@intel.com>,
Vladimir Medvedkin <vladimir.medvedkin@intel.com>
Cc: <dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>
Subject: [dpdk-dev] [PATCH v3 2/2] hash: unify crc32 selection for x86 and Arm
Date: Mon, 4 Oct 2021 04:30:07 +0530 [thread overview]
Message-ID: <20211003230008.12730-2-pbhagavatula@marvell.com> (raw)
In-Reply-To: <20211003230008.12730-1-pbhagavatula@marvell.com>
From: Pavan Nikhilesh <pbhagavatula@marvell.com>
Merge crc32 hash calculation public API implementation for x86 and Arm.
Select the best available CRC32 algorithm when unsupported algorithm
on a given CPU architecture is requested by an application.
Previously, if an application directly includes `rte_crc_arm64.h`
without including `rte_hash_crc.h` it will fail to compile.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
lib/hash/hash_crc_arm64.h | 48 ++++++++++
lib/hash/meson.build | 1 -
lib/hash/rte_crc_arm64.h | 183 --------------------------------------
lib/hash/rte_hash_crc.h | 75 ++++++++++++----
4 files changed, 108 insertions(+), 199 deletions(-)
create mode 100644 lib/hash/hash_crc_arm64.h
delete mode 100644 lib/hash/rte_crc_arm64.h
diff --git a/lib/hash/hash_crc_arm64.h b/lib/hash/hash_crc_arm64.h
new file mode 100644
index 0000000000..29b61a07a9
--- /dev/null
+++ b/lib/hash/hash_crc_arm64.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 Cavium, Inc
+ */
+
+#ifndef _HASH_CRC_ARM64_H_
+#define _HASH_CRC_ARM64_H_
+
+static inline uint32_t
+crc32c_arm64_u8(uint8_t data, uint32_t init_val)
+{
+ __asm__ volatile(
+ "crc32cb %w[crc], %w[crc], %w[value]"
+ : [crc] "+r" (init_val)
+ : [value] "r" (data));
+ return init_val;
+}
+
+static inline uint32_t
+crc32c_arm64_u16(uint16_t data, uint32_t init_val)
+{
+ __asm__ volatile(
+ "crc32ch %w[crc], %w[crc], %w[value]"
+ : [crc] "+r" (init_val)
+ : [value] "r" (data));
+ return init_val;
+}
+
+static inline uint32_t
+crc32c_arm64_u32(uint32_t data, uint32_t init_val)
+{
+ __asm__ volatile(
+ "crc32cw %w[crc], %w[crc], %w[value]"
+ : [crc] "+r" (init_val)
+ : [value] "r" (data));
+ return init_val;
+}
+
+static inline uint32_t
+crc32c_arm64_u64(uint64_t data, uint32_t init_val)
+{
+ __asm__ volatile(
+ "crc32cx %w[crc], %w[crc], %x[value]"
+ : [crc] "+r" (init_val)
+ : [value] "r" (data));
+ return init_val;
+}
+
+#endif /* _HASH_CRC_ARM64_H_ */
diff --git a/lib/hash/meson.build b/lib/hash/meson.build
index 9bc5ef925a..8794ea82a7 100644
--- a/lib/hash/meson.build
+++ b/lib/hash/meson.build
@@ -8,7 +8,6 @@ headers = files(
'rte_jhash.h',
'rte_thash.h',
)
-indirect_headers += files('rte_crc_arm64.h')
sources = files('rte_cuckoo_hash.c', 'rte_fbk_hash.c', 'rte_thash.c')
deps += ['net']
diff --git a/lib/hash/rte_crc_arm64.h b/lib/hash/rte_crc_arm64.h
deleted file mode 100644
index b4628cfc09..0000000000
--- a/lib/hash/rte_crc_arm64.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2015 Cavium, Inc
- */
-
-#ifndef _RTE_CRC_ARM64_H_
-#define _RTE_CRC_ARM64_H_
-
-/**
- * @file
- *
- * RTE CRC arm64 Hash
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <rte_cpuflags.h>
-#include <rte_branch_prediction.h>
-#include <rte_common.h>
-
-static inline uint32_t
-crc32c_arm64_u8(uint8_t data, uint32_t init_val)
-{
- __asm__ volatile(
- "crc32cb %w[crc], %w[crc], %w[value]"
- : [crc] "+r" (init_val)
- : [value] "r" (data));
- return init_val;
-}
-
-static inline uint32_t
-crc32c_arm64_u16(uint16_t data, uint32_t init_val)
-{
- __asm__ volatile(
- "crc32ch %w[crc], %w[crc], %w[value]"
- : [crc] "+r" (init_val)
- : [value] "r" (data));
- return init_val;
-}
-
-static inline uint32_t
-crc32c_arm64_u32(uint32_t data, uint32_t init_val)
-{
- __asm__ volatile(
- "crc32cw %w[crc], %w[crc], %w[value]"
- : [crc] "+r" (init_val)
- : [value] "r" (data));
- return init_val;
-}
-
-static inline uint32_t
-crc32c_arm64_u64(uint64_t data, uint32_t init_val)
-{
- __asm__ volatile(
- "crc32cx %w[crc], %w[crc], %x[value]"
- : [crc] "+r" (init_val)
- : [value] "r" (data));
- return init_val;
-}
-
-/**
- * Allow or disallow use of arm64 SIMD instrinsics for CRC32 hash
- * calculation.
- *
- * @param alg
- * An OR of following flags:
- * - (CRC32_SW) Don't use arm64 crc intrinsics
- * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available
- *
- */
-static inline void
-rte_hash_crc_set_alg(uint8_t alg)
-{
- switch (alg) {
- case CRC32_ARM64:
- if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32))
- alg = CRC32_SW;
- /* fall-through */
- case CRC32_SW:
- crc32_alg = alg;
- /* fall-through */
- default:
- break;
- }
-}
-
-/* Setting the best available algorithm */
-RTE_INIT(rte_hash_crc_init_alg)
-{
- rte_hash_crc_set_alg(CRC32_ARM64);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 1 byte value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
-{
- if (likely(crc32_alg & CRC32_ARM64))
- return crc32c_arm64_u8(data, init_val);
-
- return crc32c_1byte(data, init_val);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 2 bytes value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
-{
- if (likely(crc32_alg & CRC32_ARM64))
- return crc32c_arm64_u16(data, init_val);
-
- return crc32c_2bytes(data, init_val);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 4 byte value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
-{
- if (likely(crc32_alg & CRC32_ARM64))
- return crc32c_arm64_u32(data, init_val);
-
- return crc32c_1word(data, init_val);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 8 byte value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
-{
- if (likely(crc32_alg == CRC32_ARM64))
- return crc32c_arm64_u64(data, init_val);
-
- return crc32c_2words(data, init_val);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _RTE_CRC_ARM64_H_ */
diff --git a/lib/hash/rte_hash_crc.h b/lib/hash/rte_hash_crc.h
index 1cc8f84fe2..4e735b3016 100644
--- a/lib/hash/rte_hash_crc.h
+++ b/lib/hash/rte_hash_crc.h
@@ -21,6 +21,12 @@ extern "C" {
#include <rte_branch_prediction.h>
#include <rte_common.h>
+#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+#include "hash_crc_arm64.h"
+#elif defined(RTE_ARCH_X86)
+#include "hash_crc_x86.h"
+#endif
+
#include <hash_crc_sw.h>
#define CRC32_SW (1U << 0)
@@ -31,37 +37,64 @@ extern "C" {
static uint8_t crc32_alg = CRC32_SW;
-#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
-#include "rte_crc_arm64.h"
-#else
-#include "hash_crc_x86.h"
-
/**
- * Allow or disallow use of SSE4.2 instrinsics for CRC32 hash
+ * Allow or disallow use of SSE4.2/ARMv8 intrinsics for CRC32 hash
* calculation.
*
* @param alg
* An OR of following flags:
- * - (CRC32_SW) Don't use SSE4.2 intrinsics
+ * - (CRC32_SW) Don't use SSE4.2/ARMv8 intrinsics (default non-[x86/ARMv8])
* - (CRC32_SSE42) Use SSE4.2 intrinsics if available
- * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default)
+ * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default x86)
+ * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available (default ARMv8)
*
*/
static inline void
rte_hash_crc_set_alg(uint8_t alg)
{
-#if defined(RTE_ARCH_X86)
- if (alg == CRC32_SSE42_x64 &&
- !rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
- alg = CRC32_SSE42;
+ switch (alg) {
+ case CRC32_SSE42_x64:
+ case CRC32_SSE42:
+#if defined RTE_ARCH_X86
+ if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
+ crc32_alg = CRC32_SSE42;
+ else
+ crc32_alg = alg;
+#endif
+#if defined RTE_ARCH_ARM64
+ RTE_LOG(WARNING, HASH,
+ "Incorrect CRC32 algorithm requested setting best available algorithm on the architecture\n");
+ rte_hash_crc_set_alg(CRC32_ARM64);
+#endif
+ break;
+ case CRC32_ARM64:
+#if defined RTE_ARCH_ARM64
+ if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32))
+ crc32_alg = CRC32_ARM64;
#endif
- crc32_alg = alg;
+#if defined RTE_ARCH_X86
+ RTE_LOG(WARNING, HASH,
+ "Incorrect CRC32 algorithm requested setting best available algorithm on the architecture\n");
+ rte_hash_crc_set_alg(CRC32_SSE42_x64);
+#endif
+ break;
+ case CRC32_SW:
+ default:
+ crc32_alg = CRC32_SW;
+ break;
+ }
}
/* Setting the best available algorithm */
RTE_INIT(rte_hash_crc_init_alg)
{
+#if defined(RTE_ARCH_X86)
rte_hash_crc_set_alg(CRC32_SSE42_x64);
+#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ rte_hash_crc_set_alg(CRC32_ARM64);
+#else
+ rte_hash_crc_set_alg(CRC32_SW);
+#endif
}
/**
@@ -82,6 +115,9 @@ rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u8(data, init_val);
+#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ if (likely(crc32_alg & CRC32_ARM64))
+ return crc32c_arm64_u8(data, init_val);
#endif
return crc32c_1byte(data, init_val);
@@ -105,6 +141,9 @@ rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u16(data, init_val);
+#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ if (likely(crc32_alg & CRC32_ARM64))
+ return crc32c_arm64_u16(data, init_val);
#endif
return crc32c_2bytes(data, init_val);
@@ -128,6 +167,9 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u32(data, init_val);
+#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ if (likely(crc32_alg & CRC32_ARM64))
+ return crc32c_arm64_u32(data, init_val);
#endif
return crc32c_1word(data, init_val);
@@ -158,11 +200,14 @@ rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
return crc32c_sse42_u64_mimic(data, init_val);
#endif
+#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ if (likely(crc32_alg & CRC32_ARM64))
+ return crc32c_arm64_u64(data, init_val);
+#endif
+
return crc32c_2words(data, init_val);
}
-#endif
-
/**
* Calculate CRC32 hash on user-supplied byte array.
*
--
2.17.1
next prev parent reply other threads:[~2021-10-03 23:00 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-29 18:05 [dpdk-dev] [RFC] hash: unify crc32 API header for x86 and ARM pbhagavatula
2020-04-30 9:14 ` Van Haaren, Harry
2020-04-30 9:27 ` Pavan Nikhilesh Bhagavatula
2020-05-06 22:02 ` Wang, Yipeng1
2020-05-10 22:49 ` Pavan Nikhilesh Bhagavatula
2020-05-08 12:55 ` Ananyev, Konstantin
2020-05-10 22:53 ` Pavan Nikhilesh Bhagavatula
2020-05-11 9:46 ` Ananyev, Konstantin
2020-05-11 10:23 ` Pavan Nikhilesh Bhagavatula
2020-05-11 10:27 ` Ananyev, Konstantin
2020-05-11 10:57 ` Pavan Nikhilesh Bhagavatula
2020-05-11 12:10 ` Ananyev, Konstantin
2020-05-11 12:32 ` Pavan Nikhilesh Bhagavatula
2020-05-12 20:40 ` [dpdk-dev] [RFC v2] " pbhagavatula
2020-05-13 3:04 ` Ruifeng Wang
2020-05-13 13:22 ` Ananyev, Konstantin
2021-10-03 23:00 ` [dpdk-dev] [PATCH v3 1/2] hash: split x86 and SW hash CRC intrinsics pbhagavatula
2021-10-03 23:00 ` pbhagavatula [this message]
2021-10-04 5:52 ` [dpdk-dev] [PATCH v4 " pbhagavatula
2021-10-04 5:52 ` [dpdk-dev] [PATCH v4 2/2] hash: unify crc32 selection for x86 and Arm pbhagavatula
2021-10-18 9:21 ` Ruifeng Wang
2021-11-05 10:10 ` [dpdk-dev] [PATCH v5 1/2] hash: split x86 and SW hash CRC intrinsics pbhagavatula
2021-11-05 10:10 ` [dpdk-dev] [PATCH v5 2/2] hash: unify crc32 selection for x86 and Arm pbhagavatula
2022-01-04 9:12 ` Ruifeng Wang
2022-04-08 9:16 ` David Marchand
2021-11-16 14:57 ` [dpdk-dev] [PATCH v5 1/2] hash: split x86 and SW hash CRC intrinsics David Marchand
2022-04-27 13:35 ` [PATCH v6 " Pavan Nikhilesh
2022-04-27 13:35 ` [PATCH v6 2/2] hash: unify crc32 selection for x86 and Arm Pavan Nikhilesh
2022-04-27 15:22 ` [PATCH v7 1/2] hash: split x86 and SW hash CRC intrinsics Pavan Nikhilesh
2022-04-27 15:22 ` [PATCH v7 2/2] hash: unify crc32 selection for x86 and Arm Pavan Nikhilesh
2022-04-29 7:19 ` Ruifeng Wang
2022-04-29 7:18 ` [PATCH v7 1/2] hash: split x86 and SW hash CRC intrinsics Ruifeng Wang
2022-04-29 13:29 ` David Marchand
2022-04-29 15:56 ` [EXT] " Pavan Nikhilesh Bhagavatula
2022-04-29 16:16 ` [PATCH v8 " Pavan Nikhilesh
2022-04-29 16:17 ` [PATCH v8 2/2] hash: unify crc32 selection for x86 and Arm Pavan Nikhilesh
2022-05-03 14:33 ` David Marchand
2022-05-04 2:53 ` Wang, Yipeng1
2022-05-11 14:23 ` David Marchand
2022-05-04 2:19 ` [PATCH v8 1/2] hash: split x86 and SW hash CRC intrinsics Wang, Yipeng1
2022-05-13 18:27 ` [PATCH v9 " pbhagavatula
2022-05-13 18:27 ` [PATCH v9 2/2] hash: unify crc32 selection for x86 and Arm pbhagavatula
2022-05-19 14:20 ` David Marchand
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