From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 685A0A0C4B; Mon, 4 Oct 2021 07:53:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 38640412C6; Mon, 4 Oct 2021 07:53:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 50BEF412AC for ; Mon, 4 Oct 2021 07:53:20 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 193Msajl002324; Sun, 3 Oct 2021 22:53:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=y2bytYN3VwIGCvLmCMq9/PCG+gAo22cD2Gu6+o4S8jo=; b=enZdZWOIqKNyYhGur/mXd59sUi1mB2BVtfMZ0fhfrdlSmnIEuskmTs67pINxxIx04Vo2 L5d1eg9KSdn/+gTToqwL1Nfis5RteV+PA4PzA5ouJ6dtZpPfp1OyTyTONzuYfG6TEkBn kKh6arR+G7iqtRz5eLELxK7Z6J5NPLdvNb/8XmapCwE85KcMW4Lc3RFrCpka69feg78h iZUH9MGqmOReuP+HUxVj59KBDUpT2doI06k4Uif9WVFbOX9u+ZE5V11VqkPYFAMd0HYC gctFiAHpAntkiGLY6N/4BGcr0RNXJwcYoasNrHSu4Wjk3Yy5Mxz8HYZC2IrjnoYYZewO ww== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bfc9y9psr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 03 Oct 2021 22:53:17 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 3 Oct 2021 22:53:14 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sun, 3 Oct 2021 22:53:15 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 2DC023F7043; Sun, 3 Oct 2021 22:53:11 -0700 (PDT) From: To: , , , Yipeng Wang , Sameh Gobriel , Bruce Richardson , Vladimir Medvedkin CC: , Pavan Nikhilesh Date: Mon, 4 Oct 2021 11:22:55 +0530 Message-ID: <20211004055255.12947-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211004055255.12947-1-pbhagavatula@marvell.com> References: <20211003230008.12730-1-pbhagavatula@marvell.com> <20211004055255.12947-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 7WGIl7hN4rggX-oG8DAEebOEUDVjiYoU X-Proofpoint-ORIG-GUID: 7WGIl7hN4rggX-oG8DAEebOEUDVjiYoU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-04_01,2021-10-01_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v4 2/2] hash: unify crc32 selection for x86 and Arm X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Merge crc32 hash calculation public API implementation for x86 and Arm. Select the best available CRC32 algorithm when unsupported algorithm on a given CPU architecture is requested by an application. Previously, if an application directly includes `rte_crc_arm64.h` without including `rte_hash_crc.h` it will fail to compile. Signed-off-by: Pavan Nikhilesh --- lib/hash/hash_crc_arm64.h | 48 ++++++++++ lib/hash/meson.build | 1 - lib/hash/rte_crc_arm64.h | 183 -------------------------------------- lib/hash/rte_hash_crc.h | 81 +++++++++++++---- 4 files changed, 112 insertions(+), 201 deletions(-) create mode 100644 lib/hash/hash_crc_arm64.h delete mode 100644 lib/hash/rte_crc_arm64.h diff --git a/lib/hash/hash_crc_arm64.h b/lib/hash/hash_crc_arm64.h new file mode 100644 index 0000000000..29b61a07a9 --- /dev/null +++ b/lib/hash/hash_crc_arm64.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015 Cavium, Inc + */ + +#ifndef _HASH_CRC_ARM64_H_ +#define _HASH_CRC_ARM64_H_ + +static inline uint32_t +crc32c_arm64_u8(uint8_t data, uint32_t init_val) +{ + __asm__ volatile( + "crc32cb %w[crc], %w[crc], %w[value]" + : [crc] "+r" (init_val) + : [value] "r" (data)); + return init_val; +} + +static inline uint32_t +crc32c_arm64_u16(uint16_t data, uint32_t init_val) +{ + __asm__ volatile( + "crc32ch %w[crc], %w[crc], %w[value]" + : [crc] "+r" (init_val) + : [value] "r" (data)); + return init_val; +} + +static inline uint32_t +crc32c_arm64_u32(uint32_t data, uint32_t init_val) +{ + __asm__ volatile( + "crc32cw %w[crc], %w[crc], %w[value]" + : [crc] "+r" (init_val) + : [value] "r" (data)); + return init_val; +} + +static inline uint32_t +crc32c_arm64_u64(uint64_t data, uint32_t init_val) +{ + __asm__ volatile( + "crc32cx %w[crc], %w[crc], %x[value]" + : [crc] "+r" (init_val) + : [value] "r" (data)); + return init_val; +} + +#endif /* _HASH_CRC_ARM64_H_ */ diff --git a/lib/hash/meson.build b/lib/hash/meson.build index 9bc5ef925a..8794ea82a7 100644 --- a/lib/hash/meson.build +++ b/lib/hash/meson.build @@ -8,7 +8,6 @@ headers = files( 'rte_jhash.h', 'rte_thash.h', ) -indirect_headers += files('rte_crc_arm64.h') sources = files('rte_cuckoo_hash.c', 'rte_fbk_hash.c', 'rte_thash.c') deps += ['net'] diff --git a/lib/hash/rte_crc_arm64.h b/lib/hash/rte_crc_arm64.h deleted file mode 100644 index b4628cfc09..0000000000 --- a/lib/hash/rte_crc_arm64.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2015 Cavium, Inc - */ - -#ifndef _RTE_CRC_ARM64_H_ -#define _RTE_CRC_ARM64_H_ - -/** - * @file - * - * RTE CRC arm64 Hash - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include - -static inline uint32_t -crc32c_arm64_u8(uint8_t data, uint32_t init_val) -{ - __asm__ volatile( - "crc32cb %w[crc], %w[crc], %w[value]" - : [crc] "+r" (init_val) - : [value] "r" (data)); - return init_val; -} - -static inline uint32_t -crc32c_arm64_u16(uint16_t data, uint32_t init_val) -{ - __asm__ volatile( - "crc32ch %w[crc], %w[crc], %w[value]" - : [crc] "+r" (init_val) - : [value] "r" (data)); - return init_val; -} - -static inline uint32_t -crc32c_arm64_u32(uint32_t data, uint32_t init_val) -{ - __asm__ volatile( - "crc32cw %w[crc], %w[crc], %w[value]" - : [crc] "+r" (init_val) - : [value] "r" (data)); - return init_val; -} - -static inline uint32_t -crc32c_arm64_u64(uint64_t data, uint32_t init_val) -{ - __asm__ volatile( - "crc32cx %w[crc], %w[crc], %x[value]" - : [crc] "+r" (init_val) - : [value] "r" (data)); - return init_val; -} - -/** - * Allow or disallow use of arm64 SIMD instrinsics for CRC32 hash - * calculation. - * - * @param alg - * An OR of following flags: - * - (CRC32_SW) Don't use arm64 crc intrinsics - * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available - * - */ -static inline void -rte_hash_crc_set_alg(uint8_t alg) -{ - switch (alg) { - case CRC32_ARM64: - if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32)) - alg = CRC32_SW; - /* fall-through */ - case CRC32_SW: - crc32_alg = alg; - /* fall-through */ - default: - break; - } -} - -/* Setting the best available algorithm */ -RTE_INIT(rte_hash_crc_init_alg) -{ - rte_hash_crc_set_alg(CRC32_ARM64); -} - -/** - * Use single crc32 instruction to perform a hash on a 1 byte value. - * Fall back to software crc32 implementation in case arm64 crc intrinsics is - * not supported - * - * @param data - * Data to perform hash on. - * @param init_val - * Value to initialise hash generator. - * @return - * 32bit calculated hash value. - */ -static inline uint32_t -rte_hash_crc_1byte(uint8_t data, uint32_t init_val) -{ - if (likely(crc32_alg & CRC32_ARM64)) - return crc32c_arm64_u8(data, init_val); - - return crc32c_1byte(data, init_val); -} - -/** - * Use single crc32 instruction to perform a hash on a 2 bytes value. - * Fall back to software crc32 implementation in case arm64 crc intrinsics is - * not supported - * - * @param data - * Data to perform hash on. - * @param init_val - * Value to initialise hash generator. - * @return - * 32bit calculated hash value. - */ -static inline uint32_t -rte_hash_crc_2byte(uint16_t data, uint32_t init_val) -{ - if (likely(crc32_alg & CRC32_ARM64)) - return crc32c_arm64_u16(data, init_val); - - return crc32c_2bytes(data, init_val); -} - -/** - * Use single crc32 instruction to perform a hash on a 4 byte value. - * Fall back to software crc32 implementation in case arm64 crc intrinsics is - * not supported - * - * @param data - * Data to perform hash on. - * @param init_val - * Value to initialise hash generator. - * @return - * 32bit calculated hash value. - */ -static inline uint32_t -rte_hash_crc_4byte(uint32_t data, uint32_t init_val) -{ - if (likely(crc32_alg & CRC32_ARM64)) - return crc32c_arm64_u32(data, init_val); - - return crc32c_1word(data, init_val); -} - -/** - * Use single crc32 instruction to perform a hash on a 8 byte value. - * Fall back to software crc32 implementation in case arm64 crc intrinsics is - * not supported - * - * @param data - * Data to perform hash on. - * @param init_val - * Value to initialise hash generator. - * @return - * 32bit calculated hash value. - */ -static inline uint32_t -rte_hash_crc_8byte(uint64_t data, uint32_t init_val) -{ - if (likely(crc32_alg == CRC32_ARM64)) - return crc32c_arm64_u64(data, init_val); - - return crc32c_2words(data, init_val); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _RTE_CRC_ARM64_H_ */ diff --git a/lib/hash/rte_hash_crc.h b/lib/hash/rte_hash_crc.h index 1cc8f84fe2..a51f6d3cc4 100644 --- a/lib/hash/rte_hash_crc.h +++ b/lib/hash/rte_hash_crc.h @@ -16,10 +16,18 @@ extern "C" { #endif #include -#include -#include + #include #include +#include +#include +#include + +#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32) +#include "hash_crc_arm64.h" +#elif defined(RTE_ARCH_X86) +#include "hash_crc_x86.h" +#endif #include @@ -31,37 +39,64 @@ extern "C" { static uint8_t crc32_alg = CRC32_SW; -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32) -#include "rte_crc_arm64.h" -#else -#include "hash_crc_x86.h" - /** - * Allow or disallow use of SSE4.2 instrinsics for CRC32 hash + * Allow or disallow use of SSE4.2/ARMv8 intrinsics for CRC32 hash * calculation. * * @param alg * An OR of following flags: - * - (CRC32_SW) Don't use SSE4.2 intrinsics + * - (CRC32_SW) Don't use SSE4.2/ARMv8 intrinsics (default non-[x86/ARMv8]) * - (CRC32_SSE42) Use SSE4.2 intrinsics if available - * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default) + * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default x86) + * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available (default ARMv8) * */ static inline void rte_hash_crc_set_alg(uint8_t alg) { -#if defined(RTE_ARCH_X86) - if (alg == CRC32_SSE42_x64 && - !rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T)) - alg = CRC32_SSE42; + switch (alg) { + case CRC32_SSE42_x64: + case CRC32_SSE42: +#if defined RTE_ARCH_X86 + if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T)) + crc32_alg = CRC32_SSE42; + else + crc32_alg = alg; +#endif +#if defined RTE_ARCH_ARM64 + RTE_LOG(WARNING, HASH, + "Incorrect CRC32 algorithm requested setting best available algorithm on the architecture\n"); + rte_hash_crc_set_alg(CRC32_ARM64); #endif - crc32_alg = alg; + break; + case CRC32_ARM64: +#if defined RTE_ARCH_ARM64 + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32)) + crc32_alg = CRC32_ARM64; +#endif +#if defined RTE_ARCH_X86 + RTE_LOG(WARNING, HASH, + "Incorrect CRC32 algorithm requested setting best available algorithm on the architecture\n"); + rte_hash_crc_set_alg(CRC32_SSE42_x64); +#endif + break; + case CRC32_SW: + default: + crc32_alg = CRC32_SW; + break; + } } /* Setting the best available algorithm */ RTE_INIT(rte_hash_crc_init_alg) { +#if defined(RTE_ARCH_X86) rte_hash_crc_set_alg(CRC32_SSE42_x64); +#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32) + rte_hash_crc_set_alg(CRC32_ARM64); +#else + rte_hash_crc_set_alg(CRC32_SW); +#endif } /** @@ -82,6 +117,9 @@ rte_hash_crc_1byte(uint8_t data, uint32_t init_val) #if defined RTE_ARCH_X86 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u8(data, init_val); +#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32) + if (likely(crc32_alg & CRC32_ARM64)) + return crc32c_arm64_u8(data, init_val); #endif return crc32c_1byte(data, init_val); @@ -105,6 +143,9 @@ rte_hash_crc_2byte(uint16_t data, uint32_t init_val) #if defined RTE_ARCH_X86 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u16(data, init_val); +#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32) + if (likely(crc32_alg & CRC32_ARM64)) + return crc32c_arm64_u16(data, init_val); #endif return crc32c_2bytes(data, init_val); @@ -128,6 +169,9 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val) #if defined RTE_ARCH_X86 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u32(data, init_val); +#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32) + if (likely(crc32_alg & CRC32_ARM64)) + return crc32c_arm64_u32(data, init_val); #endif return crc32c_1word(data, init_val); @@ -158,11 +202,14 @@ rte_hash_crc_8byte(uint64_t data, uint32_t init_val) return crc32c_sse42_u64_mimic(data, init_val); #endif +#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32) + if (likely(crc32_alg & CRC32_ARM64)) + return crc32c_arm64_u64(data, init_val); +#endif + return crc32c_2words(data, init_val); } -#endif - /** * Calculate CRC32 hash on user-supplied byte array. * -- 2.17.1